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rename CFG_ macros to CONFIG_SYS
[people/ms/u-boot.git] / include / configs / NETTA.h
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04a85b3b
WD		 1/*
2 * (C) Copyright 2000-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
26 * U-Boot port on NetTA4 board
27 */
28
29#ifndef __CONFIG_H
30#define __CONFIG_H
31
32/*
33 * High Level Configuration Options
34 * (easy to change)
35 */
36
37#define CONFIG_MPC885 1 /* This is a MPC885 CPU */
38#define CONFIG_NETTA 1 /* ...on a NetTA board */
39
40#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
41#undef CONFIG_8xx_CONS_SMC2
42#undef CONFIG_8xx_CONS_NONE
43
44#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
45
46/* #define CONFIG_XIN 10000000 */
47#define CONFIG_XIN 50000000
48#define MPC8XX_HZ 120000000
49/* #define MPC8XX_HZ 100000000 */
50/* #define MPC8XX_HZ 50000000 */
51/* #define MPC8XX_HZ 80000000 */
52
53#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ
54
55#if 0
56#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
57#else
58#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
59#endif
60
61#undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */
62
32bf3d14 63#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
04a85b3b
WD		 64
65#undef CONFIG_BOOTARGS
66#define CONFIG_BOOTCOMMAND \
53677ef1 67 "tftpboot; " \
79fa88f3
WD		 68 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
69 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
04a85b3b
WD		 70 "bootm"
71
72#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
6d0f6bcf 73#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
04a85b3b
WD		 74
75#undef CONFIG_WATCHDOG /* watchdog disabled */
76#define CONFIG_HW_WATCHDOG
77
78#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
79
7be044e4
JL		 80/*
81 * BOOTP options
82 */
83#define CONFIG_BOOTP_SUBNETMASK
84#define CONFIG_BOOTP_GATEWAY
85#define CONFIG_BOOTP_HOSTNAME
86#define CONFIG_BOOTP_BOOTPATH
87#define CONFIG_BOOTP_BOOTFILESIZE
88#define CONFIG_BOOTP_NISDOMAIN
89
04a85b3b
WD		 90
91#undef CONFIG_MAC_PARTITION
92#undef CONFIG_DOS_PARTITION
93
94#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
95
53677ef1 96#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */
04a85b3b 97#define FEC_ENET 1 /* eth.c needs it that way... */
6d0f6bcf 98#undef CONFIG_SYS_DISCOVER_PHY /* do not discover phys */
04a85b3b 99#define CONFIG_MII 1
0f3ba7e9 100#define CONFIG_MII_INIT 1
04a85b3b
WD		 101#define CONFIG_RMII 1 /* use RMII interface */
102
103#if defined(CONFIG_NETTA_ISDN)
104#define CONFIG_ETHER_ON_FEC1 1
53677ef1 105#define CONFIG_FEC1_PHY 1 /* phy address of FEC1 */
04a85b3b
WD		 106#define CONFIG_FEC1_PHY_NORXERR 1
107#undef CONFIG_ETHER_ON_FEC2
108#else
109#define CONFIG_ETHER_ON_FEC1 1
53677ef1 110#define CONFIG_FEC1_PHY 8 /* phy address of FEC1 */
04a85b3b
WD		 111#define CONFIG_FEC1_PHY_NORXERR 1
112#define CONFIG_ETHER_ON_FEC2 1
53677ef1 113#define CONFIG_FEC2_PHY 1 /* phy address of FEC2 */
04a85b3b
WD		 114#define CONFIG_FEC2_PHY_NORXERR 1
115#endif
116
117#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */
118
119/* POST support */
6d0f6bcf
JCPV		 120#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
121 CONFIG_SYS_POST_CODEC | \
122 CONFIG_SYS_POST_DSP )
04a85b3b 123
e18a1061
JL		 124
125/*
126 * Command line configuration.
127 */
128#include <config_cmd_default.h>
129
130#define CONFIG_CMD_CDP
131#define CONFIG_CMD_DHCP
132#define CONFIG_CMD_DIAG
133#define CONFIG_CMD_FAT
134#define CONFIG_CMD_IDE
135#define CONFIG_CMD_JFFS2
136#define CONFIG_CMD_MII
137#define CONFIG_CMD_NAND
138#define CONFIG_CMD_NFS
139#define CONFIG_CMD_PCMCIA
140#define CONFIG_CMD_PING
141
04a85b3b
WD		 142
143#define CONFIG_BOARD_EARLY_INIT_F 1
144#define CONFIG_MISC_INIT_R
145
04a85b3b
WD		 146/*
147 * Miscellaneous configurable options
148 */
6d0f6bcf
JCPV		 149#define CONFIG_SYS_LONGHELP /* undef to save memory */
150#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
04a85b3b 151
6d0f6bcf
JCPV		 152#define CONFIG_SYS_HUSH_PARSER 1
153#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
04a85b3b 154
e18a1061 155#if defined(CONFIG_CMD_KGDB)
6d0f6bcf 156#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
04a85b3b 157#else
6d0f6bcf 158#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
04a85b3b 159#endif
6d0f6bcf
JCPV		 160#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
161#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
162#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
04a85b3b 163
6d0f6bcf
JCPV		 164#define CONFIG_SYS_MEMTEST_START 0x0300000 /* memtest works on */
165#define CONFIG_SYS_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */
04a85b3b 166
6d0f6bcf 167#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
04a85b3b 168
6d0f6bcf 169#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
04a85b3b 170
6d0f6bcf 171#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
04a85b3b
WD		 172
173/*
174 * Low Level Configuration Settings
175 * (address mappings, register initial values, etc.)
176 * You should know what you are doing if you make changes here.
177 */
178/*-----------------------------------------------------------------------
179 * Internal Memory Mapped Register
180 */
6d0f6bcf 181#define CONFIG_SYS_IMMR 0xFF000000
04a85b3b
WD		 182
183/*-----------------------------------------------------------------------
184 * Definitions for initial stack pointer and data area (in DPRAM)
185 */
6d0f6bcf
JCPV		 186#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
187#define CONFIG_SYS_INIT_RAM_END 0x3000 /* End of used area in DPRAM */
188#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
189#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
190#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
04a85b3b
WD		 191
192/*-----------------------------------------------------------------------
193 * Start addresses for the final memory configuration
194 * (Set up by the startup code)
6d0f6bcf 195 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
04a85b3b 196 */
6d0f6bcf
JCPV		 197#define CONFIG_SYS_SDRAM_BASE 0x00000000
198#define CONFIG_SYS_FLASH_BASE 0x40000000
04a85b3b 199#if defined(DEBUG)
6d0f6bcf 200#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
04a85b3b 201#else
6d0f6bcf 202#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
04a85b3b 203#endif
6d0f6bcf
JCPV		 204#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
205#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
04a85b3b
WD		 206
207/*
208 * For booting Linux, the board info and command line data
209 * have to be in the first 8 MB of memory, since this is
210 * the maximum mapped by the Linux kernel during initialization.
211 */
6d0f6bcf 212#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
04a85b3b
WD		 213
214/*-----------------------------------------------------------------------
215 * FLASH organization
216 */
6d0f6bcf
JCPV		 217#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
218#define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
04a85b3b 219
6d0f6bcf
JCPV		 220#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
221#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
04a85b3b 222
5a1aceb0 223#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 224#define CONFIG_ENV_SECT_SIZE 0x10000
04a85b3b 225
6d0f6bcf 226#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x60000)
0e8d1586
JCPV		 227#define CONFIG_ENV_OFFSET 0
228#define CONFIG_ENV_SIZE 0x4000
04a85b3b 229
6d0f6bcf 230#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + 0x70000)
0e8d1586
JCPV		 231#define CONFIG_ENV_OFFSET_REDUND 0
232#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
04a85b3b
WD		 233
234/*-----------------------------------------------------------------------
235 * Cache Configuration
236 */
6d0f6bcf 237#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
e18a1061 238#if defined(CONFIG_CMD_KGDB)
6d0f6bcf 239#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
04a85b3b
WD		 240#endif
241
242/*-----------------------------------------------------------------------
243 * SYPCR - System Protection Control 11-9
244 * SYPCR can only be written once after reset!
245 *-----------------------------------------------------------------------
246 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
247 */
248#if defined(CONFIG_WATCHDOG)
6d0f6bcf 249#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
04a85b3b
WD		 250 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
251#else
6d0f6bcf 252#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
04a85b3b
WD		 253#endif
254
255/*-----------------------------------------------------------------------
256 * SIUMCR - SIU Module Configuration 11-6
257 *-----------------------------------------------------------------------
258 * PCMCIA config., multi-function pin tri-state
259 */
260#ifndef CONFIG_CAN_DRIVER
6d0f6bcf 261#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
04a85b3b 262#else /* we must activate GPL5 in the SIUMCR for CAN */
6d0f6bcf 263#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
04a85b3b
WD		 264#endif /* CONFIG_CAN_DRIVER */
265
266/*-----------------------------------------------------------------------
267 * TBSCR - Time Base Status and Control 11-26
268 *-----------------------------------------------------------------------
269 * Clear Reference Interrupt Status, Timebase freezing enabled
270 */
6d0f6bcf 271#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
04a85b3b
WD		 272
273/*-----------------------------------------------------------------------
274 * RTCSC - Real-Time Clock Status and Control Register 11-27
275 *-----------------------------------------------------------------------
276 */
6d0f6bcf 277#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
04a85b3b
WD		 278
279/*-----------------------------------------------------------------------
280 * PISCR - Periodic Interrupt Status and Control 11-31
281 *-----------------------------------------------------------------------
282 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
283 */
6d0f6bcf 284#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
04a85b3b
WD		 285
286/*-----------------------------------------------------------------------
287 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
288 *-----------------------------------------------------------------------
289 * Reset PLL lock status sticky bit, timer expired status bit and timer
290 * interrupt status bit
291 *
292 */
293
294#if CONFIG_XIN == 10000000
295
296#if MPC8XX_HZ == 120000000
6d0f6bcf 297#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
04a85b3b 298 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
53677ef1 299 PLPRCR_TEXPS)
04a85b3b 300#elif MPC8XX_HZ == 100000000
6d0f6bcf 301#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
04a85b3b 302 (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
53677ef1 303 PLPRCR_TEXPS)
04a85b3b 304#elif MPC8XX_HZ == 50000000
6d0f6bcf 305#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
04a85b3b 306 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
53677ef1 307 PLPRCR_TEXPS)
04a85b3b 308#elif MPC8XX_HZ == 25000000
6d0f6bcf 309#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
04a85b3b 310 (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
53677ef1 311 PLPRCR_TEXPS)
04a85b3b 312#elif MPC8XX_HZ == 40000000
6d0f6bcf 313#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
04a85b3b 314 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
53677ef1 315 PLPRCR_TEXPS)
04a85b3b 316#elif MPC8XX_HZ == 75000000
6d0f6bcf 317#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
04a85b3b 318 (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
53677ef1 319 PLPRCR_TEXPS)
04a85b3b
WD		 320#else
321#error unsupported CPU freq for XIN = 10MHz
322#endif
323
324#elif CONFIG_XIN == 50000000
325
326#if MPC8XX_HZ == 120000000
6d0f6bcf 327#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
04a85b3b 328 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
53677ef1 329 PLPRCR_TEXPS)
04a85b3b 330#elif MPC8XX_HZ == 100000000
6d0f6bcf 331#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
04a85b3b 332 (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
53677ef1 333 PLPRCR_TEXPS)
04a85b3b 334#elif MPC8XX_HZ == 80000000
6d0f6bcf 335#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
04a85b3b 336 (0 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
53677ef1 337 PLPRCR_TEXPS)
04a85b3b 338#elif MPC8XX_HZ == 50000000
6d0f6bcf 339#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
04a85b3b 340 (1 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
53677ef1 341 PLPRCR_TEXPS)
04a85b3b
WD		 342#else
343#error unsupported CPU freq for XIN = 50MHz
344#endif
345
346#else
347
348#error unsupported XIN freq
349#endif
350
351
352/*
353 *-----------------------------------------------------------------------
354 * SCCR - System Clock and reset Control Register 15-27
355 *-----------------------------------------------------------------------
356 * Set clock output, timebase and RTC source and divider,
357 * power management and some other internal clocks
79fa88f3
WD		 358 *
359 * Note: When TBS == 0 the timebase is independent of current cpu clock.
04a85b3b
WD		 360 */
361
362#define SCCR_MASK SCCR_EBDF11
363#if MPC8XX_HZ > 66666666
6d0f6bcf 364#define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \
04a85b3b 365 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
79fa88f3 366 SCCR_DFNL111 | SCCR_DFNH000 | SCCR_DFLCD000 | \
04a85b3b
WD		 367 SCCR_DFALCD00 | SCCR_EBDF01)
368#else
6d0f6bcf 369#define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \
04a85b3b 370 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
79fa88f3 371 SCCR_DFNL111 | SCCR_DFNH000 | SCCR_DFLCD000 | \
04a85b3b
WD		 372 SCCR_DFALCD00)
373#endif
374
375/*-----------------------------------------------------------------------
376 *
377 *-----------------------------------------------------------------------
378 *
379 */
6d0f6bcf
JCPV		 380/*#define CONFIG_SYS_DER 0x2002000F*/
381#define CONFIG_SYS_DER 0
04a85b3b
WD		 382
383/*
384 * Init Memory Controller:
385 *
386 * BR0/1 and OR0/1 (FLASH)
387 */
388
389#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
390
391/* used to re-map FLASH both when starting from SRAM or FLASH:
392 * restrict access enough to keep SRAM working (if any)
393 * but not too much to meddle with FLASH accesses
394 */
6d0f6bcf
JCPV		 395#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
396#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
04a85b3b
WD		 397
398/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
6d0f6bcf 399#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX)
04a85b3b 400
6d0f6bcf
JCPV		 401#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
402#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
403#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
04a85b3b
WD		 404
405/*
406 * BR3 and OR3 (SDRAM)
407 *
408 */
409#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */
410#define SDRAM_MAX_SIZE (256 << 20) /* max 256MB per bank */
411
412/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
6d0f6bcf 413#define CONFIG_SYS_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS)
04a85b3b 414
6d0f6bcf
JCPV		 415#define CONFIG_SYS_OR3_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_SDRAM)
416#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_PS_32 | BR_V)
04a85b3b
WD		 417
418/*
419 * Memory Periodic Timer Prescaler
420 */
421
422/*
423 * Memory Periodic Timer Prescaler
424 *
425 * The Divider for PTA (refresh timer) configuration is based on an
426 * example SDRAM configuration (64 MBit, one bank). The adjustment to
427 * the number of chip selects (NCS) and the actually needed refresh
428 * rate is done by setting MPTPR.
429 *
430 * PTA is calculated from
431 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
432 *
433 * gclk CPU clock (not bus clock!)
434 * Trefresh Refresh cycle * 4 (four word bursts used)
435 *
436 * 4096 Rows from SDRAM example configuration
437 * 1000 factor s -> ms
438 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
439 * 4 Number of refresh cycles per period
440 * 64 Refresh cycle in ms per number of rows
441 * --------------------------------------------
442 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
443 *
444 * 50 MHz => 50.000.000 / Divider = 98
445 * 66 Mhz => 66.000.000 / Divider = 129
446 * 80 Mhz => 80.000.000 / Divider = 156
447 */
448
449#if MPC8XX_HZ == 120000000
6d0f6bcf 450#define CONFIG_SYS_MAMR_PTA 234
04a85b3b 451#elif MPC8XX_HZ == 100000000
6d0f6bcf 452#define CONFIG_SYS_MAMR_PTA 195
04a85b3b 453#elif MPC8XX_HZ == 80000000
6d0f6bcf 454#define CONFIG_SYS_MAMR_PTA 156
04a85b3b 455#elif MPC8XX_HZ == 50000000
6d0f6bcf 456#define CONFIG_SYS_MAMR_PTA 98
04a85b3b
WD		 457#else
458#error Unknown frequency
459#endif
460
461
462/*
463 * For 16 MBit, refresh rates could be 31.3 us
464 * (= 64 ms / 2K = 125 / quad bursts).
465 * For a simpler initialization, 15.6 us is used instead.
466 *
6d0f6bcf
JCPV		 467 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
468 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
04a85b3b 469 */
6d0f6bcf
JCPV		 470#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
471#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
04a85b3b
WD		 472
473/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
6d0f6bcf
JCPV		 474#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
475#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
04a85b3b
WD		 476
477/*
478 * MAMR settings for SDRAM
479 */
480
481/* 8 column SDRAM */
6d0f6bcf 482#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
04a85b3b
WD		 483 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
484 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
485
486/* 9 column SDRAM */
6d0f6bcf 487#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
04a85b3b
WD		 488 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
489 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
490
491/*
492 * Internal Definitions
493 *
494 * Boot Flags
495 */
496#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
497#define BOOTFLAG_WARM 0x02 /* Software reboot */
498
04a85b3b
WD		 499#define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */
500
501/***********************************************************************************************************
502
503 Pin definitions:
504
505 +------+----------------+--------+------------------------------------------------------------
506 | # | Name | Type | Comment
507 +------+----------------+--------+------------------------------------------------------------
508 | PA3 | OK_ETH_3V | Input | CISCO Ethernet power OK
509 | | | | (NetRoute: FEC1, TA: FEC2) (0=power OK)
510 | PA6 | P_VCCD1 | Output | TPS2211A PCMCIA
511 | PA7 | DCL1_3V | Periph | IDL1 PCM clock
512 | PA8 | DSP_DR1 | Periph | IDL1 PCM Data Rx
513 | PA9 | L1TXDA | Periph | IDL1 PCM Data Tx
514 | PA10 | P_VCCD0 | Output | TPS2211A PCMCIA
515 | PA12 | P_SHDN | Output | TPS2211A PCMCIA
516 | PA13 | ETH_LOOP | Output | CISCO Loopback remote power
517 | | | | (NetRoute: FEC1, TA: FEC2) (1=NORMAL)
518 | PA14 | P_VPPD0 | Output | TPS2211A PCMCIA
519 | PA15 | P_VPPD1 | Output | TPS2211A PCMCIA
520 | PB14 | SPIEN_FXO | Output | SPI CS for FXO daughter-board
521 | PB15 | SPIEN_S1 | Output | SPI CS for S-interface 1 (NetRoute only)
522 | PB16 | DREQ1 | Output | D channel request for S-interface chip 1.
523 | PB17 | L1ST3 | Periph | IDL1 timeslot enable signal for PPC
524 | PB18 | L1ST2 | Periph | IDL1 timeslot enable signal for PPC
525 | PB19 | SPIEN_S2 | Output | SPI CS for S-interface 2 (NetRoute only)
526 | PB20 | SPIEN_SEEPROM | Output | SPI CS for serial eeprom
527 | PB21 | LEDIO | Output | Led mode indication for PHY
528 | PB22 | UART_CTS | Input | UART CTS
529 | PB23 | UART_RTS | Output | UART RTS
530 | PB24 | UART_RX | Periph | UART Data Rx
531 | PB25 | UART_TX | Periph | UART Data Tx
532 | PB26 | RMII-MDC | Periph | Free for future use (MII mgt clock)
533 | PB27 | RMII-MDIO | Periph | Free for future use (MII mgt data)
534 | PB28 | SPI_RXD_3V | Input | SPI Data Rx
535 | PB29 | SPI_TXD | Output | SPI Data Tx
536 | PB30 | SPI_CLK | Output | SPI Clock
537 | PB31 | RMII1-REFCLK | Periph | RMII reference clock for FEC1
538 | PC4 | PHY1_LINK | Input | PHY link state FEC1 (interrupt)
539 | PC5 | PHY2_LINK | Input | PHY link state FEC2 (interrupt)
540 | PC6 | RMII1-MDINT | Input | PHY prog interrupt FEC1 (interrupt)
541 | PC7 | RMII2-MDINT | Input | PHY prog interrupt FEC1 (interrupt)
542 | PC8 | P_OC | Input | TPS2211A PCMCIA overcurrent (interrupt) (1=OK)
543 | PC9 | COM_HOOK1 | Input | Codec interrupt chip #1 (interrupt)
544 | PC10 | COM_HOOK2 | Input | Codec interrupt chip #2 (interrupt)
545 | PC11 | COM_HOOK4 | Input | Codec interrupt chip #4 (interrupt)
546 | PC12 | COM_HOOK3 | Input | Codec interrupt chip #3 (interrupt)
547 | PC13 | F_RY_BY | Input | NAND ready signal (interrupt)
548 | PC14 | FAN_OK | Input | Fan status signal (interrupt) (1=OK)
549 | PC15 | PC15_DIRECT0 | Periph | PCMCIA DMA request.
550 | PD3 | F_ALE | Output | NAND
551 | PD4 | F_CLE | Output | NAND
552 | PD5 | F_CE | Output | NAND
553 | PD6 | DSP_INT | Output | DSP debug interrupt
554 | PD7 | DSP_RESET | Output | DSP reset
555 | PD8 | RMII_MDC | Periph | MII mgt clock
556 | PD9 | SPIEN_C1 | Output | SPI CS for codec #1
557 | PD10 | SPIEN_C2 | Output | SPI CS for codec #2
558 | PD11 | SPIEN_C3 | Output | SPI CS for codec #3
559 | PD12 | FSC2 | Periph | IDL2 frame sync
560 | PD13 | DGRANT2 | Input | D channel grant from S #2
561 | PD14 | SPIEN_C4 | Output | SPI CS for codec #4
562 | PD15 | TP700 | Output | Testpoint for software debugging
563 | PE14 | RMII2-TXD0 | Periph | FEC2 transmit data
564 | PE15 | RMII2-TXD1 | Periph | FEC2 transmit data
565 | PE16 | RMII2-REFCLK | Periph | TA: RMII ref clock for
566 | | DCL2 | Periph | NetRoute: PCM clock #2
567 | PE17 | TP703 | Output | Testpoint for software debugging
568 | PE18 | DGRANT1 | Input | D channel grant from S #1
569 | PE19 | RMII2-TXEN | Periph | TA: FEC2 tx enable
570 | | PCM2OUT | Periph | NetRoute: Tx data for IDL2
571 | PE20 | FSC1 | Periph | IDL1 frame sync
572 | PE21 | RMII2-RXD0 | Periph | FEC2 receive data
573 | PE22 | RMII2-RXD1 | Periph | FEC2 receive data
574 | PE23 | L1ST1 | Periph | IDL1 timeslot enable signal for PPC
575 | PE24 | U-N1 | Output | Select user/network for S #1 (0=user)
576 | PE25 | U-N2 | Output | Select user/network for S #2 (0=user)
577 | PE26 | RMII2-RXDV | Periph | FEC2 valid
578 | PE27 | DREQ2 | Output | D channel request for S #2.
579 | PE28 | FPGA_DONE | Input | FPGA done signal
580 | PE29 | FPGA_INIT | Output | FPGA init signal
581 | PE30 | UDOUT2_3V | Input | IDL2 PCM input
582 | PE31 | | | Free
583 +------+----------------+--------+---------------------------------------------------
584
585 Chip selects:
586
587 +------+----------------+------------------------------------------------------------
588 | # | Name | Comment
589 +------+----------------+------------------------------------------------------------
590 | CS0 | CS0 | Boot flash
591 | CS1 | CS_FLASH | NAND flash
592 | CS2 | CS_DSP | DSP
593 | CS3 | DCS_DRAM | DRAM
594 | CS4 | CS_ER1 | External output register
595 +------+----------------+------------------------------------------------------------
596
597 Interrupts:
598
599 +------+----------------+------------------------------------------------------------
600 | # | Name | Comment
601 +------+----------------+------------------------------------------------------------
602 | IRQ1 | UINTER_3V | S interupt chips interrupt (common)
603 | IRQ3 | IRQ_DSP | DSP interrupt
604 | IRQ4 | IRQ_DSP1 | Extra DSP interrupt
605 +------+----------------+------------------------------------------------------------
606
607*************************************************************************************************/
608
609#define DSP_SIZE 0x00010000 /* 64K */
610#define NAND_SIZE 0x00010000 /* 64K */
611#define ER_SIZE 0x00010000 /* 64K */
612#define DUMMY_SIZE 0x00010000 /* 64K */
613
614#define DSP_BASE 0xF1000000
615#define NAND_BASE 0xF1010000
616#define ER_BASE 0xF1020000
617#define DUMMY_BASE 0xF1FF0000
618
619/****************************************************************/
620
621/* NAND */
cc4a0cee 622#define CONFIG_NAND_LEGACY
6d0f6bcf 623#define CONFIG_SYS_NAND_BASE NAND_BASE
79fa88f3
WD		 624#define CONFIG_MTD_NAND_VERIFY_WRITE
625#define CONFIG_MTD_NAND_UNSAFE
04a85b3b 626
6d0f6bcf 627#define CONFIG_SYS_MAX_NAND_DEVICE 1
79fa88f3 628/* #define NAND_NO_RB */
04a85b3b
WD		 629
630#define SECTORSIZE 512
631#define ADDR_COLUMN 1
632#define ADDR_PAGE 2
633#define ADDR_COLUMN_PAGE 3
53677ef1 634#define NAND_ChipID_UNKNOWN 0x00
04a85b3b
WD		 635#define NAND_MAX_FLOORS 1
636#define NAND_MAX_CHIPS 1
637
638/* ALE = PD3, CLE = PD4, CE = PD5, F_RY_BY = PC13 */
639#define NAND_DISABLE_CE(nand) \
640 do { \
6d0f6bcf 641 (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) |= (1 << (15 - 5)); \
04a85b3b
WD		 642 } while(0)
643
644#define NAND_ENABLE_CE(nand) \
645 do { \
6d0f6bcf 646 (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) &= ~(1 << (15 - 5)); \
04a85b3b
WD		 647 } while(0)
648
649#define NAND_CTL_CLRALE(nandptr) \
650 do { \
6d0f6bcf 651 (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) &= ~(1 << (15 - 3)); \
04a85b3b
WD		 652 } while(0)
653
654#define NAND_CTL_SETALE(nandptr) \
655 do { \
6d0f6bcf 656 (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) |= (1 << (15 - 3)); \
04a85b3b
WD		 657 } while(0)
658
659#define NAND_CTL_CLRCLE(nandptr) \
660 do { \
6d0f6bcf 661 (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) &= ~(1 << (15 - 4)); \
04a85b3b
WD		 662 } while(0)
663
664#define NAND_CTL_SETCLE(nandptr) \
665 do { \
6d0f6bcf 666 (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) |= (1 << (15 - 4)); \
04a85b3b
WD		 667 } while(0)
668
669#ifndef NAND_NO_RB
670#define NAND_WAIT_READY(nand) \
671 do { \
6d0f6bcf 672 while ((((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat & (1 << (15 - 13))) == 0) { \
04a85b3b
WD		 673 WATCHDOG_RESET(); \
674 } \
675 } while (0)
676#else
677#define NAND_WAIT_READY(nand) udelay(12)
678#endif
679
680#define WRITE_NAND_COMMAND(d, adr) \
681 do { \
682 *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
683 } while(0)
684
685#define WRITE_NAND_ADDRESS(d, adr) \
686 do { \
687 *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
688 } while(0)
689
690#define WRITE_NAND(d, adr) \
691 do { \
692 *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
693 } while(0)
694
695#define READ_NAND(adr) \
696 ((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr)))
697
79fa88f3 698#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
79fa88f3
WD		 699#define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */
700
700a0c64
WD		 701/*
702 * JFFS2 partitions
703 *
704 */
705/* No command line, one static partition, whole device */
706#undef CONFIG_JFFS2_CMDLINE
707#define CONFIG_JFFS2_DEV "nand0"
8f79e4c2 708#define CONFIG_JFFS2_PART_SIZE 0x00100000
700a0c64
WD		 709#define CONFIG_JFFS2_PART_OFFSET 0x00200000
710
711/* mtdparts command line support */
712/* Note: fake mtd_id used, no linux mtd map file */
713/*
714#define CONFIG_JFFS2_CMDLINE
715#define MTDIDS_DEFAULT "nand0=netta-nand"
716#define MTDPARTS_DEFAULT "mtdparts=netta-nand:1m@2m(jffs2)"
717*/
718
79fa88f3
WD		 719/*****************************************************************************/
720
6d0f6bcf
JCPV		 721#define CONFIG_SYS_DIRECT_FLASH_TFTP
722#define CONFIG_SYS_DIRECT_NAND_TFTP
79fa88f3 723
04a85b3b
WD		 724/*****************************************************************************/
725
726#if 1
727/*-----------------------------------------------------------------------
728 * PCMCIA stuff
729 *-----------------------------------------------------------------------
730 */
731
6d0f6bcf
JCPV		 732#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
733#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
734#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
735#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
736#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
737#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
738#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
739#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
04a85b3b
WD		 740
741/*-----------------------------------------------------------------------
742 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
743 *-----------------------------------------------------------------------
744 */
745
746#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
747
748#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
749#undef CONFIG_IDE_LED /* LED for ide not supported */
750#undef CONFIG_IDE_RESET /* reset for ide not supported */
751
6d0f6bcf
JCPV		 752#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
753#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
04a85b3b 754
6d0f6bcf 755#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
04a85b3b 756
6d0f6bcf 757#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
04a85b3b
WD		 758
759/* Offset for data I/O */
6d0f6bcf 760#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
04a85b3b
WD		 761
762/* Offset for normal register accesses */
6d0f6bcf 763#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
04a85b3b
WD		 764
765/* Offset for alternate registers */
6d0f6bcf 766#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
04a85b3b
WD		 767
768#define CONFIG_MAC_PARTITION
769#define CONFIG_DOS_PARTITION
770#endif
771
772/*************************************************************************************************/
773
774#define CONFIG_CDP_DEVICE_ID 20
775#define CONFIG_CDP_DEVICE_ID_PREFIX "NT" /* netta */
776#define CONFIG_CDP_PORT_ID "eth%d"
777#define CONFIG_CDP_CAPABILITIES 0x00000010
778#define CONFIG_CDP_VERSION "u-boot 1.0" " " __DATE__ " " __TIME__
779#define CONFIG_CDP_PLATFORM "Intracom NetTA"
780#define CONFIG_CDP_TRIGGER 0x20020001
781#define CONFIG_CDP_POWER_CONSUMPTION 4300 /* 90 mA @ 48V */
782#define CONFIG_CDP_APPLIANCE_VLAN_TYPE 0x01 /* ipphone? */
783
784/*************************************************************************************************/
785
786#define CONFIG_AUTO_COMPLETE 1
787
788/*************************************************************************************************/
789
c26e454d
WD		 790#define CONFIG_CRC32_VERIFY 1
791
792/*************************************************************************************************/
793
794#define CONFIG_HUSH_OLD_PARSER_COMPATIBLE 1
795
796/*************************************************************************************************/
797
04a85b3b 798#endif /* __CONFIG_H */
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