projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 04a85b3b WD |
1 | /* |
| 2 | * (C) Copyright 2000-2004 | |
| 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
| 4 | * | |
| 5 | * See file CREDITS for list of people who contributed to this | |
| 6 | * project. | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or | |
| 9 | * modify it under the terms of the GNU General Public License as | |
| 10 | * published by the Free Software Foundation; either version 2 of | |
| 11 | * the License, or (at your option) any later version. | |
| 12 | * | |
| 13 | * This program is distributed in the hope that it will be useful, | |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | * GNU General Public License for more details. | |
| 17 | * | |
| 18 | * You should have received a copy of the GNU General Public License | |
| 19 | * along with this program; if not, write to the Free Software | |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 21 | * MA 02111-1307 USA | |
| 22 | */ | |
| 23 | ||
| 24 | /* | |
| 25 | * Pantelis Antoniou, Intracom S.A., panto@intracom.gr | |
| 26 | * U-Boot port on NetTA4 board | |
| 27 | */ | |
| 28 | ||
| 29 | #ifndef __CONFIG_H | |
| 30 | #define __CONFIG_H | |
| 31 | ||
| 32 | /* | |
| 33 | * High Level Configuration Options | |
| 34 | * (easy to change) | |
| 35 | */ | |
| 36 | ||
| 37 | #define CONFIG_MPC885 1 /* This is a MPC885 CPU */ | |
| 38 | #define CONFIG_NETTA 1 /* ...on a NetTA board */ | |
| 39 | ||
| 2ae18241 WD |
40 | #define CONFIG_SYS_TEXT_BASE 0x40000000 |
| 41 | ||
| 04a85b3b WD |
42 | #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
| 43 | #undef CONFIG_8xx_CONS_SMC2 | |
| 44 | #undef CONFIG_8xx_CONS_NONE | |
| 45 | ||
| 46 | #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ | |
| 47 | ||
| 48 | /* #define CONFIG_XIN 10000000 */ | |
| 49 | #define CONFIG_XIN 50000000 | |
| 50 | #define MPC8XX_HZ 120000000 | |
| 51 | /* #define MPC8XX_HZ 100000000 */ | |
| 52 | /* #define MPC8XX_HZ 50000000 */ | |
| 53 | /* #define MPC8XX_HZ 80000000 */ | |
| 54 | ||
| 55 | #define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ | |
| 56 | ||
| 57 | #if 0 | |
| 58 | #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ | |
| 59 | #else | |
| 60 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
| 61 | #endif | |
| 62 | ||
| 63 | #undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */ | |
| 64 | ||
| 32bf3d14 | 65 | #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" |
| 04a85b3b WD |
66 | |
| 67 | #undef CONFIG_BOOTARGS | |
| 68 | #define CONFIG_BOOTCOMMAND \ | |
| 53677ef1 | 69 | "tftpboot; " \ |
| 79fa88f3 WD |
70 | "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ |
| 71 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ | |
| 04a85b3b WD |
72 | "bootm" |
| 73 | ||
| 74 | #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ | |
| 6d0f6bcf | 75 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
| 04a85b3b WD |
76 | |
| 77 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
| 78 | #define CONFIG_HW_WATCHDOG | |
| 79 | ||
| 80 | #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ | |
| 81 | ||
| 7be044e4 JL |
82 | /* |
| 83 | * BOOTP options | |
| 84 | */ | |
| 85 | #define CONFIG_BOOTP_SUBNETMASK | |
| 86 | #define CONFIG_BOOTP_GATEWAY | |
| 87 | #define CONFIG_BOOTP_HOSTNAME | |
| 88 | #define CONFIG_BOOTP_BOOTPATH | |
| 89 | #define CONFIG_BOOTP_BOOTFILESIZE | |
| 90 | #define CONFIG_BOOTP_NISDOMAIN | |
| 91 | ||
| 04a85b3b WD |
92 | |
| 93 | #undef CONFIG_MAC_PARTITION | |
| 94 | #undef CONFIG_DOS_PARTITION | |
| 95 | ||
| 96 | #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ | |
| 97 | ||
| 53677ef1 | 98 | #define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */ |
| 04a85b3b | 99 | #define FEC_ENET 1 /* eth.c needs it that way... */ |
| 6d0f6bcf | 100 | #undef CONFIG_SYS_DISCOVER_PHY /* do not discover phys */ |
| 04a85b3b | 101 | #define CONFIG_MII 1 |
| 0f3ba7e9 | 102 | #define CONFIG_MII_INIT 1 |
| 04a85b3b WD |
103 | #define CONFIG_RMII 1 /* use RMII interface */ |
| 104 | ||
| 105 | #if defined(CONFIG_NETTA_ISDN) | |
| 106 | #define CONFIG_ETHER_ON_FEC1 1 | |
| 53677ef1 | 107 | #define CONFIG_FEC1_PHY 1 /* phy address of FEC1 */ |
| 04a85b3b WD |
108 | #define CONFIG_FEC1_PHY_NORXERR 1 |
| 109 | #undef CONFIG_ETHER_ON_FEC2 | |
| 110 | #else | |
| 111 | #define CONFIG_ETHER_ON_FEC1 1 | |
| 53677ef1 | 112 | #define CONFIG_FEC1_PHY 8 /* phy address of FEC1 */ |
| 04a85b3b WD |
113 | #define CONFIG_FEC1_PHY_NORXERR 1 |
| 114 | #define CONFIG_ETHER_ON_FEC2 1 | |
| 53677ef1 | 115 | #define CONFIG_FEC2_PHY 1 /* phy address of FEC2 */ |
| 04a85b3b WD |
116 | #define CONFIG_FEC2_PHY_NORXERR 1 |
| 117 | #endif | |
| 118 | ||
| 119 | #define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */ | |
| 120 | ||
| 121 | /* POST support */ | |
| 6d0f6bcf JCPV |
122 | #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ |
| 123 | CONFIG_SYS_POST_CODEC | \ | |
| 124 | CONFIG_SYS_POST_DSP ) | |
| 04a85b3b | 125 | |
| e18a1061 JL |
126 | |
| 127 | /* | |
| 128 | * Command line configuration. | |
| 129 | */ | |
| 130 | #include <config_cmd_default.h> | |
| 131 | ||
| 132 | #define CONFIG_CMD_CDP | |
| 133 | #define CONFIG_CMD_DHCP | |
| 134 | #define CONFIG_CMD_DIAG | |
| 135 | #define CONFIG_CMD_FAT | |
| 136 | #define CONFIG_CMD_IDE | |
| 137 | #define CONFIG_CMD_JFFS2 | |
| 138 | #define CONFIG_CMD_MII | |
| e18a1061 JL |
139 | #define CONFIG_CMD_NFS |
| 140 | #define CONFIG_CMD_PCMCIA | |
| 141 | #define CONFIG_CMD_PING | |
| 142 | ||
| 04a85b3b WD |
143 | |
| 144 | #define CONFIG_BOARD_EARLY_INIT_F 1 | |
| 145 | #define CONFIG_MISC_INIT_R | |
| 146 | ||
| 04a85b3b WD |
147 | /* |
| 148 | * Miscellaneous configurable options | |
| 149 | */ | |
| 6d0f6bcf JCPV |
150 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| 151 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
| 04a85b3b | 152 | |
| 6d0f6bcf JCPV |
153 | #define CONFIG_SYS_HUSH_PARSER 1 |
| 154 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
| 04a85b3b | 155 | |
| e18a1061 | 156 | #if defined(CONFIG_CMD_KGDB) |
| 6d0f6bcf | 157 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
| 04a85b3b | 158 | #else |
| 6d0f6bcf | 159 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
| 04a85b3b | 160 | #endif |
| 6d0f6bcf JCPV |
161 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| 162 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
| 163 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
| 04a85b3b | 164 | |
| 6d0f6bcf JCPV |
165 | #define CONFIG_SYS_MEMTEST_START 0x0300000 /* memtest works on */ |
| 166 | #define CONFIG_SYS_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */ | |
| 04a85b3b | 167 | |
| 6d0f6bcf | 168 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
| 04a85b3b | 169 | |
| 6d0f6bcf | 170 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
| 04a85b3b | 171 | |
| 6d0f6bcf | 172 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
| 04a85b3b WD |
173 | |
| 174 | /* | |
| 175 | * Low Level Configuration Settings | |
| 176 | * (address mappings, register initial values, etc.) | |
| 177 | * You should know what you are doing if you make changes here. | |
| 178 | */ | |
| 179 | /*----------------------------------------------------------------------- | |
| 180 | * Internal Memory Mapped Register | |
| 181 | */ | |
| 6d0f6bcf | 182 | #define CONFIG_SYS_IMMR 0xFF000000 |
| 04a85b3b WD |
183 | |
| 184 | /*----------------------------------------------------------------------- | |
| 185 | * Definitions for initial stack pointer and data area (in DPRAM) | |
| 186 | */ | |
| 6d0f6bcf JCPV |
187 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
| 188 | #define CONFIG_SYS_INIT_RAM_END 0x3000 /* End of used area in DPRAM */ | |
| 189 | #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ | |
| 190 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
| 191 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
| 04a85b3b WD |
192 | |
| 193 | /*----------------------------------------------------------------------- | |
| 194 | * Start addresses for the final memory configuration | |
| 195 | * (Set up by the startup code) | |
| 6d0f6bcf | 196 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
| 04a85b3b | 197 | */ |
| 6d0f6bcf JCPV |
198 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
| 199 | #define CONFIG_SYS_FLASH_BASE 0x40000000 | |
| 04a85b3b | 200 | #if defined(DEBUG) |
| 6d0f6bcf | 201 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
| 04a85b3b | 202 | #else |
| 6d0f6bcf | 203 | #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ |
| 04a85b3b | 204 | #endif |
| 6d0f6bcf JCPV |
205 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
| 206 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
| 04a85b3b WD |
207 | |
| 208 | /* | |
| 209 | * For booting Linux, the board info and command line data | |
| 210 | * have to be in the first 8 MB of memory, since this is | |
| 211 | * the maximum mapped by the Linux kernel during initialization. | |
| 212 | */ | |
| 6d0f6bcf | 213 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
| 04a85b3b WD |
214 | |
| 215 | /*----------------------------------------------------------------------- | |
| 216 | * FLASH organization | |
| 217 | */ | |
| 6d0f6bcf JCPV |
218 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
| 219 | #define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ | |
| 04a85b3b | 220 | |
| 6d0f6bcf JCPV |
221 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
| 222 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
| 04a85b3b | 223 | |
| 5a1aceb0 | 224 | #define CONFIG_ENV_IS_IN_FLASH 1 |
| 0e8d1586 | 225 | #define CONFIG_ENV_SECT_SIZE 0x10000 |
| 04a85b3b | 226 | |
| 6d0f6bcf | 227 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x60000) |
| 0e8d1586 JCPV |
228 | #define CONFIG_ENV_OFFSET 0 |
| 229 | #define CONFIG_ENV_SIZE 0x4000 | |
| 04a85b3b | 230 | |
| 6d0f6bcf | 231 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + 0x70000) |
| 0e8d1586 JCPV |
232 | #define CONFIG_ENV_OFFSET_REDUND 0 |
| 233 | #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE | |
| 04a85b3b WD |
234 | |
| 235 | /*----------------------------------------------------------------------- | |
| 236 | * Cache Configuration | |
| 237 | */ | |
| 6d0f6bcf | 238 | #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
| e18a1061 | 239 | #if defined(CONFIG_CMD_KGDB) |
| 6d0f6bcf | 240 | #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
| 04a85b3b WD |
241 | #endif |
| 242 | ||
| 243 | /*----------------------------------------------------------------------- | |
| 244 | * SYPCR - System Protection Control 11-9 | |
| 245 | * SYPCR can only be written once after reset! | |
| 246 | *----------------------------------------------------------------------- | |
| 247 | * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze | |
| 248 | */ | |
| 249 | #if defined(CONFIG_WATCHDOG) | |
| 6d0f6bcf | 250 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
| 04a85b3b WD |
251 | SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
| 252 | #else | |
| 6d0f6bcf | 253 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
| 04a85b3b WD |
254 | #endif |
| 255 | ||
| 256 | /*----------------------------------------------------------------------- | |
| 257 | * SIUMCR - SIU Module Configuration 11-6 | |
| 258 | *----------------------------------------------------------------------- | |
| 259 | * PCMCIA config., multi-function pin tri-state | |
| 260 | */ | |
| 261 | #ifndef CONFIG_CAN_DRIVER | |
| 6d0f6bcf | 262 | #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC) |
| 04a85b3b | 263 | #else /* we must activate GPL5 in the SIUMCR for CAN */ |
| 6d0f6bcf | 264 | #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC) |
| 04a85b3b WD |
265 | #endif /* CONFIG_CAN_DRIVER */ |
| 266 | ||
| 267 | /*----------------------------------------------------------------------- | |
| 268 | * TBSCR - Time Base Status and Control 11-26 | |
| 269 | *----------------------------------------------------------------------- | |
| 270 | * Clear Reference Interrupt Status, Timebase freezing enabled | |
| 271 | */ | |
| 6d0f6bcf | 272 | #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
| 04a85b3b WD |
273 | |
| 274 | /*----------------------------------------------------------------------- | |
| 275 | * RTCSC - Real-Time Clock Status and Control Register 11-27 | |
| 276 | *----------------------------------------------------------------------- | |
| 277 | */ | |
| 6d0f6bcf | 278 | #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) |
| 04a85b3b WD |
279 | |
| 280 | /*----------------------------------------------------------------------- | |
| 281 | * PISCR - Periodic Interrupt Status and Control 11-31 | |
| 282 | *----------------------------------------------------------------------- | |
| 283 | * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled | |
| 284 | */ | |
| 6d0f6bcf | 285 | #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) |
| 04a85b3b WD |
286 | |
| 287 | /*----------------------------------------------------------------------- | |
| 288 | * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 | |
| 289 | *----------------------------------------------------------------------- | |
| 290 | * Reset PLL lock status sticky bit, timer expired status bit and timer | |
| 291 | * interrupt status bit | |
| 292 | * | |
| 293 | */ | |
| 294 | ||
| 295 | #if CONFIG_XIN == 10000000 | |
| 296 | ||
| 297 | #if MPC8XX_HZ == 120000000 | |
| 6d0f6bcf | 298 | #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
| 04a85b3b | 299 | (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ |
| 53677ef1 | 300 | PLPRCR_TEXPS) |
| 04a85b3b | 301 | #elif MPC8XX_HZ == 100000000 |
| 6d0f6bcf | 302 | #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
| 04a85b3b | 303 | (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ |
| 53677ef1 | 304 | PLPRCR_TEXPS) |
| 04a85b3b | 305 | #elif MPC8XX_HZ == 50000000 |
| 6d0f6bcf | 306 | #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
| 04a85b3b | 307 | (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \ |
| 53677ef1 | 308 | PLPRCR_TEXPS) |
| 04a85b3b | 309 | #elif MPC8XX_HZ == 25000000 |
| 6d0f6bcf | 310 | #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
| 04a85b3b | 311 | (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \ |
| 53677ef1 | 312 | PLPRCR_TEXPS) |
| 04a85b3b | 313 | #elif MPC8XX_HZ == 40000000 |
| 6d0f6bcf | 314 | #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
| 04a85b3b | 315 | (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ |
| 53677ef1 | 316 | PLPRCR_TEXPS) |
| 04a85b3b | 317 | #elif MPC8XX_HZ == 75000000 |
| 6d0f6bcf | 318 | #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
| 04a85b3b | 319 | (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ |
| 53677ef1 | 320 | PLPRCR_TEXPS) |
| 04a85b3b WD |
321 | #else |
| 322 | #error unsupported CPU freq for XIN = 10MHz | |
| 323 | #endif | |
| 324 | ||
| 325 | #elif CONFIG_XIN == 50000000 | |
| 326 | ||
| 327 | #if MPC8XX_HZ == 120000000 | |
| 6d0f6bcf | 328 | #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
| 04a85b3b | 329 | (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ |
| 53677ef1 | 330 | PLPRCR_TEXPS) |
| 04a85b3b | 331 | #elif MPC8XX_HZ == 100000000 |
| 6d0f6bcf | 332 | #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
| 04a85b3b | 333 | (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \ |
| 53677ef1 | 334 | PLPRCR_TEXPS) |
| 04a85b3b | 335 | #elif MPC8XX_HZ == 80000000 |
| 6d0f6bcf | 336 | #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
| 04a85b3b | 337 | (0 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ |
| 53677ef1 | 338 | PLPRCR_TEXPS) |
| 04a85b3b | 339 | #elif MPC8XX_HZ == 50000000 |
| 6d0f6bcf | 340 | #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
| 04a85b3b | 341 | (1 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \ |
| 53677ef1 | 342 | PLPRCR_TEXPS) |
| 04a85b3b WD |
343 | #else |
| 344 | #error unsupported CPU freq for XIN = 50MHz | |
| 345 | #endif | |
| 346 | ||
| 347 | #else | |
| 348 | ||
| 349 | #error unsupported XIN freq | |
| 350 | #endif | |
| 351 | ||
| 352 | ||
| 353 | /* | |
| 354 | *----------------------------------------------------------------------- | |
| 355 | * SCCR - System Clock and reset Control Register 15-27 | |
| 356 | *----------------------------------------------------------------------- | |
| 357 | * Set clock output, timebase and RTC source and divider, | |
| 358 | * power management and some other internal clocks | |
| 79fa88f3 WD |
359 | * |
| 360 | * Note: When TBS == 0 the timebase is independent of current cpu clock. | |
| 04a85b3b WD |
361 | */ |
| 362 | ||
| 363 | #define SCCR_MASK SCCR_EBDF11 | |
| 364 | #if MPC8XX_HZ > 66666666 | |
| 6d0f6bcf | 365 | #define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \ |
| 04a85b3b | 366 | SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ |
| 79fa88f3 | 367 | SCCR_DFNL111 | SCCR_DFNH000 | SCCR_DFLCD000 | \ |
| 04a85b3b WD |
368 | SCCR_DFALCD00 | SCCR_EBDF01) |
| 369 | #else | |
| 6d0f6bcf | 370 | #define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \ |
| 04a85b3b | 371 | SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ |
| 79fa88f3 | 372 | SCCR_DFNL111 | SCCR_DFNH000 | SCCR_DFLCD000 | \ |
| 04a85b3b WD |
373 | SCCR_DFALCD00) |
| 374 | #endif | |
| 375 | ||
| 376 | /*----------------------------------------------------------------------- | |
| 377 | * | |
| 378 | *----------------------------------------------------------------------- | |
| 379 | * | |
| 380 | */ | |
| 6d0f6bcf JCPV |
381 | /*#define CONFIG_SYS_DER 0x2002000F*/ |
| 382 | #define CONFIG_SYS_DER 0 | |
| 04a85b3b WD |
383 | |
| 384 | /* | |
| 385 | * Init Memory Controller: | |
| 386 | * | |
| 387 | * BR0/1 and OR0/1 (FLASH) | |
| 388 | */ | |
| 389 | ||
| 390 | #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ | |
| 391 | ||
| 392 | /* used to re-map FLASH both when starting from SRAM or FLASH: | |
| 393 | * restrict access enough to keep SRAM working (if any) | |
| 394 | * but not too much to meddle with FLASH accesses | |
| 395 | */ | |
| 6d0f6bcf JCPV |
396 | #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ |
| 397 | #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ | |
| 04a85b3b WD |
398 | |
| 399 | /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ | |
| 6d0f6bcf | 400 | #define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX) |
| 04a85b3b | 401 | |
| 6d0f6bcf JCPV |
402 | #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
| 403 | #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) | |
| 404 | #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V ) | |
| 04a85b3b WD |
405 | |
| 406 | /* | |
| 407 | * BR3 and OR3 (SDRAM) | |
| 408 | * | |
| 409 | */ | |
| 410 | #define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */ | |
| 411 | #define SDRAM_MAX_SIZE (256 << 20) /* max 256MB per bank */ | |
| 412 | ||
| 413 | /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ | |
| 6d0f6bcf | 414 | #define CONFIG_SYS_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS) |
| 04a85b3b | 415 | |
| 6d0f6bcf JCPV |
416 | #define CONFIG_SYS_OR3_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_SDRAM) |
| 417 | #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_PS_32 | BR_V) | |
| 04a85b3b WD |
418 | |
| 419 | /* | |
| 420 | * Memory Periodic Timer Prescaler | |
| 421 | */ | |
| 422 | ||
| 423 | /* | |
| 424 | * Memory Periodic Timer Prescaler | |
| 425 | * | |
| 426 | * The Divider for PTA (refresh timer) configuration is based on an | |
| 427 | * example SDRAM configuration (64 MBit, one bank). The adjustment to | |
| 428 | * the number of chip selects (NCS) and the actually needed refresh | |
| 429 | * rate is done by setting MPTPR. | |
| 430 | * | |
| 431 | * PTA is calculated from | |
| 432 | * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) | |
| 433 | * | |
| 434 | * gclk CPU clock (not bus clock!) | |
| 435 | * Trefresh Refresh cycle * 4 (four word bursts used) | |
| 436 | * | |
| 437 | * 4096 Rows from SDRAM example configuration | |
| 438 | * 1000 factor s -> ms | |
| 439 | * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration | |
| 440 | * 4 Number of refresh cycles per period | |
| 441 | * 64 Refresh cycle in ms per number of rows | |
| 442 | * -------------------------------------------- | |
| 443 | * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 | |
| 444 | * | |
| 445 | * 50 MHz => 50.000.000 / Divider = 98 | |
| 446 | * 66 Mhz => 66.000.000 / Divider = 129 | |
| 447 | * 80 Mhz => 80.000.000 / Divider = 156 | |
| 448 | */ | |
| 449 | ||
| 450 | #if MPC8XX_HZ == 120000000 | |
| 6d0f6bcf | 451 | #define CONFIG_SYS_MAMR_PTA 234 |
| 04a85b3b | 452 | #elif MPC8XX_HZ == 100000000 |
| 6d0f6bcf | 453 | #define CONFIG_SYS_MAMR_PTA 195 |
| 04a85b3b | 454 | #elif MPC8XX_HZ == 80000000 |
| 6d0f6bcf | 455 | #define CONFIG_SYS_MAMR_PTA 156 |
| 04a85b3b | 456 | #elif MPC8XX_HZ == 50000000 |
| 6d0f6bcf | 457 | #define CONFIG_SYS_MAMR_PTA 98 |
| 04a85b3b WD |
458 | #else |
| 459 | #error Unknown frequency | |
| 460 | #endif | |
| 461 | ||
| 462 | ||
| 463 | /* | |
| 464 | * For 16 MBit, refresh rates could be 31.3 us | |
| 465 | * (= 64 ms / 2K = 125 / quad bursts). | |
| 466 | * For a simpler initialization, 15.6 us is used instead. | |
| 467 | * | |
| 6d0f6bcf JCPV |
468 | * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks |
| 469 | * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank | |
| 04a85b3b | 470 | */ |
| 6d0f6bcf JCPV |
471 | #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ |
| 472 | #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ | |
| 04a85b3b WD |
473 | |
| 474 | /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ | |
| 6d0f6bcf JCPV |
475 | #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ |
| 476 | #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ | |
| 04a85b3b WD |
477 | |
| 478 | /* | |
| 479 | * MAMR settings for SDRAM | |
| 480 | */ | |
| 481 | ||
| 482 | /* 8 column SDRAM */ | |
| 6d0f6bcf | 483 | #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
| 04a85b3b WD |
484 | MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ |
| 485 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
| 486 | ||
| 487 | /* 9 column SDRAM */ | |
| 6d0f6bcf | 488 | #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
| 04a85b3b WD |
489 | MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ |
| 490 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
| 491 | ||
| 04a85b3b WD |
492 | #define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */ |
| 493 | ||
| 494 | /*********************************************************************************************************** | |
| 495 | ||
| 496 | Pin definitions: | |
| 497 | ||
| 498 | +------+----------------+--------+------------------------------------------------------------ | |
| 499 | | # | Name | Type | Comment | |
| 500 | +------+----------------+--------+------------------------------------------------------------ | |
| 501 | | PA3 | OK_ETH_3V | Input | CISCO Ethernet power OK | |
| 502 | | | | | (NetRoute: FEC1, TA: FEC2) (0=power OK) | |
| 503 | | PA6 | P_VCCD1 | Output | TPS2211A PCMCIA | |
| 504 | | PA7 | DCL1_3V | Periph | IDL1 PCM clock | |
| 505 | | PA8 | DSP_DR1 | Periph | IDL1 PCM Data Rx | |
| 506 | | PA9 | L1TXDA | Periph | IDL1 PCM Data Tx | |
| 507 | | PA10 | P_VCCD0 | Output | TPS2211A PCMCIA | |
| 508 | | PA12 | P_SHDN | Output | TPS2211A PCMCIA | |
| 509 | | PA13 | ETH_LOOP | Output | CISCO Loopback remote power | |
| 510 | | | | | (NetRoute: FEC1, TA: FEC2) (1=NORMAL) | |
| 511 | | PA14 | P_VPPD0 | Output | TPS2211A PCMCIA | |
| 512 | | PA15 | P_VPPD1 | Output | TPS2211A PCMCIA | |
| 513 | | PB14 | SPIEN_FXO | Output | SPI CS for FXO daughter-board | |
| 514 | | PB15 | SPIEN_S1 | Output | SPI CS for S-interface 1 (NetRoute only) | |
| 515 | | PB16 | DREQ1 | Output | D channel request for S-interface chip 1. | |
| 516 | | PB17 | L1ST3 | Periph | IDL1 timeslot enable signal for PPC | |
| 517 | | PB18 | L1ST2 | Periph | IDL1 timeslot enable signal for PPC | |
| 518 | | PB19 | SPIEN_S2 | Output | SPI CS for S-interface 2 (NetRoute only) | |
| 519 | | PB20 | SPIEN_SEEPROM | Output | SPI CS for serial eeprom | |
| 520 | | PB21 | LEDIO | Output | Led mode indication for PHY | |
| 521 | | PB22 | UART_CTS | Input | UART CTS | |
| 522 | | PB23 | UART_RTS | Output | UART RTS | |
| 523 | | PB24 | UART_RX | Periph | UART Data Rx | |
| 524 | | PB25 | UART_TX | Periph | UART Data Tx | |
| 525 | | PB26 | RMII-MDC | Periph | Free for future use (MII mgt clock) | |
| 526 | | PB27 | RMII-MDIO | Periph | Free for future use (MII mgt data) | |
| 527 | | PB28 | SPI_RXD_3V | Input | SPI Data Rx | |
| 528 | | PB29 | SPI_TXD | Output | SPI Data Tx | |
| 529 | | PB30 | SPI_CLK | Output | SPI Clock | |
| 530 | | PB31 | RMII1-REFCLK | Periph | RMII reference clock for FEC1 | |
| 531 | | PC4 | PHY1_LINK | Input | PHY link state FEC1 (interrupt) | |
| 532 | | PC5 | PHY2_LINK | Input | PHY link state FEC2 (interrupt) | |
| 533 | | PC6 | RMII1-MDINT | Input | PHY prog interrupt FEC1 (interrupt) | |
| 534 | | PC7 | RMII2-MDINT | Input | PHY prog interrupt FEC1 (interrupt) | |
| 535 | | PC8 | P_OC | Input | TPS2211A PCMCIA overcurrent (interrupt) (1=OK) | |
| 536 | | PC9 | COM_HOOK1 | Input | Codec interrupt chip #1 (interrupt) | |
| 537 | | PC10 | COM_HOOK2 | Input | Codec interrupt chip #2 (interrupt) | |
| 538 | | PC11 | COM_HOOK4 | Input | Codec interrupt chip #4 (interrupt) | |
| 539 | | PC12 | COM_HOOK3 | Input | Codec interrupt chip #3 (interrupt) | |
| 540 | | PC13 | F_RY_BY | Input | NAND ready signal (interrupt) | |
| 541 | | PC14 | FAN_OK | Input | Fan status signal (interrupt) (1=OK) | |
| 542 | | PC15 | PC15_DIRECT0 | Periph | PCMCIA DMA request. | |
| 543 | | PD3 | F_ALE | Output | NAND | |
| 544 | | PD4 | F_CLE | Output | NAND | |
| 545 | | PD5 | F_CE | Output | NAND | |
| 546 | | PD6 | DSP_INT | Output | DSP debug interrupt | |
| 547 | | PD7 | DSP_RESET | Output | DSP reset | |
| 548 | | PD8 | RMII_MDC | Periph | MII mgt clock | |
| 549 | | PD9 | SPIEN_C1 | Output | SPI CS for codec #1 | |
| 550 | | PD10 | SPIEN_C2 | Output | SPI CS for codec #2 | |
| 551 | | PD11 | SPIEN_C3 | Output | SPI CS for codec #3 | |
| 552 | | PD12 | FSC2 | Periph | IDL2 frame sync | |
| 553 | | PD13 | DGRANT2 | Input | D channel grant from S #2 | |
| 554 | | PD14 | SPIEN_C4 | Output | SPI CS for codec #4 | |
| 555 | | PD15 | TP700 | Output | Testpoint for software debugging | |
| 556 | | PE14 | RMII2-TXD0 | Periph | FEC2 transmit data | |
| 557 | | PE15 | RMII2-TXD1 | Periph | FEC2 transmit data | |
| 558 | | PE16 | RMII2-REFCLK | Periph | TA: RMII ref clock for | |
| 559 | | | DCL2 | Periph | NetRoute: PCM clock #2 | |
| 560 | | PE17 | TP703 | Output | Testpoint for software debugging | |
| 561 | | PE18 | DGRANT1 | Input | D channel grant from S #1 | |
| 562 | | PE19 | RMII2-TXEN | Periph | TA: FEC2 tx enable | |
| 563 | | | PCM2OUT | Periph | NetRoute: Tx data for IDL2 | |
| 564 | | PE20 | FSC1 | Periph | IDL1 frame sync | |
| 565 | | PE21 | RMII2-RXD0 | Periph | FEC2 receive data | |
| 566 | | PE22 | RMII2-RXD1 | Periph | FEC2 receive data | |
| 567 | | PE23 | L1ST1 | Periph | IDL1 timeslot enable signal for PPC | |
| 568 | | PE24 | U-N1 | Output | Select user/network for S #1 (0=user) | |
| 569 | | PE25 | U-N2 | Output | Select user/network for S #2 (0=user) | |
| 570 | | PE26 | RMII2-RXDV | Periph | FEC2 valid | |
| 571 | | PE27 | DREQ2 | Output | D channel request for S #2. | |
| 572 | | PE28 | FPGA_DONE | Input | FPGA done signal | |
| 573 | | PE29 | FPGA_INIT | Output | FPGA init signal | |
| 574 | | PE30 | UDOUT2_3V | Input | IDL2 PCM input | |
| 575 | | PE31 | | | Free | |
| 576 | +------+----------------+--------+--------------------------------------------------- | |
| 577 | ||
| 578 | Chip selects: | |
| 579 | ||
| 580 | +------+----------------+------------------------------------------------------------ | |
| 581 | | # | Name | Comment | |
| 582 | +------+----------------+------------------------------------------------------------ | |
| 583 | | CS0 | CS0 | Boot flash | |
| 584 | | CS1 | CS_FLASH | NAND flash | |
| 585 | | CS2 | CS_DSP | DSP | |
| 586 | | CS3 | DCS_DRAM | DRAM | |
| 587 | | CS4 | CS_ER1 | External output register | |
| 588 | +------+----------------+------------------------------------------------------------ | |
| 589 | ||
| 590 | Interrupts: | |
| 591 | ||
| 592 | +------+----------------+------------------------------------------------------------ | |
| 593 | | # | Name | Comment | |
| 594 | +------+----------------+------------------------------------------------------------ | |
| 595 | | IRQ1 | UINTER_3V | S interupt chips interrupt (common) | |
| 596 | | IRQ3 | IRQ_DSP | DSP interrupt | |
| 597 | | IRQ4 | IRQ_DSP1 | Extra DSP interrupt | |
| 598 | +------+----------------+------------------------------------------------------------ | |
| 599 | ||
| 600 | *************************************************************************************************/ | |
| 601 | ||
| 602 | #define DSP_SIZE 0x00010000 /* 64K */ | |
| 603 | #define NAND_SIZE 0x00010000 /* 64K */ | |
| 604 | #define ER_SIZE 0x00010000 /* 64K */ | |
| 605 | #define DUMMY_SIZE 0x00010000 /* 64K */ | |
| 606 | ||
| 607 | #define DSP_BASE 0xF1000000 | |
| 608 | #define NAND_BASE 0xF1010000 | |
| 609 | #define ER_BASE 0xF1020000 | |
| 610 | #define DUMMY_BASE 0xF1FF0000 | |
| 611 | ||
| 79fa88f3 WD |
612 | /*****************************************************************************/ |
| 613 | ||
| 6d0f6bcf JCPV |
614 | #define CONFIG_SYS_DIRECT_FLASH_TFTP |
| 615 | #define CONFIG_SYS_DIRECT_NAND_TFTP | |
| 79fa88f3 | 616 | |
| 04a85b3b WD |
617 | /*****************************************************************************/ |
| 618 | ||
| 619 | #if 1 | |
| 620 | /*----------------------------------------------------------------------- | |
| 621 | * PCMCIA stuff | |
| 622 | *----------------------------------------------------------------------- | |
| 623 | */ | |
| 624 | ||
| 6d0f6bcf JCPV |
625 | #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) |
| 626 | #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) | |
| 627 | #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) | |
| 628 | #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) | |
| 629 | #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) | |
| 630 | #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) | |
| 631 | #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) | |
| 632 | #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) | |
| 04a85b3b WD |
633 | |
| 634 | /*----------------------------------------------------------------------- | |
| 635 | * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) | |
| 636 | *----------------------------------------------------------------------- | |
| 637 | */ | |
| 638 | ||
| 639 | #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ | |
| 640 | ||
| 641 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ | |
| 642 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
| 643 | #undef CONFIG_IDE_RESET /* reset for ide not supported */ | |
| 644 | ||
| 6d0f6bcf JCPV |
645 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
| 646 | #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ | |
| 04a85b3b | 647 | |
| 6d0f6bcf | 648 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
| 04a85b3b | 649 | |
| 6d0f6bcf | 650 | #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR |
| 04a85b3b WD |
651 | |
| 652 | /* Offset for data I/O */ | |
| 6d0f6bcf | 653 | #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
| 04a85b3b WD |
654 | |
| 655 | /* Offset for normal register accesses */ | |
| 6d0f6bcf | 656 | #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
| 04a85b3b WD |
657 | |
| 658 | /* Offset for alternate registers */ | |
| 6d0f6bcf | 659 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 |
| 04a85b3b WD |
660 | |
| 661 | #define CONFIG_MAC_PARTITION | |
| 662 | #define CONFIG_DOS_PARTITION | |
| 663 | #endif | |
| 664 | ||
| 665 | /*************************************************************************************************/ | |
| 666 | ||
| 667 | #define CONFIG_CDP_DEVICE_ID 20 | |
| 668 | #define CONFIG_CDP_DEVICE_ID_PREFIX "NT" /* netta */ | |
| 669 | #define CONFIG_CDP_PORT_ID "eth%d" | |
| 670 | #define CONFIG_CDP_CAPABILITIES 0x00000010 | |
| 561858ee | 671 | #define CONFIG_CDP_VERSION "u-boot 1.0" " " U_BOOT_DATE " " U_BOOT_TIME |
| 04a85b3b WD |
672 | #define CONFIG_CDP_PLATFORM "Intracom NetTA" |
| 673 | #define CONFIG_CDP_TRIGGER 0x20020001 | |
| 674 | #define CONFIG_CDP_POWER_CONSUMPTION 4300 /* 90 mA @ 48V */ | |
| 675 | #define CONFIG_CDP_APPLIANCE_VLAN_TYPE 0x01 /* ipphone? */ | |
| 676 | ||
| 677 | /*************************************************************************************************/ | |
| 678 | ||
| 679 | #define CONFIG_AUTO_COMPLETE 1 | |
| 680 | ||
| 681 | /*************************************************************************************************/ | |
| 682 | ||
| c26e454d WD |
683 | #define CONFIG_CRC32_VERIFY 1 |
| 684 | ||
| 685 | /*************************************************************************************************/ | |
| 686 | ||
| 687 | #define CONFIG_HUSH_OLD_PARSER_COMPATIBLE 1 | |
| 688 | ||
| 689 | /*************************************************************************************************/ | |
| 690 | ||
| 04a85b3b | 691 | #endif /* __CONFIG_H */ |