]>
Commit | Line | Data |
---|---|---|
5b1d7137 | 1 | /* |
cd0402a7 | 2 | * (C) Copyright 2000-2010 |
5b1d7137 WD |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
5b1d7137 WD |
6 | */ |
7 | ||
8 | /* | |
9 | * Pantelis Antoniou, Intracom S.A., panto@intracom.gr | |
10 | * U-Boot port on NetVia board | |
11 | */ | |
12 | ||
13 | #ifndef __CONFIG_H | |
14 | #define __CONFIG_H | |
15 | ||
16 | /* | |
17 | * High Level Configuration Options | |
18 | * (easy to change) | |
19 | */ | |
20 | ||
21 | #define CONFIG_MPC850 1 /* This is a MPC850 CPU */ | |
22 | #define CONFIG_NETVIA 1 /* ...on a NetVia board */ | |
5b1d7137 | 23 | |
2ae18241 WD |
24 | #define CONFIG_SYS_TEXT_BASE 0x40000000 |
25 | ||
993cad93 | 26 | #if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1 |
5b1d7137 WD |
27 | #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
28 | #undef CONFIG_8xx_CONS_SMC2 | |
29 | #undef CONFIG_8xx_CONS_NONE | |
993cad93 WD |
30 | #else |
31 | #define CONFIG_8xx_CONS_NONE | |
32 | #define CONFIG_MAX3100_SERIAL | |
33 | #endif | |
34 | ||
5b1d7137 WD |
35 | #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ |
36 | ||
04a85b3b WD |
37 | #define CONFIG_XIN 10000000 |
38 | #define CONFIG_8xx_GCLK_FREQ 80000000 | |
5b1d7137 WD |
39 | |
40 | #if 0 | |
41 | #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ | |
42 | #else | |
43 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
44 | #endif | |
45 | ||
46 | #undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */ | |
47 | ||
32bf3d14 | 48 | #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" |
5b1d7137 WD |
49 | |
50 | #undef CONFIG_BOOTARGS | |
51 | #define CONFIG_BOOTCOMMAND \ | |
53677ef1 WD |
52 | "tftpboot; " \ |
53 | "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ | |
54 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ | |
5b1d7137 WD |
55 | "bootm" |
56 | ||
57 | #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ | |
6d0f6bcf | 58 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
5b1d7137 WD |
59 | |
60 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
61 | ||
62 | #define CONFIG_STATUS_LED 1 /* Status LED enabled */ | |
63 | ||
993cad93 WD |
64 | #if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 |
65 | #define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */ | |
66 | #endif | |
67 | ||
5b1d7137 WD |
68 | #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ |
69 | ||
7be044e4 JL |
70 | /* |
71 | * BOOTP options | |
72 | */ | |
73 | #define CONFIG_BOOTP_SUBNETMASK | |
74 | #define CONFIG_BOOTP_GATEWAY | |
75 | #define CONFIG_BOOTP_HOSTNAME | |
76 | #define CONFIG_BOOTP_BOOTPATH | |
77 | #define CONFIG_BOOTP_BOOTFILESIZE | |
78 | #define CONFIG_BOOTP_NISDOMAIN | |
79 | ||
5b1d7137 WD |
80 | |
81 | #undef CONFIG_MAC_PARTITION | |
82 | #undef CONFIG_DOS_PARTITION | |
83 | ||
84 | #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ | |
85 | ||
e18a1061 JL |
86 | |
87 | /* | |
88 | * Command line configuration. | |
89 | */ | |
90 | #include <config_cmd_default.h> | |
91 | ||
92 | #define CONFIG_CMD_DHCP | |
93 | #define CONFIG_CMD_PING | |
993cad93 WD |
94 | |
95 | #if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 | |
7640f419 | 96 | /* #define CONFIG_CMD_NAND */ /* disabled */ |
993cad93 | 97 | #endif |
5b1d7137 | 98 | |
e18a1061 | 99 | |
c837dcb1 | 100 | #define CONFIG_BOARD_EARLY_INIT_F 1 |
5b1d7137 WD |
101 | #define CONFIG_MISC_INIT_R |
102 | ||
5b1d7137 WD |
103 | /* |
104 | * Miscellaneous configurable options | |
105 | */ | |
6d0f6bcf | 106 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
e18a1061 | 107 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 108 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
5b1d7137 | 109 | #else |
6d0f6bcf | 110 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
5b1d7137 | 111 | #endif |
6d0f6bcf JCPV |
112 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
113 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
114 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
5b1d7137 | 115 | |
6d0f6bcf JCPV |
116 | #define CONFIG_SYS_MEMTEST_START 0x0300000 /* memtest works on */ |
117 | #define CONFIG_SYS_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */ | |
5b1d7137 | 118 | |
6d0f6bcf | 119 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
5b1d7137 | 120 | |
5b1d7137 WD |
121 | /* |
122 | * Low Level Configuration Settings | |
123 | * (address mappings, register initial values, etc.) | |
124 | * You should know what you are doing if you make changes here. | |
125 | */ | |
126 | /*----------------------------------------------------------------------- | |
127 | * Internal Memory Mapped Register | |
128 | */ | |
6d0f6bcf | 129 | #define CONFIG_SYS_IMMR 0xFF000000 |
5b1d7137 WD |
130 | |
131 | /*----------------------------------------------------------------------- | |
132 | * Definitions for initial stack pointer and data area (in DPRAM) | |
133 | */ | |
6d0f6bcf | 134 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
553f0982 | 135 | #define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */ |
25ddd1fb | 136 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 137 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
5b1d7137 WD |
138 | |
139 | /*----------------------------------------------------------------------- | |
140 | * Start addresses for the final memory configuration | |
141 | * (Set up by the startup code) | |
6d0f6bcf | 142 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
5b1d7137 | 143 | */ |
6d0f6bcf JCPV |
144 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
145 | #define CONFIG_SYS_FLASH_BASE 0x40000000 | |
5b1d7137 | 146 | #if defined(DEBUG) |
6d0f6bcf | 147 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
5b1d7137 | 148 | #else |
6d0f6bcf | 149 | #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ |
5b1d7137 | 150 | #endif |
6d0f6bcf JCPV |
151 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
152 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
5b1d7137 WD |
153 | |
154 | /* | |
155 | * For booting Linux, the board info and command line data | |
156 | * have to be in the first 8 MB of memory, since this is | |
157 | * the maximum mapped by the Linux kernel during initialization. | |
158 | */ | |
6d0f6bcf | 159 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
5b1d7137 WD |
160 | |
161 | /*----------------------------------------------------------------------- | |
162 | * FLASH organization | |
163 | */ | |
6d0f6bcf JCPV |
164 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
165 | #define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ | |
5b1d7137 | 166 | |
6d0f6bcf JCPV |
167 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
168 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
5b1d7137 | 169 | |
5a1aceb0 | 170 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 | 171 | #define CONFIG_ENV_SECT_SIZE 0x10000 |
5b1d7137 | 172 | |
6d0f6bcf | 173 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x60000) |
0e8d1586 | 174 | #define CONFIG_ENV_SIZE 0x4000 |
993cad93 | 175 | |
6d0f6bcf | 176 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + 0x70000) |
0e8d1586 | 177 | #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE |
993cad93 | 178 | |
5b1d7137 WD |
179 | /*----------------------------------------------------------------------- |
180 | * Cache Configuration | |
181 | */ | |
6d0f6bcf | 182 | #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
e18a1061 | 183 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 184 | #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
5b1d7137 WD |
185 | #endif |
186 | ||
187 | /*----------------------------------------------------------------------- | |
188 | * SYPCR - System Protection Control 11-9 | |
189 | * SYPCR can only be written once after reset! | |
190 | *----------------------------------------------------------------------- | |
191 | * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze | |
192 | */ | |
193 | #if defined(CONFIG_WATCHDOG) | |
6d0f6bcf | 194 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
5b1d7137 WD |
195 | SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
196 | #else | |
6d0f6bcf | 197 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
5b1d7137 WD |
198 | #endif |
199 | ||
200 | /*----------------------------------------------------------------------- | |
201 | * SIUMCR - SIU Module Configuration 11-6 | |
202 | *----------------------------------------------------------------------- | |
203 | * PCMCIA config., multi-function pin tri-state | |
204 | */ | |
205 | #ifndef CONFIG_CAN_DRIVER | |
6d0f6bcf | 206 | #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC) |
5b1d7137 | 207 | #else /* we must activate GPL5 in the SIUMCR for CAN */ |
6d0f6bcf | 208 | #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC) |
5b1d7137 WD |
209 | #endif /* CONFIG_CAN_DRIVER */ |
210 | ||
211 | /*----------------------------------------------------------------------- | |
212 | * TBSCR - Time Base Status and Control 11-26 | |
213 | *----------------------------------------------------------------------- | |
214 | * Clear Reference Interrupt Status, Timebase freezing enabled | |
215 | */ | |
6d0f6bcf | 216 | #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
5b1d7137 WD |
217 | |
218 | /*----------------------------------------------------------------------- | |
219 | * RTCSC - Real-Time Clock Status and Control Register 11-27 | |
220 | *----------------------------------------------------------------------- | |
221 | */ | |
6d0f6bcf | 222 | #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) |
5b1d7137 WD |
223 | |
224 | /*----------------------------------------------------------------------- | |
225 | * PISCR - Periodic Interrupt Status and Control 11-31 | |
226 | *----------------------------------------------------------------------- | |
227 | * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled | |
228 | */ | |
6d0f6bcf | 229 | #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) |
5b1d7137 WD |
230 | |
231 | /*----------------------------------------------------------------------- | |
232 | * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 | |
233 | *----------------------------------------------------------------------- | |
234 | * Reset PLL lock status sticky bit, timer expired status bit and timer | |
235 | * interrupt status bit | |
236 | * | |
04a85b3b WD |
237 | * |
238 | *----------------------------------------------------------------------- | |
5b1d7137 WD |
239 | * SCCR - System Clock and reset Control Register 15-27 |
240 | *----------------------------------------------------------------------- | |
241 | * Set clock output, timebase and RTC source and divider, | |
242 | * power management and some other internal clocks | |
243 | */ | |
04a85b3b | 244 | |
5b1d7137 | 245 | #define SCCR_MASK SCCR_EBDF11 |
04a85b3b WD |
246 | |
247 | #if CONFIG_8xx_GCLK_FREQ == 50000000 | |
248 | ||
6d0f6bcf JCPV |
249 | #define CONFIG_SYS_PLPRCR ( ((5 - 1) << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) |
250 | #define CONFIG_SYS_SCCR (SCCR_TBS | \ | |
5b1d7137 WD |
251 | SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ |
252 | SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ | |
253 | SCCR_DFALCD00) | |
254 | ||
04a85b3b WD |
255 | #elif CONFIG_8xx_GCLK_FREQ == 80000000 |
256 | ||
6d0f6bcf JCPV |
257 | #define CONFIG_SYS_PLPRCR ( ((8 - 1) << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) |
258 | #define CONFIG_SYS_SCCR (SCCR_TBS | \ | |
04a85b3b WD |
259 | SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ |
260 | SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ | |
261 | SCCR_DFALCD00 | SCCR_EBDF01) | |
262 | ||
263 | #endif | |
264 | ||
5b1d7137 WD |
265 | /*----------------------------------------------------------------------- |
266 | * | |
267 | *----------------------------------------------------------------------- | |
268 | * | |
269 | */ | |
6d0f6bcf JCPV |
270 | /*#define CONFIG_SYS_DER 0x2002000F*/ |
271 | #define CONFIG_SYS_DER 0 | |
5b1d7137 WD |
272 | |
273 | /* | |
274 | * Init Memory Controller: | |
275 | * | |
276 | * BR0/1 and OR0/1 (FLASH) | |
277 | */ | |
278 | ||
279 | #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ | |
280 | ||
281 | /* used to re-map FLASH both when starting from SRAM or FLASH: | |
282 | * restrict access enough to keep SRAM working (if any) | |
283 | * but not too much to meddle with FLASH accesses | |
284 | */ | |
6d0f6bcf JCPV |
285 | #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ |
286 | #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ | |
5b1d7137 WD |
287 | |
288 | /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ | |
6d0f6bcf | 289 | #define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX) |
5b1d7137 | 290 | |
6d0f6bcf JCPV |
291 | #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
292 | #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) | |
293 | #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V ) | |
5b1d7137 | 294 | |
5b1d7137 WD |
295 | /* |
296 | * BR3 and OR3 (SDRAM) | |
297 | * | |
298 | */ | |
299 | #define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */ | |
300 | #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ | |
301 | ||
302 | /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ | |
6d0f6bcf | 303 | #define CONFIG_SYS_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS) |
5b1d7137 | 304 | |
6d0f6bcf JCPV |
305 | #define CONFIG_SYS_OR3_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_SDRAM) |
306 | #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_PS_32 | BR_V) | |
5b1d7137 | 307 | |
5b1d7137 WD |
308 | /* |
309 | * Memory Periodic Timer Prescaler | |
310 | */ | |
311 | ||
312 | /* periodic timer for refresh */ | |
6d0f6bcf | 313 | #define CONFIG_SYS_MAMR_PTA 208 |
5b1d7137 WD |
314 | |
315 | /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ | |
6d0f6bcf | 316 | #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ |
5b1d7137 WD |
317 | |
318 | /* | |
319 | * MAMR settings for SDRAM | |
320 | */ | |
321 | ||
322 | /* 9 column SDRAM */ | |
6d0f6bcf | 323 | #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
5b1d7137 WD |
324 | MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ |
325 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
326 | ||
5b1d7137 WD |
327 | /* Ethernet at SCC2 */ |
328 | #define CONFIG_SCC2_ENET | |
329 | ||
993cad93 WD |
330 | /****************************************************************/ |
331 | ||
332 | #define DSP_SIZE 0x00010000 /* 64K */ | |
333 | #define FPGA_SIZE 0x00010000 /* 64K */ | |
334 | ||
335 | #define DSP0_BASE 0xF1000000 | |
336 | #define DSP1_BASE (DSP0_BASE + DSP_SIZE) | |
337 | #define FPGA_BASE (DSP1_BASE + DSP_SIZE) | |
338 | ||
339 | #if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 | |
340 | ||
341 | #define ER_SIZE 0x00010000 /* 64K */ | |
342 | #define ER_BASE (FPGA_BASE + FPGA_SIZE) | |
343 | ||
344 | #define NAND_SIZE 0x00010000 /* 64K */ | |
345 | #define NAND_BASE (ER_BASE + ER_SIZE) | |
346 | ||
347 | #endif | |
348 | ||
349 | /****************************************************************/ | |
350 | ||
351 | #if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 | |
352 | ||
353 | #define STATUS_LED_BIT 0x00000001 /* bit 31 */ | |
6d0f6bcf | 354 | #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) |
993cad93 WD |
355 | #define STATUS_LED_STATE STATUS_LED_BLINKING |
356 | ||
357 | #define STATUS_LED_BIT1 0x00000002 /* bit 30 */ | |
6d0f6bcf | 358 | #define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2) |
993cad93 WD |
359 | #define STATUS_LED_STATE1 STATUS_LED_OFF |
360 | ||
361 | #define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */ | |
362 | #define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ | |
363 | ||
364 | #endif | |
365 | ||
993cad93 WD |
366 | |
367 | /*****************************************************************************/ | |
368 | ||
369 | #ifndef __ASSEMBLY__ | |
370 | ||
371 | #if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 | |
372 | ||
373 | /* LEDs */ | |
374 | ||
375 | /* last value written to the external register; we cannot read back */ | |
376 | extern unsigned int last_er_val; | |
377 | ||
378 | /* led_id_t is unsigned long mask */ | |
379 | typedef unsigned int led_id_t; | |
380 | ||
381 | static inline void __led_init(led_id_t mask, int state) | |
382 | { | |
383 | unsigned int new_er_val; | |
384 | ||
385 | if (state) | |
386 | new_er_val = last_er_val & ~mask; | |
387 | else | |
388 | new_er_val = last_er_val | mask; | |
389 | ||
390 | *(volatile unsigned int *)ER_BASE = new_er_val; | |
391 | last_er_val = new_er_val; | |
392 | } | |
393 | ||
394 | static inline void __led_toggle(led_id_t mask) | |
395 | { | |
396 | unsigned int new_er_val; | |
397 | ||
398 | new_er_val = last_er_val ^ mask; | |
399 | *(volatile unsigned int *)ER_BASE = new_er_val; | |
400 | last_er_val = new_er_val; | |
401 | } | |
402 | ||
403 | static inline void __led_set(led_id_t mask, int state) | |
404 | { | |
405 | unsigned int new_er_val; | |
406 | ||
407 | if (state) | |
408 | new_er_val = last_er_val & ~mask; | |
409 | else | |
410 | new_er_val = last_er_val | mask; | |
411 | ||
412 | *(volatile unsigned int *)ER_BASE = new_er_val; | |
413 | last_er_val = new_er_val; | |
414 | } | |
415 | ||
416 | /* MAX3100 console */ | |
6d0f6bcf | 417 | #define MAX3100_SPI_RXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat) |
993cad93 WD |
418 | #define MAX3100_SPI_RXD_BIT 0x00000008 |
419 | ||
6d0f6bcf | 420 | #define MAX3100_SPI_TXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat) |
993cad93 WD |
421 | #define MAX3100_SPI_TXD_BIT 0x00000004 |
422 | ||
6d0f6bcf | 423 | #define MAX3100_SPI_CLK_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat) |
993cad93 WD |
424 | #define MAX3100_SPI_CLK_BIT 0x00000002 |
425 | ||
6d0f6bcf | 426 | #define MAX3100_CS_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) |
993cad93 WD |
427 | #define MAX3100_CS_BIT 0x0010 |
428 | ||
429 | #endif | |
430 | ||
431 | #endif | |
432 | ||
04a85b3b | 433 | /*************************************************************************************************/ |
993cad93 | 434 | |
5b1d7137 | 435 | #endif /* __CONFIG_H */ |