[people/ms/u-boot.git] / include / configs / NETVIA.h

/*
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
 * U-Boot port on NetVia board
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC850		1	/* This is a MPC850 CPU		*/
#define CONFIG_NETVIA		1	/* ...on a NetVia board		*/

#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1
#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
#undef	CONFIG_8xx_CONS_SMC2
#undef	CONFIG_8xx_CONS_NONE
#else
#define CONFIG_8xx_CONS_NONE
#define CONFIG_MAX3100_SERIAL
#endif

#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/

#define CONFIG_XIN		10000000
#define CONFIG_8xx_GCLK_FREQ	80000000

#if 0
#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
#else
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
#endif

#undef	CONFIG_CLOCKS_IN_MHZ	/* clocks NOT passsed to Linux in MHz */

#define CONFIG_PREBOOT	"echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"

#undef	CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND							\
	"tftpboot; "								\
	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
	"bootm"

#define CONFIG_LOADS_ECHO	0	/* echo off for serial download	*/
#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/

#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
#define CONFIG_BOARD_SPECIFIC_LED	/* version has board specific leds */
#endif

#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_NISDOMAIN


#undef CONFIG_MAC_PARTITION
#undef CONFIG_DOS_PARTITION

#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PING

#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
/* #define CONFIG_CMD_NAND */ /* disabled */
#endif


#define CONFIG_BOARD_EARLY_INIT_F 1
#define CONFIG_MISC_INIT_R

/*
 * Miscellaneous configurable options
 */
#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB)
#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x0300000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x0700000	/* 3 ... 7 MB in DRAM	*/

#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/

#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/

#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CONFIG_SYS_IMMR		0xFF000000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
#define	CONFIG_SYS_INIT_RAM_END	0x3000	/* End of used area in DPRAM	*/
#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define	CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH_BASE		0x40000000
#if defined(DEBUG)
#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#else
#define	CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
#endif
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	8	/* max number of sectors on one chip	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define	CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_SECT_SIZE	0x10000

#define	CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x60000)
#define CONFIG_ENV_OFFSET		0
#define	CONFIG_ENV_SIZE		0x4000

#define CONFIG_ENV_ADDR_REDUND	(CONFIG_SYS_FLASH_BASE + 0x70000)
#define CONFIG_ENV_OFFSET_REDUND	0
#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
#endif

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#if defined(CONFIG_WATCHDOG)
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
#else
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				11-6
 *-----------------------------------------------------------------------
 * PCMCIA config., multi-function pin tri-state
 */
#ifndef	CONFIG_CAN_DRIVER
#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
#else	/* we must activate GPL5 in the SIUMCR for CAN */
#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
#endif	/* CONFIG_CAN_DRIVER */

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control				11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)

/*-----------------------------------------------------------------------
 * RTCSC - Real-Time Clock Status and Control Register		11-27
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)

/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
 *-----------------------------------------------------------------------
 * Reset PLL lock status sticky bit, timer expired status bit and timer
 * interrupt status bit
 *
 *
 *-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */

#define SCCR_MASK	SCCR_EBDF11

#if CONFIG_8xx_GCLK_FREQ == 50000000

#define CONFIG_SYS_PLPRCR	( ((5 - 1) << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
#define CONFIG_SYS_SCCR	(SCCR_TBS     | \
			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
			 SCCR_DFALCD00)

#elif CONFIG_8xx_GCLK_FREQ == 80000000

#define CONFIG_SYS_PLPRCR	( ((8 - 1) << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
#define CONFIG_SYS_SCCR	(SCCR_TBS     | \
			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
			 SCCR_DFALCD00 | SCCR_EBDF01)

#endif

/*-----------------------------------------------------------------------
 *
 *-----------------------------------------------------------------------
 *
 */
/*#define	CONFIG_SYS_DER	0x2002000F*/
#define CONFIG_SYS_DER	0

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */

#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/

/* used to re-map FLASH both when starting from SRAM or FLASH:
 * restrict access enough to keep SRAM working (if any)
 * but not too much to meddle with FLASH accesses
 */
#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */

/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1	*/
#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_BI | OR_SCY_5_CLK | OR_TRLX)

#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )

/*
 * BR3 and OR3 (SDRAM)
 *
 */
#define SDRAM_BASE3_PRELIM	0x00000000	/* SDRAM bank #0	*/
#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/

/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
#define CONFIG_SYS_OR_TIMING_SDRAM	(OR_CSNT_SAM | OR_G5LS)

#define CONFIG_SYS_OR3_PRELIM	((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_SDRAM)
#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_PS_32 | BR_V)

/*
 * Memory Periodic Timer Prescaler
 */

/* periodic timer for refresh */
#define CONFIG_SYS_MAMR_PTA	208

/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/

/*
 * MAMR settings for SDRAM
 */

/* 9 column SDRAM */
#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

/* Ethernet at SCC2 */
#define CONFIG_SCC2_ENET

/****************************************************************/

#define DSP_SIZE	0x00010000	/* 64K */
#define FPGA_SIZE	0x00010000	/* 64K */

#define DSP0_BASE	0xF1000000
#define DSP1_BASE	(DSP0_BASE + DSP_SIZE)
#define FPGA_BASE	(DSP1_BASE + DSP_SIZE)

#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2

#define ER_SIZE		0x00010000	/* 64K */
#define ER_BASE		(FPGA_BASE + FPGA_SIZE)

#define NAND_SIZE	0x00010000	/* 64K */
#define NAND_BASE	(ER_BASE + ER_SIZE)

#endif

/****************************************************************/

#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2

#define STATUS_LED_BIT		0x00000001		/* bit 31 */
#define STATUS_LED_PERIOD	(CONFIG_SYS_HZ / 2)
#define STATUS_LED_STATE	STATUS_LED_BLINKING

#define STATUS_LED_BIT1		0x00000002		/* bit 30 */
#define STATUS_LED_PERIOD1	(CONFIG_SYS_HZ / 2)
#define STATUS_LED_STATE1	STATUS_LED_OFF

#define STATUS_LED_ACTIVE	0		/* LED on for bit == 0	*/
#define STATUS_LED_BOOT		0		/* LED 0 used for boot status */

#endif


/*****************************************************************************/

#ifndef __ASSEMBLY__

#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2

/* LEDs */

/* last value written to the external register; we cannot read back */
extern unsigned int last_er_val;

/* led_id_t is unsigned long mask */
typedef unsigned int led_id_t;

static inline void __led_init(led_id_t mask, int state)
{
	unsigned int new_er_val;

	if (state)
		new_er_val = last_er_val & ~mask;
	else
		new_er_val = last_er_val |  mask;

	*(volatile unsigned int *)ER_BASE = new_er_val;
	last_er_val = new_er_val;
}

static inline void __led_toggle(led_id_t mask)
{
	unsigned int new_er_val;

	new_er_val = last_er_val ^ mask;
	*(volatile unsigned int *)ER_BASE = new_er_val;
	last_er_val = new_er_val;
}

static inline void __led_set(led_id_t mask, int state)
{
	unsigned int new_er_val;

	if (state)
		new_er_val = last_er_val & ~mask;
	else
		new_er_val = last_er_val |  mask;

	*(volatile unsigned int *)ER_BASE = new_er_val;
	last_er_val = new_er_val;
}

/* MAX3100 console */
#define MAX3100_SPI_RXD_PORT	(((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
#define MAX3100_SPI_RXD_BIT	0x00000008

#define MAX3100_SPI_TXD_PORT	(((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
#define MAX3100_SPI_TXD_BIT	0x00000004

#define MAX3100_SPI_CLK_PORT	(((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
#define MAX3100_SPI_CLK_BIT	0x00000002

#define MAX3100_CS_PORT		(((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat)
#define MAX3100_CS_BIT		0x0010

#endif

#endif

/*************************************************************************************************/

#endif	/* __CONFIG_H */
Commit	Line	Data
5b1d7137 WD	1	/*
	2	* (C) Copyright 2000
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* Pantelis Antoniou, Intracom S.A., panto@intracom.gr
	26	* U-Boot port on NetVia board
	27	*/
	28
	29	#ifndef __CONFIG_H
	30	#define __CONFIG_H
	31
	32	/*
	33	* High Level Configuration Options
	34	* (easy to change)
	35	*/
	36
	37	#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
	38	#define CONFIG_NETVIA 1 /* ...on a NetVia board */
5b1d7137	39
993cad93	40	#if !defined(CONFIG_NETVIA_VERSION) \|\| CONFIG_NETVIA_VERSION == 1
5b1d7137 WD	41	#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
	42	#undef CONFIG_8xx_CONS_SMC2
	43	#undef CONFIG_8xx_CONS_NONE
993cad93 WD	44	#else
	45	#define CONFIG_8xx_CONS_NONE
	46	#define CONFIG_MAX3100_SERIAL
	47	#endif
	48
5b1d7137 WD	49	#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
5b1d7137 WD	50
04a85b3b WD	51	#define CONFIG_XIN 10000000
04a85b3b WD	52	#define CONFIG_8xx_GCLK_FREQ 80000000
5b1d7137 WD	53
	54	#if 0
	55	#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
	56	#else
	57	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	58	#endif
	59
	60	#undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */
	61
32bf3d14	62	#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
5b1d7137 WD	63
	64	#undef CONFIG_BOOTARGS
	65	#define CONFIG_BOOTCOMMAND \
53677ef1 WD	66	"tftpboot; " \
	67	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
	68	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
5b1d7137 WD	69	"bootm"
	70
	71	#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
6d0f6bcf	72	#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
5b1d7137 WD	73
	74	#undef CONFIG_WATCHDOG /* watchdog disabled */
	75
	76	#define CONFIG_STATUS_LED 1 /* Status LED enabled */
	77
993cad93 WD	78	#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
	79	#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */
	80	#endif
	81
5b1d7137 WD	82	#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
5b1d7137 WD	83
7be044e4 JL	84	/*
	85	* BOOTP options
	86	*/
	87	#define CONFIG_BOOTP_SUBNETMASK
	88	#define CONFIG_BOOTP_GATEWAY
	89	#define CONFIG_BOOTP_HOSTNAME
	90	#define CONFIG_BOOTP_BOOTPATH
	91	#define CONFIG_BOOTP_BOOTFILESIZE
	92	#define CONFIG_BOOTP_NISDOMAIN
	93
5b1d7137 WD	94
	95	#undef CONFIG_MAC_PARTITION
	96	#undef CONFIG_DOS_PARTITION
	97
	98	#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
	99
e18a1061 JL	100
	101	/*
	102	* Command line configuration.
	103	*/
	104	#include <config_cmd_default.h>
	105
	106	#define CONFIG_CMD_DHCP
	107	#define CONFIG_CMD_PING
993cad93 WD	108
993cad93 WD	109	#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
7640f419	110	/* #define CONFIG_CMD_NAND / / disabled */
993cad93	111	#endif
5b1d7137	112
e18a1061	113
c837dcb1	114	#define CONFIG_BOARD_EARLY_INIT_F 1
5b1d7137 WD	115	#define CONFIG_MISC_INIT_R
5b1d7137 WD	116
5b1d7137 WD	117	/*
	118	* Miscellaneous configurable options
	119	*/
6d0f6bcf JCPV	120	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	121	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
e18a1061	122	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	123	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
5b1d7137	124	#else
6d0f6bcf	125	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
5b1d7137	126	#endif
6d0f6bcf JCPV	127	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	128	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	129	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
5b1d7137	130
6d0f6bcf JCPV	131	#define CONFIG_SYS_MEMTEST_START 0x0300000 /* memtest works on */
6d0f6bcf JCPV	132	#define CONFIG_SYS_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */
5b1d7137	133
6d0f6bcf	134	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
5b1d7137	135
6d0f6bcf	136	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
5b1d7137	137
6d0f6bcf	138	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
5b1d7137 WD	139
	140	/*
	141	* Low Level Configuration Settings
	142	* (address mappings, register initial values, etc.)
	143	* You should know what you are doing if you make changes here.
	144	*/
	145	/*-----------------------------------------------------------------------
	146	* Internal Memory Mapped Register
	147	*/
6d0f6bcf	148	#define CONFIG_SYS_IMMR 0xFF000000
5b1d7137 WD	149
	150	/*-----------------------------------------------------------------------
	151	* Definitions for initial stack pointer and data area (in DPRAM)
	152	*/
6d0f6bcf JCPV	153	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
	154	#define CONFIG_SYS_INIT_RAM_END 0x3000 /* End of used area in DPRAM */
	155	#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
	156	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
	157	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
5b1d7137 WD	158
	159	/*-----------------------------------------------------------------------
	160	* Start addresses for the final memory configuration
	161	* (Set up by the startup code)
6d0f6bcf	162	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
5b1d7137	163	*/
6d0f6bcf JCPV	164	#define CONFIG_SYS_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	165	#define CONFIG_SYS_FLASH_BASE 0x40000000
5b1d7137	166	#if defined(DEBUG)
6d0f6bcf	167	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
5b1d7137	168	#else
6d0f6bcf	169	#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
5b1d7137	170	#endif
6d0f6bcf JCPV	171	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
6d0f6bcf JCPV	172	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
5b1d7137 WD	173
	174	/*
	175	* For booting Linux, the board info and command line data
	176	* have to be in the first 8 MB of memory, since this is
	177	* the maximum mapped by the Linux kernel during initialization.
	178	*/
6d0f6bcf	179	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
5b1d7137 WD	180
	181	/*-----------------------------------------------------------------------
	182	* FLASH organization
	183	*/
6d0f6bcf JCPV	184	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
6d0f6bcf JCPV	185	#define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
5b1d7137	186
6d0f6bcf JCPV	187	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	188	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
5b1d7137	189
5a1aceb0	190	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586	191	#define CONFIG_ENV_SECT_SIZE 0x10000
5b1d7137	192
6d0f6bcf	193	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x60000)
0e8d1586 JCPV	194	#define CONFIG_ENV_OFFSET 0
0e8d1586 JCPV	195	#define CONFIG_ENV_SIZE 0x4000
993cad93	196
6d0f6bcf	197	#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + 0x70000)
0e8d1586 JCPV	198	#define CONFIG_ENV_OFFSET_REDUND 0
0e8d1586 JCPV	199	#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
993cad93	200
5b1d7137 WD	201	/*-----------------------------------------------------------------------
	202	* Cache Configuration
	203	*/
6d0f6bcf	204	#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
e18a1061	205	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	206	#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
5b1d7137 WD	207	#endif
	208
	209	/*-----------------------------------------------------------------------
	210	* SYPCR - System Protection Control 11-9
	211	* SYPCR can only be written once after reset!
	212	*-----------------------------------------------------------------------
	213	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
	214	*/
	215	#if defined(CONFIG_WATCHDOG)
6d0f6bcf	216	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
5b1d7137 WD	217	SYPCR_SWE \| SYPCR_SWRI\| SYPCR_SWP)
5b1d7137 WD	218	#else
6d0f6bcf	219	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| SYPCR_SWP)
5b1d7137 WD	220	#endif
	221
	222	/*-----------------------------------------------------------------------
	223	* SIUMCR - SIU Module Configuration 11-6
	224	*-----------------------------------------------------------------------
	225	* PCMCIA config., multi-function pin tri-state
	226	*/
	227	#ifndef CONFIG_CAN_DRIVER
6d0f6bcf	228	#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 \| SIUMCR_DBPC00 \| SIUMCR_MLRC01 \| SIUMCR_FRC)
5b1d7137	229	#else /* we must activate GPL5 in the SIUMCR for CAN */
6d0f6bcf	230	#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 \| SIUMCR_DBPC00 \| SIUMCR_MLRC01 \| SIUMCR_FRC)
5b1d7137 WD	231	#endif /* CONFIG_CAN_DRIVER */
	232
	233	/*-----------------------------------------------------------------------
	234	* TBSCR - Time Base Status and Control 11-26
	235	*-----------------------------------------------------------------------
	236	* Clear Reference Interrupt Status, Timebase freezing enabled
	237	*/
6d0f6bcf	238	#define CONFIG_SYS_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBF)
5b1d7137 WD	239
	240	/*-----------------------------------------------------------------------
	241	* RTCSC - Real-Time Clock Status and Control Register 11-27
	242	*-----------------------------------------------------------------------
	243	*/
6d0f6bcf	244	#define CONFIG_SYS_RTCSC (RTCSC_SEC \| RTCSC_ALR \| RTCSC_RTF\| RTCSC_RTE)
5b1d7137 WD	245
	246	/*-----------------------------------------------------------------------
	247	* PISCR - Periodic Interrupt Status and Control 11-31
	248	*-----------------------------------------------------------------------
	249	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
	250	*/
6d0f6bcf	251	#define CONFIG_SYS_PISCR (PISCR_PS \| PISCR_PITF)
5b1d7137 WD	252
	253	/*-----------------------------------------------------------------------
	254	* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
	255	*-----------------------------------------------------------------------
	256	* Reset PLL lock status sticky bit, timer expired status bit and timer
	257	* interrupt status bit
	258	*
04a85b3b WD	259	*
04a85b3b WD	260	*-----------------------------------------------------------------------
5b1d7137 WD	261	* SCCR - System Clock and reset Control Register 15-27
	262	*-----------------------------------------------------------------------
	263	* Set clock output, timebase and RTC source and divider,
	264	* power management and some other internal clocks
	265	*/
04a85b3b	266
5b1d7137	267	#define SCCR_MASK SCCR_EBDF11
04a85b3b WD	268
	269	#if CONFIG_8xx_GCLK_FREQ == 50000000
	270
6d0f6bcf JCPV	271	#define CONFIG_SYS_PLPRCR ( ((5 - 1) << PLPRCR_MF_SHIFT) \| PLPRCR_SPLSS \| PLPRCR_TEXPS \| PLPRCR_TMIST)
6d0f6bcf JCPV	272	#define CONFIG_SYS_SCCR (SCCR_TBS \| \
5b1d7137 WD	273	SCCR_COM00 \| SCCR_DFSYNC00 \| SCCR_DFBRG00 \| \
	274	SCCR_DFNL000 \| SCCR_DFNH000 \| SCCR_DFLCD000 \| \
	275	SCCR_DFALCD00)
	276
04a85b3b WD	277	#elif CONFIG_8xx_GCLK_FREQ == 80000000
04a85b3b WD	278
6d0f6bcf JCPV	279	#define CONFIG_SYS_PLPRCR ( ((8 - 1) << PLPRCR_MF_SHIFT) \| PLPRCR_SPLSS \| PLPRCR_TEXPS \| PLPRCR_TMIST)
6d0f6bcf JCPV	280	#define CONFIG_SYS_SCCR (SCCR_TBS \| \
04a85b3b WD	281	SCCR_COM00 \| SCCR_DFSYNC00 \| SCCR_DFBRG00 \| \
	282	SCCR_DFNL000 \| SCCR_DFNH000 \| SCCR_DFLCD000 \| \
	283	SCCR_DFALCD00 \| SCCR_EBDF01)
	284
	285	#endif
	286
5b1d7137 WD	287	/*-----------------------------------------------------------------------
	288	*
	289	*-----------------------------------------------------------------------
	290	*
	291	*/
6d0f6bcf JCPV	292	/#define CONFIG_SYS_DER 0x2002000F/
6d0f6bcf JCPV	293	#define CONFIG_SYS_DER 0
5b1d7137 WD	294
	295	/*
	296	* Init Memory Controller:
	297	*
	298	* BR0/1 and OR0/1 (FLASH)
	299	*/
	300
	301	#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
	302
	303	/* used to re-map FLASH both when starting from SRAM or FLASH:
	304	* restrict access enough to keep SRAM working (if any)
	305	* but not too much to meddle with FLASH accesses
	306	*/
6d0f6bcf JCPV	307	#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
6d0f6bcf JCPV	308	#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
5b1d7137 WD	309
5b1d7137 WD	310	/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
6d0f6bcf	311	#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM \| OR_BI \| OR_SCY_5_CLK \| OR_TRLX)
5b1d7137	312
6d0f6bcf JCPV	313	#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM \| CONFIG_SYS_OR_TIMING_FLASH)
	314	#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \| CONFIG_SYS_OR_TIMING_FLASH)
	315	#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) \| BR_PS_8 \| BR_V )
5b1d7137	316
5b1d7137 WD	317	/*
	318	* BR3 and OR3 (SDRAM)
	319	*
	320	*/
	321	#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */
	322	#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
	323
	324	/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
6d0f6bcf	325	#define CONFIG_SYS_OR_TIMING_SDRAM (OR_CSNT_SAM \| OR_G5LS)
5b1d7137	326
6d0f6bcf JCPV	327	#define CONFIG_SYS_OR3_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) \| CONFIG_SYS_OR_TIMING_SDRAM)
6d0f6bcf JCPV	328	#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) \| BR_MS_UPMA \| BR_PS_32 \| BR_V)
5b1d7137	329
5b1d7137 WD	330	/*
	331	* Memory Periodic Timer Prescaler
	332	*/
	333
	334	/* periodic timer for refresh */
6d0f6bcf	335	#define CONFIG_SYS_MAMR_PTA 208
5b1d7137 WD	336
5b1d7137 WD	337	/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
6d0f6bcf	338	#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
5b1d7137 WD	339
	340	/*
	341	* MAMR settings for SDRAM
	342	*/
	343
	344	/* 9 column SDRAM */
6d0f6bcf	345	#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
5b1d7137 WD	346	MAMR_AMA_TYPE_1 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A10 \| \
	347	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
	348
	349	/*
	350	* Internal Definitions
	351	*
	352	* Boot Flags
	353	*/
	354	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	355	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	356
	357	/* Ethernet at SCC2 */
	358	#define CONFIG_SCC2_ENET
	359
993cad93 WD	360	/****************************************************************/
	361
	362	#define DSP_SIZE 0x00010000 /* 64K */
	363	#define FPGA_SIZE 0x00010000 /* 64K */
	364
	365	#define DSP0_BASE 0xF1000000
	366	#define DSP1_BASE (DSP0_BASE + DSP_SIZE)
	367	#define FPGA_BASE (DSP1_BASE + DSP_SIZE)
	368
	369	#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
	370
	371	#define ER_SIZE 0x00010000 /* 64K */
	372	#define ER_BASE (FPGA_BASE + FPGA_SIZE)
	373
	374	#define NAND_SIZE 0x00010000 /* 64K */
	375	#define NAND_BASE (ER_BASE + ER_SIZE)
	376
	377	#endif
	378
	379	/****************************************************************/
	380
	381	#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
	382
	383	#define STATUS_LED_BIT 0x00000001 /* bit 31 */
6d0f6bcf	384	#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
993cad93 WD	385	#define STATUS_LED_STATE STATUS_LED_BLINKING
	386
	387	#define STATUS_LED_BIT1 0x00000002 /* bit 30 */
6d0f6bcf	388	#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
993cad93 WD	389	#define STATUS_LED_STATE1 STATUS_LED_OFF
	390
	391	#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
	392	#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
	393
	394	#endif
	395
993cad93 WD	396
	397	/*****************************************************************************/
	398
	399	#ifndef __ASSEMBLY__
	400
	401	#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
	402
	403	/* LEDs */
	404
	405	/* last value written to the external register; we cannot read back */
	406	extern unsigned int last_er_val;
	407
	408	/* led_id_t is unsigned long mask */
	409	typedef unsigned int led_id_t;
	410
	411	static inline void __led_init(led_id_t mask, int state)
	412	{
	413	unsigned int new_er_val;
	414
	415	if (state)
	416	new_er_val = last_er_val & ~mask;
	417	else
	418	new_er_val = last_er_val \| mask;
	419
	420	(volatile unsigned int )ER_BASE = new_er_val;
	421	last_er_val = new_er_val;
	422	}
	423
	424	static inline void __led_toggle(led_id_t mask)
	425	{
	426	unsigned int new_er_val;
	427
	428	new_er_val = last_er_val ^ mask;
	429	(volatile unsigned int )ER_BASE = new_er_val;
	430	last_er_val = new_er_val;
	431	}
	432
	433	static inline void __led_set(led_id_t mask, int state)
	434	{
	435	unsigned int new_er_val;
	436
	437	if (state)
	438	new_er_val = last_er_val & ~mask;
	439	else
	440	new_er_val = last_er_val \| mask;
	441
	442	(volatile unsigned int )ER_BASE = new_er_val;
	443	last_er_val = new_er_val;
	444	}
	445
	446	/* MAX3100 console */
6d0f6bcf	447	#define MAX3100_SPI_RXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
993cad93 WD	448	#define MAX3100_SPI_RXD_BIT 0x00000008
993cad93 WD	449
6d0f6bcf	450	#define MAX3100_SPI_TXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
993cad93 WD	451	#define MAX3100_SPI_TXD_BIT 0x00000004
993cad93 WD	452
6d0f6bcf	453	#define MAX3100_SPI_CLK_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
993cad93 WD	454	#define MAX3100_SPI_CLK_BIT 0x00000002
993cad93 WD	455
6d0f6bcf	456	#define MAX3100_CS_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat)
993cad93 WD	457	#define MAX3100_CS_BIT 0x0010
	458
	459	#endif
	460
	461	#endif
	462
04a85b3b	463	/*************************************************************************************************/
993cad93	464
5b1d7137	465	#endif /* __CONFIG_H */