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5b1d7137 | 1 | /* |
cd0402a7 | 2 | * (C) Copyright 2000-2010 |
5b1d7137 WD |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
5b1d7137 WD |
6 | */ |
7 | ||
8 | /* | |
9 | * Pantelis Antoniou, Intracom S.A., panto@intracom.gr | |
10 | * U-Boot port on NetVia board | |
11 | */ | |
12 | ||
13 | #ifndef __CONFIG_H | |
14 | #define __CONFIG_H | |
15 | ||
16 | /* | |
17 | * High Level Configuration Options | |
18 | * (easy to change) | |
19 | */ | |
20 | ||
21 | #define CONFIG_MPC850 1 /* This is a MPC850 CPU */ | |
22 | #define CONFIG_NETVIA 1 /* ...on a NetVia board */ | |
5b1d7137 | 23 | |
2ae18241 WD |
24 | #define CONFIG_SYS_TEXT_BASE 0x40000000 |
25 | ||
993cad93 | 26 | #if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1 |
5b1d7137 WD |
27 | #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
28 | #undef CONFIG_8xx_CONS_SMC2 | |
29 | #undef CONFIG_8xx_CONS_NONE | |
993cad93 WD |
30 | #else |
31 | #define CONFIG_8xx_CONS_NONE | |
32 | #define CONFIG_MAX3100_SERIAL | |
33 | #endif | |
34 | ||
5b1d7137 WD |
35 | #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ |
36 | ||
04a85b3b WD |
37 | #define CONFIG_XIN 10000000 |
38 | #define CONFIG_8xx_GCLK_FREQ 80000000 | |
5b1d7137 WD |
39 | |
40 | #if 0 | |
41 | #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ | |
42 | #else | |
43 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
44 | #endif | |
45 | ||
46 | #undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */ | |
47 | ||
32bf3d14 | 48 | #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" |
5b1d7137 WD |
49 | |
50 | #undef CONFIG_BOOTARGS | |
51 | #define CONFIG_BOOTCOMMAND \ | |
53677ef1 WD |
52 | "tftpboot; " \ |
53 | "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ | |
54 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ | |
5b1d7137 WD |
55 | "bootm" |
56 | ||
57 | #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ | |
6d0f6bcf | 58 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
5b1d7137 WD |
59 | |
60 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
61 | ||
62 | #define CONFIG_STATUS_LED 1 /* Status LED enabled */ | |
63 | ||
993cad93 WD |
64 | #if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 |
65 | #define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */ | |
66 | #endif | |
67 | ||
5b1d7137 WD |
68 | #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ |
69 | ||
7be044e4 JL |
70 | /* |
71 | * BOOTP options | |
72 | */ | |
73 | #define CONFIG_BOOTP_SUBNETMASK | |
74 | #define CONFIG_BOOTP_GATEWAY | |
75 | #define CONFIG_BOOTP_HOSTNAME | |
76 | #define CONFIG_BOOTP_BOOTPATH | |
77 | #define CONFIG_BOOTP_BOOTFILESIZE | |
78 | #define CONFIG_BOOTP_NISDOMAIN | |
79 | ||
5b1d7137 WD |
80 | |
81 | #undef CONFIG_MAC_PARTITION | |
82 | #undef CONFIG_DOS_PARTITION | |
83 | ||
84 | #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ | |
85 | ||
e18a1061 JL |
86 | |
87 | /* | |
88 | * Command line configuration. | |
89 | */ | |
90 | #include <config_cmd_default.h> | |
91 | ||
92 | #define CONFIG_CMD_DHCP | |
93 | #define CONFIG_CMD_PING | |
993cad93 WD |
94 | |
95 | #if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 | |
7640f419 | 96 | /* #define CONFIG_CMD_NAND */ /* disabled */ |
993cad93 | 97 | #endif |
5b1d7137 | 98 | |
e18a1061 | 99 | |
c837dcb1 | 100 | #define CONFIG_BOARD_EARLY_INIT_F 1 |
5b1d7137 WD |
101 | #define CONFIG_MISC_INIT_R |
102 | ||
5b1d7137 WD |
103 | /* |
104 | * Miscellaneous configurable options | |
105 | */ | |
6d0f6bcf JCPV |
106 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
107 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
e18a1061 | 108 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 109 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
5b1d7137 | 110 | #else |
6d0f6bcf | 111 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
5b1d7137 | 112 | #endif |
6d0f6bcf JCPV |
113 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
114 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
115 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
5b1d7137 | 116 | |
6d0f6bcf JCPV |
117 | #define CONFIG_SYS_MEMTEST_START 0x0300000 /* memtest works on */ |
118 | #define CONFIG_SYS_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */ | |
5b1d7137 | 119 | |
6d0f6bcf | 120 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
5b1d7137 | 121 | |
6d0f6bcf | 122 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
5b1d7137 | 123 | |
5b1d7137 WD |
124 | /* |
125 | * Low Level Configuration Settings | |
126 | * (address mappings, register initial values, etc.) | |
127 | * You should know what you are doing if you make changes here. | |
128 | */ | |
129 | /*----------------------------------------------------------------------- | |
130 | * Internal Memory Mapped Register | |
131 | */ | |
6d0f6bcf | 132 | #define CONFIG_SYS_IMMR 0xFF000000 |
5b1d7137 WD |
133 | |
134 | /*----------------------------------------------------------------------- | |
135 | * Definitions for initial stack pointer and data area (in DPRAM) | |
136 | */ | |
6d0f6bcf | 137 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
553f0982 | 138 | #define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */ |
25ddd1fb | 139 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 140 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
5b1d7137 WD |
141 | |
142 | /*----------------------------------------------------------------------- | |
143 | * Start addresses for the final memory configuration | |
144 | * (Set up by the startup code) | |
6d0f6bcf | 145 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
5b1d7137 | 146 | */ |
6d0f6bcf JCPV |
147 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
148 | #define CONFIG_SYS_FLASH_BASE 0x40000000 | |
5b1d7137 | 149 | #if defined(DEBUG) |
6d0f6bcf | 150 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
5b1d7137 | 151 | #else |
6d0f6bcf | 152 | #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ |
5b1d7137 | 153 | #endif |
6d0f6bcf JCPV |
154 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
155 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
5b1d7137 WD |
156 | |
157 | /* | |
158 | * For booting Linux, the board info and command line data | |
159 | * have to be in the first 8 MB of memory, since this is | |
160 | * the maximum mapped by the Linux kernel during initialization. | |
161 | */ | |
6d0f6bcf | 162 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
5b1d7137 WD |
163 | |
164 | /*----------------------------------------------------------------------- | |
165 | * FLASH organization | |
166 | */ | |
6d0f6bcf JCPV |
167 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
168 | #define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ | |
5b1d7137 | 169 | |
6d0f6bcf JCPV |
170 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
171 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
5b1d7137 | 172 | |
5a1aceb0 | 173 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 | 174 | #define CONFIG_ENV_SECT_SIZE 0x10000 |
5b1d7137 | 175 | |
6d0f6bcf | 176 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x60000) |
0e8d1586 | 177 | #define CONFIG_ENV_SIZE 0x4000 |
993cad93 | 178 | |
6d0f6bcf | 179 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + 0x70000) |
0e8d1586 | 180 | #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE |
993cad93 | 181 | |
5b1d7137 WD |
182 | /*----------------------------------------------------------------------- |
183 | * Cache Configuration | |
184 | */ | |
6d0f6bcf | 185 | #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
e18a1061 | 186 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 187 | #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
5b1d7137 WD |
188 | #endif |
189 | ||
190 | /*----------------------------------------------------------------------- | |
191 | * SYPCR - System Protection Control 11-9 | |
192 | * SYPCR can only be written once after reset! | |
193 | *----------------------------------------------------------------------- | |
194 | * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze | |
195 | */ | |
196 | #if defined(CONFIG_WATCHDOG) | |
6d0f6bcf | 197 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
5b1d7137 WD |
198 | SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
199 | #else | |
6d0f6bcf | 200 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
5b1d7137 WD |
201 | #endif |
202 | ||
203 | /*----------------------------------------------------------------------- | |
204 | * SIUMCR - SIU Module Configuration 11-6 | |
205 | *----------------------------------------------------------------------- | |
206 | * PCMCIA config., multi-function pin tri-state | |
207 | */ | |
208 | #ifndef CONFIG_CAN_DRIVER | |
6d0f6bcf | 209 | #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC) |
5b1d7137 | 210 | #else /* we must activate GPL5 in the SIUMCR for CAN */ |
6d0f6bcf | 211 | #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC) |
5b1d7137 WD |
212 | #endif /* CONFIG_CAN_DRIVER */ |
213 | ||
214 | /*----------------------------------------------------------------------- | |
215 | * TBSCR - Time Base Status and Control 11-26 | |
216 | *----------------------------------------------------------------------- | |
217 | * Clear Reference Interrupt Status, Timebase freezing enabled | |
218 | */ | |
6d0f6bcf | 219 | #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
5b1d7137 WD |
220 | |
221 | /*----------------------------------------------------------------------- | |
222 | * RTCSC - Real-Time Clock Status and Control Register 11-27 | |
223 | *----------------------------------------------------------------------- | |
224 | */ | |
6d0f6bcf | 225 | #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) |
5b1d7137 WD |
226 | |
227 | /*----------------------------------------------------------------------- | |
228 | * PISCR - Periodic Interrupt Status and Control 11-31 | |
229 | *----------------------------------------------------------------------- | |
230 | * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled | |
231 | */ | |
6d0f6bcf | 232 | #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) |
5b1d7137 WD |
233 | |
234 | /*----------------------------------------------------------------------- | |
235 | * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 | |
236 | *----------------------------------------------------------------------- | |
237 | * Reset PLL lock status sticky bit, timer expired status bit and timer | |
238 | * interrupt status bit | |
239 | * | |
04a85b3b WD |
240 | * |
241 | *----------------------------------------------------------------------- | |
5b1d7137 WD |
242 | * SCCR - System Clock and reset Control Register 15-27 |
243 | *----------------------------------------------------------------------- | |
244 | * Set clock output, timebase and RTC source and divider, | |
245 | * power management and some other internal clocks | |
246 | */ | |
04a85b3b | 247 | |
5b1d7137 | 248 | #define SCCR_MASK SCCR_EBDF11 |
04a85b3b WD |
249 | |
250 | #if CONFIG_8xx_GCLK_FREQ == 50000000 | |
251 | ||
6d0f6bcf JCPV |
252 | #define CONFIG_SYS_PLPRCR ( ((5 - 1) << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) |
253 | #define CONFIG_SYS_SCCR (SCCR_TBS | \ | |
5b1d7137 WD |
254 | SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ |
255 | SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ | |
256 | SCCR_DFALCD00) | |
257 | ||
04a85b3b WD |
258 | #elif CONFIG_8xx_GCLK_FREQ == 80000000 |
259 | ||
6d0f6bcf JCPV |
260 | #define CONFIG_SYS_PLPRCR ( ((8 - 1) << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) |
261 | #define CONFIG_SYS_SCCR (SCCR_TBS | \ | |
04a85b3b WD |
262 | SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ |
263 | SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ | |
264 | SCCR_DFALCD00 | SCCR_EBDF01) | |
265 | ||
266 | #endif | |
267 | ||
5b1d7137 WD |
268 | /*----------------------------------------------------------------------- |
269 | * | |
270 | *----------------------------------------------------------------------- | |
271 | * | |
272 | */ | |
6d0f6bcf JCPV |
273 | /*#define CONFIG_SYS_DER 0x2002000F*/ |
274 | #define CONFIG_SYS_DER 0 | |
5b1d7137 WD |
275 | |
276 | /* | |
277 | * Init Memory Controller: | |
278 | * | |
279 | * BR0/1 and OR0/1 (FLASH) | |
280 | */ | |
281 | ||
282 | #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ | |
283 | ||
284 | /* used to re-map FLASH both when starting from SRAM or FLASH: | |
285 | * restrict access enough to keep SRAM working (if any) | |
286 | * but not too much to meddle with FLASH accesses | |
287 | */ | |
6d0f6bcf JCPV |
288 | #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ |
289 | #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ | |
5b1d7137 WD |
290 | |
291 | /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ | |
6d0f6bcf | 292 | #define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX) |
5b1d7137 | 293 | |
6d0f6bcf JCPV |
294 | #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
295 | #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) | |
296 | #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V ) | |
5b1d7137 | 297 | |
5b1d7137 WD |
298 | /* |
299 | * BR3 and OR3 (SDRAM) | |
300 | * | |
301 | */ | |
302 | #define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */ | |
303 | #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ | |
304 | ||
305 | /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ | |
6d0f6bcf | 306 | #define CONFIG_SYS_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS) |
5b1d7137 | 307 | |
6d0f6bcf JCPV |
308 | #define CONFIG_SYS_OR3_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_SDRAM) |
309 | #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_PS_32 | BR_V) | |
5b1d7137 | 310 | |
5b1d7137 WD |
311 | /* |
312 | * Memory Periodic Timer Prescaler | |
313 | */ | |
314 | ||
315 | /* periodic timer for refresh */ | |
6d0f6bcf | 316 | #define CONFIG_SYS_MAMR_PTA 208 |
5b1d7137 WD |
317 | |
318 | /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ | |
6d0f6bcf | 319 | #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ |
5b1d7137 WD |
320 | |
321 | /* | |
322 | * MAMR settings for SDRAM | |
323 | */ | |
324 | ||
325 | /* 9 column SDRAM */ | |
6d0f6bcf | 326 | #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
5b1d7137 WD |
327 | MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ |
328 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
329 | ||
5b1d7137 WD |
330 | /* Ethernet at SCC2 */ |
331 | #define CONFIG_SCC2_ENET | |
332 | ||
993cad93 WD |
333 | /****************************************************************/ |
334 | ||
335 | #define DSP_SIZE 0x00010000 /* 64K */ | |
336 | #define FPGA_SIZE 0x00010000 /* 64K */ | |
337 | ||
338 | #define DSP0_BASE 0xF1000000 | |
339 | #define DSP1_BASE (DSP0_BASE + DSP_SIZE) | |
340 | #define FPGA_BASE (DSP1_BASE + DSP_SIZE) | |
341 | ||
342 | #if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 | |
343 | ||
344 | #define ER_SIZE 0x00010000 /* 64K */ | |
345 | #define ER_BASE (FPGA_BASE + FPGA_SIZE) | |
346 | ||
347 | #define NAND_SIZE 0x00010000 /* 64K */ | |
348 | #define NAND_BASE (ER_BASE + ER_SIZE) | |
349 | ||
350 | #endif | |
351 | ||
352 | /****************************************************************/ | |
353 | ||
354 | #if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 | |
355 | ||
356 | #define STATUS_LED_BIT 0x00000001 /* bit 31 */ | |
6d0f6bcf | 357 | #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) |
993cad93 WD |
358 | #define STATUS_LED_STATE STATUS_LED_BLINKING |
359 | ||
360 | #define STATUS_LED_BIT1 0x00000002 /* bit 30 */ | |
6d0f6bcf | 361 | #define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2) |
993cad93 WD |
362 | #define STATUS_LED_STATE1 STATUS_LED_OFF |
363 | ||
364 | #define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */ | |
365 | #define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ | |
366 | ||
367 | #endif | |
368 | ||
993cad93 WD |
369 | |
370 | /*****************************************************************************/ | |
371 | ||
372 | #ifndef __ASSEMBLY__ | |
373 | ||
374 | #if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 | |
375 | ||
376 | /* LEDs */ | |
377 | ||
378 | /* last value written to the external register; we cannot read back */ | |
379 | extern unsigned int last_er_val; | |
380 | ||
381 | /* led_id_t is unsigned long mask */ | |
382 | typedef unsigned int led_id_t; | |
383 | ||
384 | static inline void __led_init(led_id_t mask, int state) | |
385 | { | |
386 | unsigned int new_er_val; | |
387 | ||
388 | if (state) | |
389 | new_er_val = last_er_val & ~mask; | |
390 | else | |
391 | new_er_val = last_er_val | mask; | |
392 | ||
393 | *(volatile unsigned int *)ER_BASE = new_er_val; | |
394 | last_er_val = new_er_val; | |
395 | } | |
396 | ||
397 | static inline void __led_toggle(led_id_t mask) | |
398 | { | |
399 | unsigned int new_er_val; | |
400 | ||
401 | new_er_val = last_er_val ^ mask; | |
402 | *(volatile unsigned int *)ER_BASE = new_er_val; | |
403 | last_er_val = new_er_val; | |
404 | } | |
405 | ||
406 | static inline void __led_set(led_id_t mask, int state) | |
407 | { | |
408 | unsigned int new_er_val; | |
409 | ||
410 | if (state) | |
411 | new_er_val = last_er_val & ~mask; | |
412 | else | |
413 | new_er_val = last_er_val | mask; | |
414 | ||
415 | *(volatile unsigned int *)ER_BASE = new_er_val; | |
416 | last_er_val = new_er_val; | |
417 | } | |
418 | ||
419 | /* MAX3100 console */ | |
6d0f6bcf | 420 | #define MAX3100_SPI_RXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat) |
993cad93 WD |
421 | #define MAX3100_SPI_RXD_BIT 0x00000008 |
422 | ||
6d0f6bcf | 423 | #define MAX3100_SPI_TXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat) |
993cad93 WD |
424 | #define MAX3100_SPI_TXD_BIT 0x00000004 |
425 | ||
6d0f6bcf | 426 | #define MAX3100_SPI_CLK_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat) |
993cad93 WD |
427 | #define MAX3100_SPI_CLK_BIT 0x00000002 |
428 | ||
6d0f6bcf | 429 | #define MAX3100_CS_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) |
993cad93 WD |
430 | #define MAX3100_CS_BIT 0x0010 |
431 | ||
432 | #endif | |
433 | ||
434 | #endif | |
435 | ||
04a85b3b | 436 | /*************************************************************************************************/ |
993cad93 | 437 | |
5b1d7137 | 438 | #endif /* __CONFIG_H */ |