[people/ms/u-boot.git] / include / configs / NETVIA.h

/*
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
 * U-Boot port on NetVia board
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC850		1	/* This is a MPC850 CPU		*/
#define CONFIG_NETVIA		1	/* ...on a NetVia board		*/

#define	CONFIG_SYS_TEXT_BASE	0x40000000

#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1
#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
#undef	CONFIG_8xx_CONS_SMC2
#undef	CONFIG_8xx_CONS_NONE
#else
#define CONFIG_8xx_CONS_NONE
#define CONFIG_MAX3100_SERIAL
#endif

#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/

#define CONFIG_XIN		10000000
#define CONFIG_8xx_GCLK_FREQ	80000000

#if 0
#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
#else
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
#endif

#undef	CONFIG_CLOCKS_IN_MHZ	/* clocks NOT passsed to Linux in MHz */

#define CONFIG_PREBOOT	"echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"

#undef	CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND							\
	"tftpboot; "								\
	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
	"bootm"

#define CONFIG_LOADS_ECHO	0	/* echo off for serial download	*/
#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/

#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
#define CONFIG_BOARD_SPECIFIC_LED	/* version has board specific leds */
#endif

#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_NISDOMAIN


#undef CONFIG_MAC_PARTITION
#undef CONFIG_DOS_PARTITION

#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PING

#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
/* #define CONFIG_CMD_NAND */ /* disabled */
#endif


#define CONFIG_BOARD_EARLY_INIT_F 1
#define CONFIG_MISC_INIT_R

/*
 * Miscellaneous configurable options
 */
#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB)
#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x0300000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x0700000	/* 3 ... 7 MB in DRAM	*/

#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/

#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/

#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CONFIG_SYS_IMMR		0xFF000000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
#define	CONFIG_SYS_INIT_RAM_SIZE	0x3000	/* Size of used area in DPRAM	*/
#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE)
#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define	CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH_BASE		0x40000000
#if defined(DEBUG)
#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#else
#define	CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
#endif
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	8	/* max number of sectors on one chip	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define	CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_SECT_SIZE	0x10000

#define	CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x60000)
#define CONFIG_ENV_OFFSET		0
#define	CONFIG_ENV_SIZE		0x4000

#define CONFIG_ENV_ADDR_REDUND	(CONFIG_SYS_FLASH_BASE + 0x70000)
#define CONFIG_ENV_OFFSET_REDUND	0
#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
#endif

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#if defined(CONFIG_WATCHDOG)
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
#else
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				11-6
 *-----------------------------------------------------------------------
 * PCMCIA config., multi-function pin tri-state
 */
#ifndef	CONFIG_CAN_DRIVER
#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
#else	/* we must activate GPL5 in the SIUMCR for CAN */
#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
#endif	/* CONFIG_CAN_DRIVER */

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control				11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)

/*-----------------------------------------------------------------------
 * RTCSC - Real-Time Clock Status and Control Register		11-27
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)

/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
 *-----------------------------------------------------------------------
 * Reset PLL lock status sticky bit, timer expired status bit and timer
 * interrupt status bit
 *
 *
 *-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */

#define SCCR_MASK	SCCR_EBDF11

#if CONFIG_8xx_GCLK_FREQ == 50000000

#define CONFIG_SYS_PLPRCR	( ((5 - 1) << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
#define CONFIG_SYS_SCCR	(SCCR_TBS     | \
			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
			 SCCR_DFALCD00)

#elif CONFIG_8xx_GCLK_FREQ == 80000000

#define CONFIG_SYS_PLPRCR	( ((8 - 1) << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
#define CONFIG_SYS_SCCR	(SCCR_TBS     | \
			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
			 SCCR_DFALCD00 | SCCR_EBDF01)

#endif

/*-----------------------------------------------------------------------
 *
 *-----------------------------------------------------------------------
 *
 */
/*#define	CONFIG_SYS_DER	0x2002000F*/
#define CONFIG_SYS_DER	0

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */

#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/

/* used to re-map FLASH both when starting from SRAM or FLASH:
 * restrict access enough to keep SRAM working (if any)
 * but not too much to meddle with FLASH accesses
 */
#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */

/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1	*/
#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_BI | OR_SCY_5_CLK | OR_TRLX)

#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )

/*
 * BR3 and OR3 (SDRAM)
 *
 */
#define SDRAM_BASE3_PRELIM	0x00000000	/* SDRAM bank #0	*/
#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/

/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
#define CONFIG_SYS_OR_TIMING_SDRAM	(OR_CSNT_SAM | OR_G5LS)

#define CONFIG_SYS_OR3_PRELIM	((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_SDRAM)
#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_PS_32 | BR_V)

/*
 * Memory Periodic Timer Prescaler
 */

/* periodic timer for refresh */
#define CONFIG_SYS_MAMR_PTA	208

/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/

/*
 * MAMR settings for SDRAM
 */

/* 9 column SDRAM */
#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)

/* Ethernet at SCC2 */
#define CONFIG_SCC2_ENET

/****************************************************************/

#define DSP_SIZE	0x00010000	/* 64K */
#define FPGA_SIZE	0x00010000	/* 64K */

#define DSP0_BASE	0xF1000000
#define DSP1_BASE	(DSP0_BASE + DSP_SIZE)
#define FPGA_BASE	(DSP1_BASE + DSP_SIZE)

#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2

#define ER_SIZE		0x00010000	/* 64K */
#define ER_BASE		(FPGA_BASE + FPGA_SIZE)

#define NAND_SIZE	0x00010000	/* 64K */
#define NAND_BASE	(ER_BASE + ER_SIZE)

#endif

/****************************************************************/

#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2

#define STATUS_LED_BIT		0x00000001		/* bit 31 */
#define STATUS_LED_PERIOD	(CONFIG_SYS_HZ / 2)
#define STATUS_LED_STATE	STATUS_LED_BLINKING

#define STATUS_LED_BIT1		0x00000002		/* bit 30 */
#define STATUS_LED_PERIOD1	(CONFIG_SYS_HZ / 2)
#define STATUS_LED_STATE1	STATUS_LED_OFF

#define STATUS_LED_ACTIVE	0		/* LED on for bit == 0	*/
#define STATUS_LED_BOOT		0		/* LED 0 used for boot status */

#endif


/*****************************************************************************/

#ifndef __ASSEMBLY__

#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2

/* LEDs */

/* last value written to the external register; we cannot read back */
extern unsigned int last_er_val;

/* led_id_t is unsigned long mask */
typedef unsigned int led_id_t;

static inline void __led_init(led_id_t mask, int state)
{
	unsigned int new_er_val;

	if (state)
		new_er_val = last_er_val & ~mask;
	else
		new_er_val = last_er_val |  mask;

	*(volatile unsigned int *)ER_BASE = new_er_val;
	last_er_val = new_er_val;
}

static inline void __led_toggle(led_id_t mask)
{
	unsigned int new_er_val;

	new_er_val = last_er_val ^ mask;
	*(volatile unsigned int *)ER_BASE = new_er_val;
	last_er_val = new_er_val;
}

static inline void __led_set(led_id_t mask, int state)
{
	unsigned int new_er_val;

	if (state)
		new_er_val = last_er_val & ~mask;
	else
		new_er_val = last_er_val |  mask;

	*(volatile unsigned int *)ER_BASE = new_er_val;
	last_er_val = new_er_val;
}

/* MAX3100 console */
#define MAX3100_SPI_RXD_PORT	(((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
#define MAX3100_SPI_RXD_BIT	0x00000008

#define MAX3100_SPI_TXD_PORT	(((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
#define MAX3100_SPI_TXD_BIT	0x00000004

#define MAX3100_SPI_CLK_PORT	(((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
#define MAX3100_SPI_CLK_BIT	0x00000002

#define MAX3100_CS_PORT		(((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat)
#define MAX3100_CS_BIT		0x0010

#endif

#endif

/*************************************************************************************************/

#endif	/* __CONFIG_H */
Commit	Line	Data
5b1d7137 WD	1	/*
	2	* (C) Copyright 2000
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* Pantelis Antoniou, Intracom S.A., panto@intracom.gr
	26	* U-Boot port on NetVia board
	27	*/
	28
	29	#ifndef __CONFIG_H
	30	#define __CONFIG_H
	31
	32	/*
	33	* High Level Configuration Options
	34	* (easy to change)
	35	*/
	36
	37	#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
	38	#define CONFIG_NETVIA 1 /* ...on a NetVia board */
5b1d7137	39
2ae18241 WD	40	#define CONFIG_SYS_TEXT_BASE 0x40000000
2ae18241 WD	41
993cad93	42	#if !defined(CONFIG_NETVIA_VERSION) \|\| CONFIG_NETVIA_VERSION == 1
5b1d7137 WD	43	#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
	44	#undef CONFIG_8xx_CONS_SMC2
	45	#undef CONFIG_8xx_CONS_NONE
993cad93 WD	46	#else
	47	#define CONFIG_8xx_CONS_NONE
	48	#define CONFIG_MAX3100_SERIAL
	49	#endif
	50
5b1d7137 WD	51	#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
5b1d7137 WD	52
04a85b3b WD	53	#define CONFIG_XIN 10000000
04a85b3b WD	54	#define CONFIG_8xx_GCLK_FREQ 80000000
5b1d7137 WD	55
	56	#if 0
	57	#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
	58	#else
	59	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	60	#endif
	61
	62	#undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */
	63
32bf3d14	64	#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
5b1d7137 WD	65
	66	#undef CONFIG_BOOTARGS
	67	#define CONFIG_BOOTCOMMAND \
53677ef1 WD	68	"tftpboot; " \
	69	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
	70	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
5b1d7137 WD	71	"bootm"
	72
	73	#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
6d0f6bcf	74	#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
5b1d7137 WD	75
	76	#undef CONFIG_WATCHDOG /* watchdog disabled */
	77
	78	#define CONFIG_STATUS_LED 1 /* Status LED enabled */
	79
993cad93 WD	80	#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
	81	#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */
	82	#endif
	83
5b1d7137 WD	84	#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
5b1d7137 WD	85
7be044e4 JL	86	/*
	87	* BOOTP options
	88	*/
	89	#define CONFIG_BOOTP_SUBNETMASK
	90	#define CONFIG_BOOTP_GATEWAY
	91	#define CONFIG_BOOTP_HOSTNAME
	92	#define CONFIG_BOOTP_BOOTPATH
	93	#define CONFIG_BOOTP_BOOTFILESIZE
	94	#define CONFIG_BOOTP_NISDOMAIN
	95
5b1d7137 WD	96
	97	#undef CONFIG_MAC_PARTITION
	98	#undef CONFIG_DOS_PARTITION
	99
	100	#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
	101
e18a1061 JL	102
	103	/*
	104	* Command line configuration.
	105	*/
	106	#include <config_cmd_default.h>
	107
	108	#define CONFIG_CMD_DHCP
	109	#define CONFIG_CMD_PING
993cad93 WD	110
993cad93 WD	111	#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
7640f419	112	/* #define CONFIG_CMD_NAND / / disabled */
993cad93	113	#endif
5b1d7137	114
e18a1061	115
c837dcb1	116	#define CONFIG_BOARD_EARLY_INIT_F 1
5b1d7137 WD	117	#define CONFIG_MISC_INIT_R
5b1d7137 WD	118
5b1d7137 WD	119	/*
	120	* Miscellaneous configurable options
	121	*/
6d0f6bcf JCPV	122	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	123	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
e18a1061	124	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	125	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
5b1d7137	126	#else
6d0f6bcf	127	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
5b1d7137	128	#endif
6d0f6bcf JCPV	129	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	130	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	131	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
5b1d7137	132
6d0f6bcf JCPV	133	#define CONFIG_SYS_MEMTEST_START 0x0300000 /* memtest works on */
6d0f6bcf JCPV	134	#define CONFIG_SYS_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */
5b1d7137	135
6d0f6bcf	136	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
5b1d7137	137
6d0f6bcf	138	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
5b1d7137	139
6d0f6bcf	140	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
5b1d7137 WD	141
	142	/*
	143	* Low Level Configuration Settings
	144	* (address mappings, register initial values, etc.)
	145	* You should know what you are doing if you make changes here.
	146	*/
	147	/*-----------------------------------------------------------------------
	148	* Internal Memory Mapped Register
	149	*/
6d0f6bcf	150	#define CONFIG_SYS_IMMR 0xFF000000
5b1d7137 WD	151
	152	/*-----------------------------------------------------------------------
	153	* Definitions for initial stack pointer and data area (in DPRAM)
	154	*/
6d0f6bcf	155	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
553f0982	156	#define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */
6d0f6bcf	157	#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
553f0982	158	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE)
6d0f6bcf	159	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
5b1d7137 WD	160
	161	/*-----------------------------------------------------------------------
	162	* Start addresses for the final memory configuration
	163	* (Set up by the startup code)
6d0f6bcf	164	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
5b1d7137	165	*/
6d0f6bcf JCPV	166	#define CONFIG_SYS_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	167	#define CONFIG_SYS_FLASH_BASE 0x40000000
5b1d7137	168	#if defined(DEBUG)
6d0f6bcf	169	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
5b1d7137	170	#else
6d0f6bcf	171	#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
5b1d7137	172	#endif
6d0f6bcf JCPV	173	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
6d0f6bcf JCPV	174	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
5b1d7137 WD	175
	176	/*
	177	* For booting Linux, the board info and command line data
	178	* have to be in the first 8 MB of memory, since this is
	179	* the maximum mapped by the Linux kernel during initialization.
	180	*/
6d0f6bcf	181	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
5b1d7137 WD	182
	183	/*-----------------------------------------------------------------------
	184	* FLASH organization
	185	*/
6d0f6bcf JCPV	186	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
6d0f6bcf JCPV	187	#define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
5b1d7137	188
6d0f6bcf JCPV	189	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	190	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
5b1d7137	191
5a1aceb0	192	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586	193	#define CONFIG_ENV_SECT_SIZE 0x10000
5b1d7137	194
6d0f6bcf	195	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x60000)
0e8d1586 JCPV	196	#define CONFIG_ENV_OFFSET 0
0e8d1586 JCPV	197	#define CONFIG_ENV_SIZE 0x4000
993cad93	198
6d0f6bcf	199	#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + 0x70000)
0e8d1586 JCPV	200	#define CONFIG_ENV_OFFSET_REDUND 0
0e8d1586 JCPV	201	#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
993cad93	202
5b1d7137 WD	203	/*-----------------------------------------------------------------------
	204	* Cache Configuration
	205	*/
6d0f6bcf	206	#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
e18a1061	207	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	208	#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
5b1d7137 WD	209	#endif
	210
	211	/*-----------------------------------------------------------------------
	212	* SYPCR - System Protection Control 11-9
	213	* SYPCR can only be written once after reset!
	214	*-----------------------------------------------------------------------
	215	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
	216	*/
	217	#if defined(CONFIG_WATCHDOG)
6d0f6bcf	218	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
5b1d7137 WD	219	SYPCR_SWE \| SYPCR_SWRI\| SYPCR_SWP)
5b1d7137 WD	220	#else
6d0f6bcf	221	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| SYPCR_SWP)
5b1d7137 WD	222	#endif
	223
	224	/*-----------------------------------------------------------------------
	225	* SIUMCR - SIU Module Configuration 11-6
	226	*-----------------------------------------------------------------------
	227	* PCMCIA config., multi-function pin tri-state
	228	*/
	229	#ifndef CONFIG_CAN_DRIVER
6d0f6bcf	230	#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 \| SIUMCR_DBPC00 \| SIUMCR_MLRC01 \| SIUMCR_FRC)
5b1d7137	231	#else /* we must activate GPL5 in the SIUMCR for CAN */
6d0f6bcf	232	#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 \| SIUMCR_DBPC00 \| SIUMCR_MLRC01 \| SIUMCR_FRC)
5b1d7137 WD	233	#endif /* CONFIG_CAN_DRIVER */
	234
	235	/*-----------------------------------------------------------------------
	236	* TBSCR - Time Base Status and Control 11-26
	237	*-----------------------------------------------------------------------
	238	* Clear Reference Interrupt Status, Timebase freezing enabled
	239	*/
6d0f6bcf	240	#define CONFIG_SYS_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBF)
5b1d7137 WD	241
	242	/*-----------------------------------------------------------------------
	243	* RTCSC - Real-Time Clock Status and Control Register 11-27
	244	*-----------------------------------------------------------------------
	245	*/
6d0f6bcf	246	#define CONFIG_SYS_RTCSC (RTCSC_SEC \| RTCSC_ALR \| RTCSC_RTF\| RTCSC_RTE)
5b1d7137 WD	247
	248	/*-----------------------------------------------------------------------
	249	* PISCR - Periodic Interrupt Status and Control 11-31
	250	*-----------------------------------------------------------------------
	251	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
	252	*/
6d0f6bcf	253	#define CONFIG_SYS_PISCR (PISCR_PS \| PISCR_PITF)
5b1d7137 WD	254
	255	/*-----------------------------------------------------------------------
	256	* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
	257	*-----------------------------------------------------------------------
	258	* Reset PLL lock status sticky bit, timer expired status bit and timer
	259	* interrupt status bit
	260	*
04a85b3b WD	261	*
04a85b3b WD	262	*-----------------------------------------------------------------------
5b1d7137 WD	263	* SCCR - System Clock and reset Control Register 15-27
	264	*-----------------------------------------------------------------------
	265	* Set clock output, timebase and RTC source and divider,
	266	* power management and some other internal clocks
	267	*/
04a85b3b	268
5b1d7137	269	#define SCCR_MASK SCCR_EBDF11
04a85b3b WD	270
	271	#if CONFIG_8xx_GCLK_FREQ == 50000000
	272
6d0f6bcf JCPV	273	#define CONFIG_SYS_PLPRCR ( ((5 - 1) << PLPRCR_MF_SHIFT) \| PLPRCR_SPLSS \| PLPRCR_TEXPS \| PLPRCR_TMIST)
6d0f6bcf JCPV	274	#define CONFIG_SYS_SCCR (SCCR_TBS \| \
5b1d7137 WD	275	SCCR_COM00 \| SCCR_DFSYNC00 \| SCCR_DFBRG00 \| \
	276	SCCR_DFNL000 \| SCCR_DFNH000 \| SCCR_DFLCD000 \| \
	277	SCCR_DFALCD00)
	278
04a85b3b WD	279	#elif CONFIG_8xx_GCLK_FREQ == 80000000
04a85b3b WD	280
6d0f6bcf JCPV	281	#define CONFIG_SYS_PLPRCR ( ((8 - 1) << PLPRCR_MF_SHIFT) \| PLPRCR_SPLSS \| PLPRCR_TEXPS \| PLPRCR_TMIST)
6d0f6bcf JCPV	282	#define CONFIG_SYS_SCCR (SCCR_TBS \| \
04a85b3b WD	283	SCCR_COM00 \| SCCR_DFSYNC00 \| SCCR_DFBRG00 \| \
	284	SCCR_DFNL000 \| SCCR_DFNH000 \| SCCR_DFLCD000 \| \
	285	SCCR_DFALCD00 \| SCCR_EBDF01)
	286
	287	#endif
	288
5b1d7137 WD	289	/*-----------------------------------------------------------------------
	290	*
	291	*-----------------------------------------------------------------------
	292	*
	293	*/
6d0f6bcf JCPV	294	/#define CONFIG_SYS_DER 0x2002000F/
6d0f6bcf JCPV	295	#define CONFIG_SYS_DER 0
5b1d7137 WD	296
	297	/*
	298	* Init Memory Controller:
	299	*
	300	* BR0/1 and OR0/1 (FLASH)
	301	*/
	302
	303	#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
	304
	305	/* used to re-map FLASH both when starting from SRAM or FLASH:
	306	* restrict access enough to keep SRAM working (if any)
	307	* but not too much to meddle with FLASH accesses
	308	*/
6d0f6bcf JCPV	309	#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
6d0f6bcf JCPV	310	#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
5b1d7137 WD	311
5b1d7137 WD	312	/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
6d0f6bcf	313	#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM \| OR_BI \| OR_SCY_5_CLK \| OR_TRLX)
5b1d7137	314
6d0f6bcf JCPV	315	#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM \| CONFIG_SYS_OR_TIMING_FLASH)
	316	#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \| CONFIG_SYS_OR_TIMING_FLASH)
	317	#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) \| BR_PS_8 \| BR_V )
5b1d7137	318
5b1d7137 WD	319	/*
	320	* BR3 and OR3 (SDRAM)
	321	*
	322	*/
	323	#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */
	324	#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
	325
	326	/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
6d0f6bcf	327	#define CONFIG_SYS_OR_TIMING_SDRAM (OR_CSNT_SAM \| OR_G5LS)
5b1d7137	328
6d0f6bcf JCPV	329	#define CONFIG_SYS_OR3_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) \| CONFIG_SYS_OR_TIMING_SDRAM)
6d0f6bcf JCPV	330	#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) \| BR_MS_UPMA \| BR_PS_32 \| BR_V)
5b1d7137	331
5b1d7137 WD	332	/*
	333	* Memory Periodic Timer Prescaler
	334	*/
	335
	336	/* periodic timer for refresh */
6d0f6bcf	337	#define CONFIG_SYS_MAMR_PTA 208
5b1d7137 WD	338
5b1d7137 WD	339	/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
6d0f6bcf	340	#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
5b1d7137 WD	341
	342	/*
	343	* MAMR settings for SDRAM
	344	*/
	345
	346	/* 9 column SDRAM */
6d0f6bcf	347	#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
5b1d7137 WD	348	MAMR_AMA_TYPE_1 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A10 \| \
	349	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
	350
5b1d7137 WD	351	/* Ethernet at SCC2 */
	352	#define CONFIG_SCC2_ENET
	353
993cad93 WD	354	/****************************************************************/
	355
	356	#define DSP_SIZE 0x00010000 /* 64K */
	357	#define FPGA_SIZE 0x00010000 /* 64K */
	358
	359	#define DSP0_BASE 0xF1000000
	360	#define DSP1_BASE (DSP0_BASE + DSP_SIZE)
	361	#define FPGA_BASE (DSP1_BASE + DSP_SIZE)
	362
	363	#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
	364
	365	#define ER_SIZE 0x00010000 /* 64K */
	366	#define ER_BASE (FPGA_BASE + FPGA_SIZE)
	367
	368	#define NAND_SIZE 0x00010000 /* 64K */
	369	#define NAND_BASE (ER_BASE + ER_SIZE)
	370
	371	#endif
	372
	373	/****************************************************************/
	374
	375	#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
	376
	377	#define STATUS_LED_BIT 0x00000001 /* bit 31 */
6d0f6bcf	378	#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
993cad93 WD	379	#define STATUS_LED_STATE STATUS_LED_BLINKING
	380
	381	#define STATUS_LED_BIT1 0x00000002 /* bit 30 */
6d0f6bcf	382	#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
993cad93 WD	383	#define STATUS_LED_STATE1 STATUS_LED_OFF
	384
	385	#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
	386	#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
	387
	388	#endif
	389
993cad93 WD	390
	391	/*****************************************************************************/
	392
	393	#ifndef __ASSEMBLY__
	394
	395	#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
	396
	397	/* LEDs */
	398
	399	/* last value written to the external register; we cannot read back */
	400	extern unsigned int last_er_val;
	401
	402	/* led_id_t is unsigned long mask */
	403	typedef unsigned int led_id_t;
	404
	405	static inline void __led_init(led_id_t mask, int state)
	406	{
	407	unsigned int new_er_val;
	408
	409	if (state)
	410	new_er_val = last_er_val & ~mask;
	411	else
	412	new_er_val = last_er_val \| mask;
	413
	414	(volatile unsigned int )ER_BASE = new_er_val;
	415	last_er_val = new_er_val;
	416	}
	417
	418	static inline void __led_toggle(led_id_t mask)
	419	{
	420	unsigned int new_er_val;
	421
	422	new_er_val = last_er_val ^ mask;
	423	(volatile unsigned int )ER_BASE = new_er_val;
	424	last_er_val = new_er_val;
	425	}
	426
	427	static inline void __led_set(led_id_t mask, int state)
	428	{
	429	unsigned int new_er_val;
	430
	431	if (state)
	432	new_er_val = last_er_val & ~mask;
	433	else
	434	new_er_val = last_er_val \| mask;
	435
	436	(volatile unsigned int )ER_BASE = new_er_val;
	437	last_er_val = new_er_val;
	438	}
	439
	440	/* MAX3100 console */
6d0f6bcf	441	#define MAX3100_SPI_RXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
993cad93 WD	442	#define MAX3100_SPI_RXD_BIT 0x00000008
993cad93 WD	443
6d0f6bcf	444	#define MAX3100_SPI_TXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
993cad93 WD	445	#define MAX3100_SPI_TXD_BIT 0x00000004
993cad93 WD	446
6d0f6bcf	447	#define MAX3100_SPI_CLK_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
993cad93 WD	448	#define MAX3100_SPI_CLK_BIT 0x00000002
993cad93 WD	449
6d0f6bcf	450	#define MAX3100_CS_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat)
993cad93 WD	451	#define MAX3100_CS_BIT 0x0010
	452
	453	#endif
	454
	455	#endif
	456
04a85b3b	457	/*************************************************************************************************/
993cad93	458
5b1d7137	459	#endif /* __CONFIG_H */