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f12e568c | 1 | /* |
414eec35 | 2 | * (C) Copyright 2000-2005 |
f12e568c WD |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * board/config.h - configuration options, board specific | |
26 | */ | |
27 | ||
28 | #ifndef __CONFIG_H | |
29 | #define __CONFIG_H | |
30 | ||
31 | /* | |
32 | * High Level Configuration Options | |
33 | * (easy to change) | |
34 | */ | |
35 | ||
36 | #define CONFIG_MPC855 1 /* This is a MPC855 CPU */ | |
37 | #define CONFIG_TQM855M 1 /* ...on a TQM8xxM module */ | |
e7df029f | 38 | #define CONFIG_NSCU 1 |
f12e568c WD |
39 | |
40 | #define CONFIG_8xx_CONS_SCC1 1 /* Console is on SMC1 */ | |
41 | ||
42 | #define CONFIG_66MHz 1 /* running at 66 MHz, 1:1 clock */ | |
43 | ||
44 | #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ | |
45 | ||
46 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
47 | ||
f12e568c WD |
48 | #define CONFIG_BOARD_TYPES 1 /* support board types */ |
49 | ||
50 | #define CONFIG_PREBOOT "echo;" \ | |
51 | "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ | |
52 | "echo" | |
53 | ||
54 | #undef CONFIG_BOOTARGS | |
55 | ||
56 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
57 | "netdev=eth0\0" \ | |
58 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
fe126d8b | 59 | "nfsroot=${serverip}:${rootpath}\0" \ |
f12e568c | 60 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
fe126d8b WD |
61 | "addip=setenv bootargs ${bootargs} " \ |
62 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
63 | ":${hostname}:${netdev}:off panic=1\0" \ | |
f12e568c | 64 | "flash_nfs=run nfsargs addip;" \ |
fe126d8b | 65 | "bootm ${kernel_addr}\0" \ |
f12e568c | 66 | "flash_self=run ramargs addip;" \ |
fe126d8b WD |
67 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
68 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ | |
f12e568c WD |
69 | "rootpath=/opt/eldk/ppc_8xx\0" \ |
70 | "bootfile=/tftpboot/NSCU/uImage\0" \ | |
71 | "kernel_addr=40080000\0" \ | |
72 | "ramdisk_addr=40180000\0" \ | |
73 | "" | |
74 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
75 | ||
cfca5e60 WD |
76 | #define CONFIG_MISC_INIT_R 1 |
77 | ||
f12e568c WD |
78 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
79 | #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ | |
80 | ||
81 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
82 | ||
83 | #define CONFIG_STATUS_LED 1 /* Status LED enabled */ | |
84 | ||
85 | #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ | |
86 | ||
87 | #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) | |
88 | ||
89 | #define CONFIG_MAC_PARTITION | |
90 | #define CONFIG_DOS_PARTITION | |
91 | ||
92 | #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ | |
93 | ||
bdccc4fe WD |
94 | #define CONFIG_ISP1362_USB /* ISP1362 USB OTG controller */ |
95 | ||
f12e568c | 96 | |
e18a1061 JL |
97 | /* |
98 | * Command line configuration. | |
99 | */ | |
100 | #include <config_cmd_default.h> | |
101 | ||
102 | #define CONFIG_CMD_ASKENV | |
103 | #define CONFIG_CMD_DATE | |
104 | #define CONFIG_CMD_DHCP | |
105 | #define CONFIG_CMD_IDE | |
106 | #define CONFIG_CMD_NFS | |
107 | #define CONFIG_CMD_SNTP | |
108 | ||
f12e568c WD |
109 | |
110 | /* | |
111 | * Miscellaneous configurable options | |
112 | */ | |
113 | #define CFG_LONGHELP /* undef to save memory */ | |
114 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
115 | ||
116 | #if 0 | |
117 | #define CFG_HUSH_PARSER 1 /* use "hush" command parser */ | |
118 | #endif | |
119 | #ifdef CFG_HUSH_PARSER | |
120 | #define CFG_PROMPT_HUSH_PS2 "> " | |
121 | #endif | |
122 | ||
e18a1061 | 123 | #if defined(CONFIG_CMD_KGDB) |
f12e568c WD |
124 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
125 | #else | |
126 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
127 | #endif | |
128 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
129 | #define CFG_MAXARGS 16 /* max number of command args */ | |
130 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
131 | ||
132 | #define CFG_MEMTEST_START 0x0400000 /* memtest works on */ | |
133 | #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
134 | ||
135 | #define CFG_LOAD_ADDR 0x100000 /* default load address */ | |
136 | ||
137 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
138 | ||
139 | #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } | |
140 | ||
141 | /* | |
142 | * Low Level Configuration Settings | |
143 | * (address mappings, register initial values, etc.) | |
144 | * You should know what you are doing if you make changes here. | |
145 | */ | |
146 | /*----------------------------------------------------------------------- | |
147 | * Internal Memory Mapped Register | |
148 | */ | |
149 | #define CFG_IMMR 0xFFF00000 | |
150 | ||
151 | /*----------------------------------------------------------------------- | |
152 | * Definitions for initial stack pointer and data area (in DPRAM) | |
153 | */ | |
154 | #define CFG_INIT_RAM_ADDR CFG_IMMR | |
155 | #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ | |
156 | #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ | |
157 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
158 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
159 | ||
160 | /*----------------------------------------------------------------------- | |
161 | * Start addresses for the final memory configuration | |
162 | * (Set up by the startup code) | |
163 | * Please note that CFG_SDRAM_BASE _must_ start at 0 | |
164 | */ | |
165 | #define CFG_SDRAM_BASE 0x00000000 | |
166 | #define CFG_FLASH_BASE 0x40000000 | |
167 | #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
168 | #define CFG_MONITOR_BASE CFG_FLASH_BASE | |
169 | #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
170 | ||
171 | /* | |
172 | * For booting Linux, the board info and command line data | |
173 | * have to be in the first 8 MB of memory, since this is | |
174 | * the maximum mapped by the Linux kernel during initialization. | |
175 | */ | |
176 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
177 | ||
178 | /*----------------------------------------------------------------------- | |
179 | * FLASH organization | |
180 | */ | |
181 | #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
182 | #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ | |
183 | ||
184 | #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ | |
185 | #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
186 | ||
187 | #define CFG_ENV_IS_IN_FLASH 1 | |
188 | #define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ | |
189 | #define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ | |
190 | #define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ | |
191 | ||
192 | /* Address and size of Redundant Environment Sector */ | |
193 | #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE) | |
194 | #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) | |
195 | ||
196 | /*----------------------------------------------------------------------- | |
197 | * Hardware Information Block | |
198 | */ | |
199 | #define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ | |
200 | #define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ | |
201 | #define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ | |
202 | ||
203 | /*----------------------------------------------------------------------- | |
204 | * Cache Configuration | |
205 | */ | |
206 | #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ | |
e18a1061 | 207 | #if defined(CONFIG_CMD_KGDB) |
f12e568c WD |
208 | #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
209 | #endif | |
210 | ||
211 | /*----------------------------------------------------------------------- | |
212 | * SYPCR - System Protection Control 11-9 | |
213 | * SYPCR can only be written once after reset! | |
214 | *----------------------------------------------------------------------- | |
215 | * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze | |
216 | */ | |
217 | #if defined(CONFIG_WATCHDOG) | |
218 | #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ | |
219 | SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) | |
220 | #else | |
221 | #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) | |
222 | #endif | |
223 | ||
224 | /*----------------------------------------------------------------------- | |
225 | * SIUMCR - SIU Module Configuration 11-6 | |
226 | *----------------------------------------------------------------------- | |
227 | * PCMCIA config., multi-function pin tri-state | |
228 | */ | |
229 | #ifndef CONFIG_CAN_DRIVER | |
230 | #define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) | |
231 | #else /* we must activate GPL5 in the SIUMCR for CAN */ | |
232 | #define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) | |
233 | #endif /* CONFIG_CAN_DRIVER */ | |
234 | ||
235 | /*----------------------------------------------------------------------- | |
236 | * TBSCR - Time Base Status and Control 11-26 | |
237 | *----------------------------------------------------------------------- | |
238 | * Clear Reference Interrupt Status, Timebase freezing enabled | |
239 | */ | |
240 | #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) | |
241 | ||
242 | /*----------------------------------------------------------------------- | |
243 | * RTCSC - Real-Time Clock Status and Control Register 11-27 | |
244 | *----------------------------------------------------------------------- | |
245 | */ | |
246 | #define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) | |
247 | ||
248 | /*----------------------------------------------------------------------- | |
249 | * PISCR - Periodic Interrupt Status and Control 11-31 | |
250 | *----------------------------------------------------------------------- | |
251 | * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled | |
252 | */ | |
253 | #define CFG_PISCR (PISCR_PS | PISCR_PITF) | |
254 | ||
255 | /*----------------------------------------------------------------------- | |
256 | * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 | |
257 | *----------------------------------------------------------------------- | |
258 | * Reset PLL lock status sticky bit, timer expired status bit and timer | |
259 | * interrupt status bit | |
f12e568c | 260 | */ |
f12e568c | 261 | #define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) |
f12e568c WD |
262 | |
263 | /*----------------------------------------------------------------------- | |
264 | * SCCR - System Clock and reset Control Register 15-27 | |
265 | *----------------------------------------------------------------------- | |
266 | * Set clock output, timebase and RTC source and divider, | |
267 | * power management and some other internal clocks | |
268 | */ | |
269 | #define SCCR_MASK SCCR_EBDF11 | |
cfca5e60 | 270 | #define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ |
f12e568c WD |
271 | SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ |
272 | SCCR_DFALCD00) | |
f12e568c WD |
273 | |
274 | /*----------------------------------------------------------------------- | |
275 | * PCMCIA stuff | |
276 | *----------------------------------------------------------------------- | |
277 | * | |
278 | */ | |
e7df029f | 279 | /* NSCU use both slots, SLOT_A as "primary". */ |
280 | #define CONFIG_PCMCIA_SLOT_A 1 | |
281 | ||
f12e568c WD |
282 | #define CFG_PCMCIA_MEM_ADDR (0xE0000000) |
283 | #define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) | |
284 | #define CFG_PCMCIA_DMA_ADDR (0xE4000000) | |
285 | #define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) | |
286 | #define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) | |
287 | #define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) | |
288 | #define CFG_PCMCIA_IO_ADDR (0xEC000000) | |
289 | #define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) | |
e7df029f | 290 | #define PCMCIA_MEM_WIN_NO 8 /* override default 4 in pcmcia.h */ |
291 | #define PCMCIA_SOCKETS_NO 2 /* we have two sockets */ | |
79536a6e | 292 | #undef NSCU_OE_INV /* PCMCIA_GCRX_CXOE was inverted on early boards */ |
f12e568c WD |
293 | |
294 | /*----------------------------------------------------------------------- | |
295 | * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) | |
296 | *----------------------------------------------------------------------- | |
297 | */ | |
298 | ||
299 | #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ | |
300 | ||
301 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ | |
302 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
303 | #undef CONFIG_IDE_RESET /* reset for ide not supported */ | |
304 | ||
e7df029f | 305 | #define CFG_IDE_MAXBUS 2 /* max. 2 IDE buses */ |
306 | #define CFG_IDE_MAXDEVICE 4 /* max. 2 drives per IDE bus */ | |
f12e568c WD |
307 | |
308 | #define CFG_ATA_IDE0_OFFSET 0x0000 | |
e7df029f | 309 | #define CFG_ATA_IDE1_OFFSET (4 * CFG_PCMCIA_MEM_SIZE) /* starts @ 4th window */ |
f12e568c WD |
310 | |
311 | #define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR | |
312 | ||
313 | /* Offset for data I/O */ | |
314 | #define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) | |
315 | ||
316 | /* Offset for normal register accesses */ | |
317 | #define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) | |
318 | ||
319 | /* Offset for alternate registers */ | |
320 | #define CFG_ATA_ALT_OFFSET 0x0100 | |
321 | ||
322 | /*----------------------------------------------------------------------- | |
323 | * | |
324 | *----------------------------------------------------------------------- | |
325 | * | |
326 | */ | |
327 | #define CFG_DER 0 | |
328 | ||
329 | /* | |
330 | * Init Memory Controller: | |
331 | * | |
332 | * BR0/1 and OR0/1 (FLASH) | |
333 | */ | |
334 | ||
335 | #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ | |
336 | #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ | |
337 | ||
338 | /* used to re-map FLASH both when starting from SRAM or FLASH: | |
339 | * restrict access enough to keep SRAM working (if any) | |
340 | * but not too much to meddle with FLASH accesses | |
341 | */ | |
342 | #define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ | |
343 | #define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ | |
344 | ||
345 | /* | |
346 | * FLASH timing: | |
347 | */ | |
f12e568c WD |
348 | #define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ |
349 | OR_SCY_3_CLK | OR_EHTR | OR_BI) | |
f12e568c WD |
350 | |
351 | #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) | |
352 | #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) | |
353 | #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) | |
354 | ||
355 | #define CFG_OR1_REMAP CFG_OR0_REMAP | |
356 | #define CFG_OR1_PRELIM CFG_OR0_PRELIM | |
357 | #define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) | |
358 | ||
359 | /* | |
360 | * BR2/3 and OR2/3 (SDRAM) | |
361 | * | |
362 | */ | |
363 | #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ | |
364 | #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ | |
365 | #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ | |
366 | ||
367 | /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ | |
368 | #define CFG_OR_TIMING_SDRAM 0x00000A00 | |
369 | ||
370 | #define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) | |
371 | #define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) | |
372 | ||
373 | #ifndef CONFIG_CAN_DRIVER | |
374 | #define CFG_OR3_PRELIM CFG_OR2_PRELIM | |
375 | #define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) | |
376 | #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ | |
377 | #define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ | |
378 | #define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ | |
379 | #define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI) | |
380 | #define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \ | |
381 | BR_PS_8 | BR_MS_UPMB | BR_V ) | |
382 | #endif /* CONFIG_CAN_DRIVER */ | |
383 | ||
bdccc4fe WD |
384 | #ifdef CONFIG_ISP1362_USB |
385 | #define CFG_ISP1362_BASE 0xD0000000 /* ISP1362 mapped at 0xD0000000 */ | |
386 | #define CFG_ISP1362_OR_AM 0xFFFF8000 /* 32 kB address mask */ | |
387 | #define CFG_OR5_ISP1362 (CFG_ISP1362_OR_AM | OR_CSNT_SAM | \ | |
388 | OR_ACS_DIV2 | OR_BI | OR_SCY_5_CLK) | |
389 | #define CFG_BR5_ISP1362 ((CFG_ISP1362_BASE & BR_BA_MSK) | \ | |
390 | BR_PS_16 | BR_MS_GPCM | BR_V ) | |
391 | #endif /* CONFIG_ISP1362_USB */ | |
42d1f039 | 392 | |
f12e568c WD |
393 | /* |
394 | * Memory Periodic Timer Prescaler | |
395 | * | |
396 | * The Divider for PTA (refresh timer) configuration is based on an | |
397 | * example SDRAM configuration (64 MBit, one bank). The adjustment to | |
398 | * the number of chip selects (NCS) and the actually needed refresh | |
399 | * rate is done by setting MPTPR. | |
400 | * | |
401 | * PTA is calculated from | |
402 | * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) | |
403 | * | |
404 | * gclk CPU clock (not bus clock!) | |
405 | * Trefresh Refresh cycle * 4 (four word bursts used) | |
406 | * | |
407 | * 4096 Rows from SDRAM example configuration | |
408 | * 1000 factor s -> ms | |
409 | * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration | |
410 | * 4 Number of refresh cycles per period | |
411 | * 64 Refresh cycle in ms per number of rows | |
412 | * -------------------------------------------- | |
413 | * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 | |
414 | * | |
415 | * 50 MHz => 50.000.000 / Divider = 98 | |
416 | * 66 Mhz => 66.000.000 / Divider = 129 | |
417 | * 80 Mhz => 80.000.000 / Divider = 156 | |
418 | */ | |
cfca5e60 WD |
419 | |
420 | #define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) | |
421 | #define CFG_MAMR_PTA 98 | |
f12e568c WD |
422 | |
423 | /* | |
424 | * For 16 MBit, refresh rates could be 31.3 us | |
425 | * (= 64 ms / 2K = 125 / quad bursts). | |
426 | * For a simpler initialization, 15.6 us is used instead. | |
427 | * | |
428 | * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks | |
429 | * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank | |
430 | */ | |
431 | #define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ | |
432 | #define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ | |
433 | ||
434 | /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ | |
435 | #define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ | |
436 | #define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ | |
437 | ||
438 | /* | |
439 | * MAMR settings for SDRAM | |
440 | */ | |
441 | ||
442 | /* 8 column SDRAM */ | |
443 | #define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ | |
444 | MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ | |
445 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
446 | /* 9 column SDRAM */ | |
447 | #define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ | |
448 | MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ | |
449 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
450 | ||
451 | ||
452 | /* | |
453 | * Internal Definitions | |
454 | * | |
455 | * Boot Flags | |
456 | */ | |
457 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
458 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
459 | ||
460 | #undef CONFIG_SCC1_ENET | |
461 | #define CONFIG_FEC_ENET | |
462 | /* #define CONFIG_ETHPRIME "FEC ETHERNET" */ | |
463 | ||
464 | #endif /* __CONFIG_H */ |