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f12e568c | 1 | /* |
29f8f58f | 2 | * (C) Copyright 2000-2008 |
f12e568c WD |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * board/config.h - configuration options, board specific | |
26 | */ | |
27 | ||
28 | #ifndef __CONFIG_H | |
29 | #define __CONFIG_H | |
30 | ||
31 | /* | |
32 | * High Level Configuration Options | |
33 | * (easy to change) | |
34 | */ | |
35 | ||
36 | #define CONFIG_MPC855 1 /* This is a MPC855 CPU */ | |
37 | #define CONFIG_TQM855M 1 /* ...on a TQM8xxM module */ | |
e7df029f | 38 | #define CONFIG_NSCU 1 |
f12e568c WD |
39 | |
40 | #define CONFIG_8xx_CONS_SCC1 1 /* Console is on SMC1 */ | |
3cb7a480 WD |
41 | #define CONFIG_SYS_SMC_RXBUFLEN 128 |
42 | #define CONFIG_SYS_MAXIDLE 10 | |
f12e568c WD |
43 | |
44 | #define CONFIG_66MHz 1 /* running at 66 MHz, 1:1 clock */ | |
45 | ||
46 | #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ | |
47 | ||
48 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
49 | ||
f12e568c WD |
50 | #define CONFIG_BOARD_TYPES 1 /* support board types */ |
51 | ||
52 | #define CONFIG_PREBOOT "echo;" \ | |
32bf3d14 | 53 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
f12e568c WD |
54 | "echo" |
55 | ||
56 | #undef CONFIG_BOOTARGS | |
57 | ||
58 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
59 | "netdev=eth0\0" \ | |
60 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
fe126d8b | 61 | "nfsroot=${serverip}:${rootpath}\0" \ |
f12e568c | 62 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
fe126d8b WD |
63 | "addip=setenv bootargs ${bootargs} " \ |
64 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
65 | ":${hostname}:${netdev}:off panic=1\0" \ | |
f12e568c | 66 | "flash_nfs=run nfsargs addip;" \ |
fe126d8b | 67 | "bootm ${kernel_addr}\0" \ |
f12e568c | 68 | "flash_self=run ramargs addip;" \ |
fe126d8b WD |
69 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
70 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ | |
f12e568c | 71 | "rootpath=/opt/eldk/ppc_8xx\0" \ |
29f8f58f WD |
72 | "hostname=NSCU\0" \ |
73 | "bootfile=${hostname}/uImage\0" \ | |
f12e568c WD |
74 | "kernel_addr=40080000\0" \ |
75 | "ramdisk_addr=40180000\0" \ | |
29f8f58f WD |
76 | "u-boot=${hostname}/u-image.bin\0" \ |
77 | "load=tftp 200000 ${u-boot}\0" \ | |
78 | "update=prot off 40000000 +${filesize};" \ | |
79 | "era 40000000 +${filesize};" \ | |
80 | "cp.b 200000 40000000 ${filesize};" \ | |
81 | "sete filesize;save\0" \ | |
f12e568c WD |
82 | "" |
83 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
84 | ||
cfca5e60 WD |
85 | #define CONFIG_MISC_INIT_R 1 |
86 | ||
f12e568c | 87 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
6d0f6bcf | 88 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
f12e568c WD |
89 | |
90 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
91 | ||
92 | #define CONFIG_STATUS_LED 1 /* Status LED enabled */ | |
93 | ||
94 | #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ | |
95 | ||
7be044e4 JL |
96 | /* |
97 | * BOOTP options | |
98 | */ | |
99 | #define CONFIG_BOOTP_SUBNETMASK | |
100 | #define CONFIG_BOOTP_GATEWAY | |
101 | #define CONFIG_BOOTP_HOSTNAME | |
102 | #define CONFIG_BOOTP_BOOTPATH | |
103 | #define CONFIG_BOOTP_BOOTFILESIZE | |
104 | ||
f12e568c WD |
105 | |
106 | #define CONFIG_MAC_PARTITION | |
107 | #define CONFIG_DOS_PARTITION | |
108 | ||
109 | #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ | |
110 | ||
bdccc4fe WD |
111 | #define CONFIG_ISP1362_USB /* ISP1362 USB OTG controller */ |
112 | ||
f12e568c | 113 | |
e18a1061 JL |
114 | /* |
115 | * Command line configuration. | |
116 | */ | |
117 | #include <config_cmd_default.h> | |
118 | ||
119 | #define CONFIG_CMD_ASKENV | |
120 | #define CONFIG_CMD_DATE | |
121 | #define CONFIG_CMD_DHCP | |
29f8f58f | 122 | #define CONFIG_CMD_ELF |
e18a1061 JL |
123 | #define CONFIG_CMD_IDE |
124 | #define CONFIG_CMD_NFS | |
125 | #define CONFIG_CMD_SNTP | |
126 | ||
f12e568c | 127 | |
29f8f58f WD |
128 | #define CONFIG_NETCONSOLE |
129 | ||
130 | ||
f12e568c WD |
131 | /* |
132 | * Miscellaneous configurable options | |
133 | */ | |
6d0f6bcf JCPV |
134 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
135 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
f12e568c | 136 | |
29f8f58f WD |
137 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history |
138 | */ | |
6d0f6bcf JCPV |
139 | #define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ |
140 | #ifdef CONFIG_SYS_HUSH_PARSER | |
141 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
f12e568c WD |
142 | #endif |
143 | ||
e18a1061 | 144 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 145 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
f12e568c | 146 | #else |
6d0f6bcf | 147 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
f12e568c | 148 | #endif |
6d0f6bcf JCPV |
149 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
150 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
151 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
f12e568c | 152 | |
6d0f6bcf JCPV |
153 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
154 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
f12e568c | 155 | |
6d0f6bcf | 156 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
f12e568c | 157 | |
6d0f6bcf | 158 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
f12e568c | 159 | |
6d0f6bcf | 160 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
f12e568c WD |
161 | |
162 | /* | |
163 | * Low Level Configuration Settings | |
164 | * (address mappings, register initial values, etc.) | |
165 | * You should know what you are doing if you make changes here. | |
166 | */ | |
167 | /*----------------------------------------------------------------------- | |
168 | * Internal Memory Mapped Register | |
169 | */ | |
6d0f6bcf | 170 | #define CONFIG_SYS_IMMR 0xFFF00000 |
f12e568c WD |
171 | |
172 | /*----------------------------------------------------------------------- | |
173 | * Definitions for initial stack pointer and data area (in DPRAM) | |
174 | */ | |
6d0f6bcf JCPV |
175 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
176 | #define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ | |
177 | #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ | |
178 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
179 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
f12e568c WD |
180 | |
181 | /*----------------------------------------------------------------------- | |
182 | * Start addresses for the final memory configuration | |
183 | * (Set up by the startup code) | |
6d0f6bcf | 184 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
f12e568c | 185 | */ |
6d0f6bcf JCPV |
186 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
187 | #define CONFIG_SYS_FLASH_BASE 0x40000000 | |
188 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
189 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
190 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
f12e568c WD |
191 | |
192 | /* | |
193 | * For booting Linux, the board info and command line data | |
194 | * have to be in the first 8 MB of memory, since this is | |
195 | * the maximum mapped by the Linux kernel during initialization. | |
196 | */ | |
6d0f6bcf | 197 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
f12e568c WD |
198 | |
199 | /*----------------------------------------------------------------------- | |
200 | * FLASH organization | |
201 | */ | |
f12e568c | 202 | |
29f8f58f | 203 | /* use CFI flash driver */ |
6d0f6bcf | 204 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ |
00b1883a | 205 | #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ |
6d0f6bcf JCPV |
206 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size } |
207 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
208 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 | |
209 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ | |
210 | #define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ | |
f12e568c | 211 | |
5a1aceb0 | 212 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
213 | #define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ |
214 | #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ | |
f12e568c WD |
215 | |
216 | /* Address and size of Redundant Environment Sector */ | |
0e8d1586 JCPV |
217 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) |
218 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
f12e568c | 219 | |
6d0f6bcf | 220 | #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ |
29f8f58f | 221 | |
f12e568c WD |
222 | /*----------------------------------------------------------------------- |
223 | * Hardware Information Block | |
224 | */ | |
6d0f6bcf JCPV |
225 | #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ |
226 | #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ | |
227 | #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ | |
f12e568c WD |
228 | |
229 | /*----------------------------------------------------------------------- | |
230 | * Cache Configuration | |
231 | */ | |
6d0f6bcf | 232 | #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
e18a1061 | 233 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 234 | #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
f12e568c WD |
235 | #endif |
236 | ||
237 | /*----------------------------------------------------------------------- | |
238 | * SYPCR - System Protection Control 11-9 | |
239 | * SYPCR can only be written once after reset! | |
240 | *----------------------------------------------------------------------- | |
241 | * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze | |
242 | */ | |
243 | #if defined(CONFIG_WATCHDOG) | |
6d0f6bcf | 244 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
f12e568c WD |
245 | SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
246 | #else | |
6d0f6bcf | 247 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
f12e568c WD |
248 | #endif |
249 | ||
250 | /*----------------------------------------------------------------------- | |
251 | * SIUMCR - SIU Module Configuration 11-6 | |
252 | *----------------------------------------------------------------------- | |
253 | * PCMCIA config., multi-function pin tri-state | |
254 | */ | |
255 | #ifndef CONFIG_CAN_DRIVER | |
6d0f6bcf | 256 | #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
f12e568c | 257 | #else /* we must activate GPL5 in the SIUMCR for CAN */ |
6d0f6bcf | 258 | #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
f12e568c WD |
259 | #endif /* CONFIG_CAN_DRIVER */ |
260 | ||
261 | /*----------------------------------------------------------------------- | |
262 | * TBSCR - Time Base Status and Control 11-26 | |
263 | *----------------------------------------------------------------------- | |
264 | * Clear Reference Interrupt Status, Timebase freezing enabled | |
265 | */ | |
6d0f6bcf | 266 | #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
f12e568c WD |
267 | |
268 | /*----------------------------------------------------------------------- | |
269 | * RTCSC - Real-Time Clock Status and Control Register 11-27 | |
270 | *----------------------------------------------------------------------- | |
271 | */ | |
6d0f6bcf | 272 | #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) |
f12e568c WD |
273 | |
274 | /*----------------------------------------------------------------------- | |
275 | * PISCR - Periodic Interrupt Status and Control 11-31 | |
276 | *----------------------------------------------------------------------- | |
277 | * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled | |
278 | */ | |
6d0f6bcf | 279 | #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) |
f12e568c WD |
280 | |
281 | /*----------------------------------------------------------------------- | |
282 | * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 | |
283 | *----------------------------------------------------------------------- | |
284 | * Reset PLL lock status sticky bit, timer expired status bit and timer | |
285 | * interrupt status bit | |
f12e568c | 286 | */ |
6d0f6bcf | 287 | #define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) |
f12e568c WD |
288 | |
289 | /*----------------------------------------------------------------------- | |
290 | * SCCR - System Clock and reset Control Register 15-27 | |
291 | *----------------------------------------------------------------------- | |
292 | * Set clock output, timebase and RTC source and divider, | |
293 | * power management and some other internal clocks | |
294 | */ | |
295 | #define SCCR_MASK SCCR_EBDF11 | |
6d0f6bcf | 296 | #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ |
f12e568c WD |
297 | SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ |
298 | SCCR_DFALCD00) | |
f12e568c WD |
299 | |
300 | /*----------------------------------------------------------------------- | |
301 | * PCMCIA stuff | |
302 | *----------------------------------------------------------------------- | |
303 | * | |
304 | */ | |
e7df029f | 305 | /* NSCU use both slots, SLOT_A as "primary". */ |
306 | #define CONFIG_PCMCIA_SLOT_A 1 | |
307 | ||
6d0f6bcf JCPV |
308 | #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) |
309 | #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) | |
310 | #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) | |
311 | #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) | |
312 | #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) | |
313 | #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) | |
314 | #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) | |
315 | #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) | |
53677ef1 WD |
316 | #define PCMCIA_MEM_WIN_NO 8 /* override default 4 in pcmcia.h */ |
317 | #define PCMCIA_SOCKETS_NO 2 /* we have two sockets */ | |
79536a6e | 318 | #undef NSCU_OE_INV /* PCMCIA_GCRX_CXOE was inverted on early boards */ |
f12e568c WD |
319 | |
320 | /*----------------------------------------------------------------------- | |
321 | * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) | |
322 | *----------------------------------------------------------------------- | |
323 | */ | |
324 | ||
325 | #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ | |
326 | ||
327 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ | |
328 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
329 | #undef CONFIG_IDE_RESET /* reset for ide not supported */ | |
330 | ||
6d0f6bcf JCPV |
331 | #define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE buses */ |
332 | #define CONFIG_SYS_IDE_MAXDEVICE 4 /* max. 2 drives per IDE bus */ | |
f12e568c | 333 | |
6d0f6bcf JCPV |
334 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
335 | #define CONFIG_SYS_ATA_IDE1_OFFSET (4 * CONFIG_SYS_PCMCIA_MEM_SIZE) /* starts @ 4th window */ | |
f12e568c | 336 | |
6d0f6bcf | 337 | #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR |
f12e568c WD |
338 | |
339 | /* Offset for data I/O */ | |
6d0f6bcf | 340 | #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
f12e568c WD |
341 | |
342 | /* Offset for normal register accesses */ | |
6d0f6bcf | 343 | #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
f12e568c WD |
344 | |
345 | /* Offset for alternate registers */ | |
6d0f6bcf | 346 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 |
f12e568c WD |
347 | |
348 | /*----------------------------------------------------------------------- | |
349 | * | |
350 | *----------------------------------------------------------------------- | |
351 | * | |
352 | */ | |
6d0f6bcf | 353 | #define CONFIG_SYS_DER 0 |
f12e568c WD |
354 | |
355 | /* | |
356 | * Init Memory Controller: | |
357 | * | |
358 | * BR0/1 and OR0/1 (FLASH) | |
359 | */ | |
360 | ||
361 | #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ | |
362 | #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ | |
363 | ||
364 | /* used to re-map FLASH both when starting from SRAM or FLASH: | |
365 | * restrict access enough to keep SRAM working (if any) | |
366 | * but not too much to meddle with FLASH accesses | |
367 | */ | |
6d0f6bcf JCPV |
368 | #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ |
369 | #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ | |
f12e568c WD |
370 | |
371 | /* | |
372 | * FLASH timing: | |
373 | */ | |
6d0f6bcf | 374 | #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ |
f12e568c | 375 | OR_SCY_3_CLK | OR_EHTR | OR_BI) |
f12e568c | 376 | |
6d0f6bcf JCPV |
377 | #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
378 | #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) | |
379 | #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) | |
f12e568c | 380 | |
6d0f6bcf JCPV |
381 | #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP |
382 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM | |
383 | #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) | |
f12e568c WD |
384 | |
385 | /* | |
386 | * BR2/3 and OR2/3 (SDRAM) | |
387 | * | |
388 | */ | |
389 | #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ | |
390 | #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ | |
391 | #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ | |
392 | ||
393 | /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ | |
6d0f6bcf | 394 | #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 |
f12e568c | 395 | |
6d0f6bcf JCPV |
396 | #define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) |
397 | #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) | |
f12e568c WD |
398 | |
399 | #ifndef CONFIG_CAN_DRIVER | |
6d0f6bcf JCPV |
400 | #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM |
401 | #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) | |
f12e568c | 402 | #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ |
6d0f6bcf JCPV |
403 | #define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ |
404 | #define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ | |
405 | #define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) | |
406 | #define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ | |
f12e568c WD |
407 | BR_PS_8 | BR_MS_UPMB | BR_V ) |
408 | #endif /* CONFIG_CAN_DRIVER */ | |
409 | ||
bdccc4fe | 410 | #ifdef CONFIG_ISP1362_USB |
6d0f6bcf JCPV |
411 | #define CONFIG_SYS_ISP1362_BASE 0xD0000000 /* ISP1362 mapped at 0xD0000000 */ |
412 | #define CONFIG_SYS_ISP1362_OR_AM 0xFFFF8000 /* 32 kB address mask */ | |
413 | #define CONFIG_SYS_OR5_ISP1362 (CONFIG_SYS_ISP1362_OR_AM | OR_CSNT_SAM | \ | |
bdccc4fe | 414 | OR_ACS_DIV2 | OR_BI | OR_SCY_5_CLK) |
6d0f6bcf | 415 | #define CONFIG_SYS_BR5_ISP1362 ((CONFIG_SYS_ISP1362_BASE & BR_BA_MSK) | \ |
bdccc4fe WD |
416 | BR_PS_16 | BR_MS_GPCM | BR_V ) |
417 | #endif /* CONFIG_ISP1362_USB */ | |
42d1f039 | 418 | |
f12e568c WD |
419 | /* |
420 | * Memory Periodic Timer Prescaler | |
421 | * | |
422 | * The Divider for PTA (refresh timer) configuration is based on an | |
423 | * example SDRAM configuration (64 MBit, one bank). The adjustment to | |
424 | * the number of chip selects (NCS) and the actually needed refresh | |
425 | * rate is done by setting MPTPR. | |
426 | * | |
427 | * PTA is calculated from | |
428 | * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) | |
429 | * | |
430 | * gclk CPU clock (not bus clock!) | |
431 | * Trefresh Refresh cycle * 4 (four word bursts used) | |
432 | * | |
433 | * 4096 Rows from SDRAM example configuration | |
434 | * 1000 factor s -> ms | |
435 | * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration | |
436 | * 4 Number of refresh cycles per period | |
437 | * 64 Refresh cycle in ms per number of rows | |
438 | * -------------------------------------------- | |
439 | * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 | |
440 | * | |
441 | * 50 MHz => 50.000.000 / Divider = 98 | |
442 | * 66 Mhz => 66.000.000 / Divider = 129 | |
443 | * 80 Mhz => 80.000.000 / Divider = 156 | |
444 | */ | |
cfca5e60 | 445 | |
6d0f6bcf JCPV |
446 | #define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) |
447 | #define CONFIG_SYS_MAMR_PTA 98 | |
f12e568c WD |
448 | |
449 | /* | |
450 | * For 16 MBit, refresh rates could be 31.3 us | |
451 | * (= 64 ms / 2K = 125 / quad bursts). | |
452 | * For a simpler initialization, 15.6 us is used instead. | |
453 | * | |
6d0f6bcf JCPV |
454 | * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks |
455 | * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank | |
f12e568c | 456 | */ |
6d0f6bcf JCPV |
457 | #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ |
458 | #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ | |
f12e568c WD |
459 | |
460 | /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ | |
6d0f6bcf JCPV |
461 | #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ |
462 | #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ | |
f12e568c WD |
463 | |
464 | /* | |
465 | * MAMR settings for SDRAM | |
466 | */ | |
467 | ||
468 | /* 8 column SDRAM */ | |
6d0f6bcf | 469 | #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
f12e568c WD |
470 | MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ |
471 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
472 | /* 9 column SDRAM */ | |
6d0f6bcf | 473 | #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
f12e568c WD |
474 | MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ |
475 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
476 | ||
477 | ||
478 | /* | |
479 | * Internal Definitions | |
480 | * | |
481 | * Boot Flags | |
482 | */ | |
483 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
484 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
485 | ||
486 | #undef CONFIG_SCC1_ENET | |
487 | #define CONFIG_FEC_ENET | |
488 | /* #define CONFIG_ETHPRIME "FEC ETHERNET" */ | |
489 | ||
490 | #endif /* __CONFIG_H */ |