[people/ms/u-boot.git] / include / configs / NX823.h

/*
 * (C) Copyright 2001
 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
 *
 * (C) Copyright 2001
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC823		1	/* This is a MPC823 CPU	    */
#define CONFIG_NX823		1	/* ...on a NEXUS 823  module	*/

#define	CONFIG_SYS_TEXT_BASE	0x40000000

/*#define  CONFIG_VIDEO		1 */

#define CONFIG_8xx_GCLK_FREQ	MPC8XX_SPEED
#define CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1	    */
#undef	CONFIG_8xx_CONS_SMC2
#undef	CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE 57600	/* console baudrate = 115kbps	*/
#define CONFIG_BOOTDELAY	2	/* autoboot after 2 seconds */
#define CONFIG_BOOTARGS		"ramdisk_size=8000 "\
				"root=/dev/nfs rw nfsroot=10.77.77.250:/ppcroot "\
				"nfsaddrs=10.77.77.20:10.77.77.250"
#define CONFIG_BOOTCOMMAND	"bootm 400e0000"

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
#undef	CONFIG_WATCHDOG			/* watchdog disabled, for now	    */
#define CONFIG_SOURCE

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_SOURCE


/* call various generic functions */
#define CONFIG_MISC_INIT_R

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
#else
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CONFIG_SYS_IMMR		0xFFF00000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
#define CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH_BASE		0x40000000
#define CONFIG_SYS_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor	*/
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks	    */
#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)  */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)  */

#define CONFIG_ENV_IS_IN_FLASH	1
#define xEMBED
#ifdef	EMBED
#define CONFIG_ENV_SIZE		0x200	/* FIXME How big when embedded?? */
#define CONFIG_ENV_ADDR		CONFIG_SYS_MONITOR_BASE
#else
#define CONFIG_ENV_ADDR		0x40020000	/* absolute address for now   */
#define CONFIG_ENV_SIZE		0x20000 /* 8K ouch, this may later be */
#endif

#define CONFIG_SYS_FLASH_SN_BASE	0x4001fff0	/* programmer automagically puts    */
#define CONFIG_SYS_FLASH_SN_SECTOR	0x40000000	/* a serial number here		    */
#define CONFIG_SYS_FLASH_SN_BYTES	8

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs		*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value    */
#endif

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#if defined(CONFIG_WATCHDOG)
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWP)
#else
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				12-30
 *-----------------------------------------------------------------------
 * PCMCIA config., multi-function pin tri-state
 */
#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00)

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control				12-16
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)

/*-----------------------------------------------------------------------
 * RTCSC - Real-Time Clock Status and Control Register		12-18
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		12-23
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)

/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register		5-7
 *-----------------------------------------------------------------------
 * Reset PLL lock status sticky bit, timer expired status bit and timer
 * interrupt status bit
 */
#define MPC8XX_SPEED	66666666L
#define MPC8XX_XIN	32768	/* 32.768 kHz crystal */
#define MPC8XX_FACT		(MPC8XX_SPEED/MPC8XX_XIN)
#define CONFIG_SYS_PLPRCR_MF  ((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT)
#define CONFIG_SYS_PLPRCR		(CONFIG_SYS_PLPRCR_MF | PLPRCR_TEXPS | PLPRCR_TMIST)

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		5-3
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
#define SCCR_MASK	SCCR_EBDF11
#define CONFIG_SYS_SCCR	(SCCR_TBS     | \
			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
			 SCCR_DFALCD00)

/*-----------------------------------------------------------------------
 *
 *-----------------------------------------------------------------------
 *
 */
#define CONFIG_SYS_DER		0

/*
 * Init Memory Controller:
 *
 * BR0 and OR0 (FLASH)
 */

#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0    */

/* used to re-map FLASH both when starting from SRAM or FLASH:
 * restrict access enough to keep SRAM working (if any)
 * but not too much to meddle with FLASH accesses
 */
#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */

/* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 8, EHTR = 0	*/
#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV1 | OR_BI | \
				 OR_SCY_8_CLK )

#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )

/*
 * BR1/2 and OR1/2 (SDRAM)
 */
#define SDRAM_BASE1_PRELIM	0x00000000	/* SDRAM bank #0    */
#define SDRAM_BASE2_PRELIM	0x20000000	/* SDRAM bank #1    */
#define SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/

/* SDRAM timing: Multiplexed addresses, drive GPL5 high on first cycle */
#define CONFIG_SYS_OR_TIMING_SDRAM	(OR_G5LS | OR_CSNT_SAM)

#define CONFIG_SYS_OR1_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
#define CONFIG_SYS_BR1_PRELIM	((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
#define CONFIG_SYS_OR2_PRELIM	CONFIG_SYS_OR1_PRELIM
#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )

/* IO and memory mapped stuff */
#define NX823_IO_OR_AM		0xFFFF0000	/* mask for IO addresses */
#define NX823_IO_BASE		0xFF000000	/* start of IO	*/
#define GPOUT_OFFSET		(3<<16)
#define QUART_OFFSET		(4<<16)
#define VIDAC_OFFSET		(5<<16)
#define CPLD_OFFSET		(6<<16)
#define SED1386_OFFSET		(7<<16)

/*
 * BR3 and OR3 (general purpose output latches)
 */
#define GPOUT_BASE	(NX823_IO_BASE + GPOUT_OFFSET)
#define GPOUT_TIMING	(OR_CSNT_SAM | OR_TRLX | OR_BI)
#define CONFIG_SYS_OR3_PRELIM	(NX823_IO_OR_AM | GPOUT_TIMING)
#define CONFIG_SYS_BR3_PRELIM	(GPOUT_BASE | BR_V)

/*
 * BR4 and OR4 (QUART)
 */
#define QUART_BASE	(NX823_IO_BASE + QUART_OFFSET)
#define QUART_TIMING	(OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_TRLX)
#define CONFIG_SYS_OR4_PRELIM	(NX823_IO_OR_AM | QUART_TIMING | OR_BI)
#define CONFIG_SYS_BR4_PRELIM	(QUART_BASE | BR_PS_8 | BR_V)

/*
 * BR5 and OR5 (Video DAC)
 */
#define VIDAC_BASE	(NX823_IO_BASE + VIDAC_OFFSET)
#define VIDAC_TIMING	(OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_EHTR)
#define CONFIG_SYS_OR5_PRELIM	(NX823_IO_OR_AM | VIDAC_TIMING | OR_BI)
#define CONFIG_SYS_BR5_PRELIM	(VIDAC_BASE | BR_PS_8 | BR_V)

/*
 * BR6 and OR6 (CPLD)
 * FIXME timing not verified for CPLD
 */
#define CPLD_BASE	(NX823_IO_BASE + CPLD_OFFSET)
#define CPLD_TIMING	(OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_EHTR)
#define CONFIG_SYS_OR6_PRELIM	(NX823_IO_OR_AM | CPLD_TIMING | OR_BI)
#define CONFIG_SYS_BR6_PRELIM	(CPLD_BASE | BR_PS_8 | BR_V )

/*
 * BR7 and OR7 (SED1386)
 * FIXME timing not verified for SED controller
 */
#define SED1386_BASE	0xF7000000
#define CONFIG_SYS_OR7_PRELIM	(0xFF000000 | OR_BI | OR_SETA)
#define CONFIG_SYS_BR7_PRELIM	(SED1386_BASE | BR_PS_16 | BR_V )

/*
 * Memory Periodic Timer Prescaler
 */

/* periodic timer for refresh */
#define CONFIG_SYS_MAMR_PTA	97		/* start with divider for 100 MHz   */

/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16 /* setting for 2 banks	*/
#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32 /* setting for 1 bank	*/

/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8	/* setting for 2 banks	*/
#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16 /* setting for 1 bank	*/

/*
 * MAMR settings for SDRAM
 */

/* 8 column SDRAM */
#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
/* 9 column SDRAM */
#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)

#define CONFIG_ENV_OVERWRITE	/* allow changes to ethaddr (for now)	*/
#define CONFIG_ETHADDR		00:10:20:30:40:50
#define CONFIG_IPADDR		10.77.77.20
#define CONFIG_SERVERIP		10.77.77.250

#endif /* __CONFIG_H */
Commit	Line	Data
c12b5a32 WD	1	/*
	2	* (C) Copyright 2001
	3	* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
	4	*
	5	* (C) Copyright 2001
	6	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	7	*
3765b3e7	8	* SPDX-License-Identifier: GPL-2.0+
c12b5a32 WD	9	*/
	10
	11	/*
	12	* board/config.h - configuration options, board specific
	13	*/
	14
	15	#ifndef __CONFIG_H
	16	#define __CONFIG_H
	17
	18	/*
	19	* High Level Configuration Options
	20	* (easy to change)
	21	*/
	22
	23	#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
	24	#define CONFIG_NX823 1 /* ...on a NEXUS 823 module */
	25
2ae18241 WD	26	#define CONFIG_SYS_TEXT_BASE 0x40000000
2ae18241 WD	27
c12b5a32 WD	28	/#define CONFIG_VIDEO 1 /
	29
	30	#define CONFIG_8xx_GCLK_FREQ MPC8XX_SPEED
	31	#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
	32	#undef CONFIG_8xx_CONS_SMC2
	33	#undef CONFIG_8xx_CONS_NONE
	34	#define CONFIG_BAUDRATE 57600 /* console baudrate = 115kbps */
	35	#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */
e5084af8	36	#define CONFIG_BOOTARGS "ramdisk_size=8000 "\
c12b5a32 WD	37	"root=/dev/nfs rw nfsroot=10.77.77.250:/ppcroot "\
	38	"nfsaddrs=10.77.77.20:10.77.77.250"
	39	#define CONFIG_BOOTCOMMAND "bootm 400e0000"
	40
	41	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	42	#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
c12b5a32	43	#undef CONFIG_WATCHDOG /* watchdog disabled, for now */
74de7aef	44	#define CONFIG_SOURCE
c12b5a32	45
7be044e4 JL	46	/*
	47	* BOOTP options
	48	*/
	49	#define CONFIG_BOOTP_SUBNETMASK
	50	#define CONFIG_BOOTP_GATEWAY
	51	#define CONFIG_BOOTP_HOSTNAME
	52	#define CONFIG_BOOTP_BOOTPATH
	53	#define CONFIG_BOOTP_BOOTFILESIZE
	54
e18a1061 JL	55
	56	/*
	57	* Command line configuration.
	58	*/
	59	#include <config_cmd_default.h>
	60
74de7aef	61	#define CONFIG_CMD_SOURCE
e18a1061 JL	62
e18a1061 JL	63
c12b5a32 WD	64	/* call various generic functions */
	65	#define CONFIG_MISC_INIT_R
	66
c12b5a32 WD	67	/*
	68	* Miscellaneous configurable options
	69	*/
6d0f6bcf	70	#define CONFIG_SYS_LONGHELP /* undef to save memory */
e18a1061	71	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	72	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
c12b5a32	73	#else
6d0f6bcf	74	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
c12b5a32	75	#endif
6d0f6bcf JCPV	76	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	77	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	78	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
c12b5a32	79
6d0f6bcf JCPV	80	#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
6d0f6bcf JCPV	81	#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
c12b5a32	82
6d0f6bcf	83	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
c12b5a32	84
c12b5a32 WD	85	/*
	86	* Low Level Configuration Settings
	87	* (address mappings, register initial values, etc.)
	88	* You should know what you are doing if you make changes here.
	89	*/
	90	/*-----------------------------------------------------------------------
	91	* Internal Memory Mapped Register
	92	*/
6d0f6bcf	93	#define CONFIG_SYS_IMMR 0xFFF00000
c12b5a32 WD	94
	95	/*-----------------------------------------------------------------------
	96	* Definitions for initial stack pointer and data area (in DPRAM)
	97	*/
6d0f6bcf	98	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
553f0982	99	#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
25ddd1fb	100	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	101	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
c12b5a32 WD	102
	103	/*-----------------------------------------------------------------------
	104	* Start addresses for the final memory configuration
	105	* (Set up by the startup code)
6d0f6bcf	106	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
c12b5a32	107	*/
6d0f6bcf JCPV	108	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	109	#define CONFIG_SYS_FLASH_BASE 0x40000000
	110	#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
	111	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	112	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
c12b5a32 WD	113
	114	/*
	115	* For booting Linux, the board info and command line data
	116	* have to be in the first 8 MB of memory, since this is
	117	* the maximum mapped by the Linux kernel during initialization.
	118	*/
6d0f6bcf	119	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
c12b5a32 WD	120
	121	/*-----------------------------------------------------------------------
	122	* FLASH organization
	123	*/
6d0f6bcf JCPV	124	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
6d0f6bcf JCPV	125	#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
c12b5a32	126
6d0f6bcf JCPV	127	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	128	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
c12b5a32	129
5a1aceb0	130	#define CONFIG_ENV_IS_IN_FLASH 1
c12b5a32 WD	131	#define xEMBED
c12b5a32 WD	132	#ifdef EMBED
0e8d1586	133	#define CONFIG_ENV_SIZE 0x200 /* FIXME How big when embedded?? */
6d0f6bcf	134	#define CONFIG_ENV_ADDR CONFIG_SYS_MONITOR_BASE
c12b5a32	135	#else
0e8d1586 JCPV	136	#define CONFIG_ENV_ADDR 0x40020000 /* absolute address for now */
0e8d1586 JCPV	137	#define CONFIG_ENV_SIZE 0x20000 /* 8K ouch, this may later be */
c12b5a32 WD	138	#endif
c12b5a32 WD	139
6d0f6bcf JCPV	140	#define CONFIG_SYS_FLASH_SN_BASE 0x4001fff0 /* programmer automagically puts */
	141	#define CONFIG_SYS_FLASH_SN_SECTOR 0x40000000 /* a serial number here */
	142	#define CONFIG_SYS_FLASH_SN_BYTES 8
c12b5a32 WD	143
	144	/*-----------------------------------------------------------------------
	145	* Cache Configuration
	146	*/
6d0f6bcf	147	#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
e18a1061	148	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	149	#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
c12b5a32 WD	150	#endif
	151
	152	/*-----------------------------------------------------------------------
	153	* SYPCR - System Protection Control 11-9
	154	* SYPCR can only be written once after reset!
	155	*-----------------------------------------------------------------------
	156	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
	157	*/
	158	#if defined(CONFIG_WATCHDOG)
6d0f6bcf	159	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
c12b5a32 WD	160	SYPCR_SWE \| SYPCR_SWP)
c12b5a32 WD	161	#else
6d0f6bcf	162	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| SYPCR_SWP)
c12b5a32 WD	163	#endif
	164
	165	/*-----------------------------------------------------------------------
	166	* SIUMCR - SIU Module Configuration 12-30
	167	*-----------------------------------------------------------------------
	168	* PCMCIA config., multi-function pin tri-state
	169	*/
6d0f6bcf	170	#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 \| SIUMCR_DBPC00)
c12b5a32 WD	171
	172	/*-----------------------------------------------------------------------
	173	* TBSCR - Time Base Status and Control 12-16
	174	*-----------------------------------------------------------------------
	175	* Clear Reference Interrupt Status, Timebase freezing enabled
	176	*/
6d0f6bcf	177	#define CONFIG_SYS_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBF)
c12b5a32 WD	178
	179	/*-----------------------------------------------------------------------
	180	* RTCSC - Real-Time Clock Status and Control Register 12-18
	181	*-----------------------------------------------------------------------
	182	*/
6d0f6bcf	183	#define CONFIG_SYS_RTCSC (RTCSC_SEC \| RTCSC_ALR \| RTCSC_RTF\| RTCSC_RTE)
c12b5a32 WD	184
	185	/*-----------------------------------------------------------------------
	186	* PISCR - Periodic Interrupt Status and Control 12-23
	187	*-----------------------------------------------------------------------
	188	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
	189	*/
6d0f6bcf	190	#define CONFIG_SYS_PISCR (PISCR_PS \| PISCR_PITF)
c12b5a32 WD	191
	192	/*-----------------------------------------------------------------------
	193	* PLPRCR - PLL, Low-Power, and Reset Control Register 5-7
	194	*-----------------------------------------------------------------------
	195	* Reset PLL lock status sticky bit, timer expired status bit and timer
	196	* interrupt status bit
	197	*/
	198	#define MPC8XX_SPEED 66666666L
	199	#define MPC8XX_XIN 32768 /* 32.768 kHz crystal */
	200	#define MPC8XX_FACT (MPC8XX_SPEED/MPC8XX_XIN)
6d0f6bcf JCPV	201	#define CONFIG_SYS_PLPRCR_MF ((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT)
6d0f6bcf JCPV	202	#define CONFIG_SYS_PLPRCR (CONFIG_SYS_PLPRCR_MF \| PLPRCR_TEXPS \| PLPRCR_TMIST)
c12b5a32 WD	203
	204	/*-----------------------------------------------------------------------
	205	* SCCR - System Clock and reset Control Register 5-3
	206	*-----------------------------------------------------------------------
	207	* Set clock output, timebase and RTC source and divider,
	208	* power management and some other internal clocks
	209	*/
	210	#define SCCR_MASK SCCR_EBDF11
6d0f6bcf	211	#define CONFIG_SYS_SCCR (SCCR_TBS \| \
c12b5a32 WD	212	SCCR_COM00 \| SCCR_DFSYNC00 \| SCCR_DFBRG00 \| \
	213	SCCR_DFNL000 \| SCCR_DFNH000 \| SCCR_DFLCD000 \| \
	214	SCCR_DFALCD00)
	215
	216	/*-----------------------------------------------------------------------
	217	*
	218	*-----------------------------------------------------------------------
	219	*
	220	*/
6d0f6bcf	221	#define CONFIG_SYS_DER 0
c12b5a32 WD	222
	223	/*
	224	* Init Memory Controller:
	225	*
	226	* BR0 and OR0 (FLASH)
	227	*/
	228
	229	#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
	230
	231	/* used to re-map FLASH both when starting from SRAM or FLASH:
	232	* restrict access enough to keep SRAM working (if any)
	233	* but not too much to meddle with FLASH accesses
	234	*/
6d0f6bcf JCPV	235	#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
6d0f6bcf JCPV	236	#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
c12b5a32 WD	237
c12b5a32 WD	238	/* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 8, EHTR = 0 */
6d0f6bcf	239	#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM \| OR_ACS_DIV1 \| OR_BI \| \
c12b5a32 WD	240	OR_SCY_8_CLK )
c12b5a32 WD	241
6d0f6bcf JCPV	242	#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM \| CONFIG_SYS_OR_TIMING_FLASH)
	243	#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \| CONFIG_SYS_OR_TIMING_FLASH)
	244	#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) \| BR_PS_16 \| BR_V )
c12b5a32 WD	245
	246	/*
	247	* BR1/2 and OR1/2 (SDRAM)
	248	*/
	249	#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */
	250	#define SDRAM_BASE2_PRELIM 0x20000000 /* SDRAM bank #1 */
	251	#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
	252
	253	/* SDRAM timing: Multiplexed addresses, drive GPL5 high on first cycle */
6d0f6bcf	254	#define CONFIG_SYS_OR_TIMING_SDRAM (OR_G5LS \| OR_CSNT_SAM)
c12b5a32	255
6d0f6bcf JCPV	256	#define CONFIG_SYS_OR1_PRELIM (CONFIG_SYS_PRELIM_OR_AM \| CONFIG_SYS_OR_TIMING_SDRAM )
	257	#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) \| BR_MS_UPMA \| BR_V )
	258	#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR1_PRELIM
	259	#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) \| BR_MS_UPMA \| BR_V )
c12b5a32 WD	260
	261	/* IO and memory mapped stuff */
	262	#define NX823_IO_OR_AM 0xFFFF0000 /* mask for IO addresses */
	263	#define NX823_IO_BASE 0xFF000000 /* start of IO */
	264	#define GPOUT_OFFSET (3<<16)
	265	#define QUART_OFFSET (4<<16)
	266	#define VIDAC_OFFSET (5<<16)
	267	#define CPLD_OFFSET (6<<16)
	268	#define SED1386_OFFSET (7<<16)
	269
	270	/*
	271	* BR3 and OR3 (general purpose output latches)
	272	*/
	273	#define GPOUT_BASE (NX823_IO_BASE + GPOUT_OFFSET)
	274	#define GPOUT_TIMING (OR_CSNT_SAM \| OR_TRLX \| OR_BI)
6d0f6bcf JCPV	275	#define CONFIG_SYS_OR3_PRELIM (NX823_IO_OR_AM \| GPOUT_TIMING)
6d0f6bcf JCPV	276	#define CONFIG_SYS_BR3_PRELIM (GPOUT_BASE \| BR_V)
c12b5a32 WD	277
	278	/*
	279	* BR4 and OR4 (QUART)
	280	*/
	281	#define QUART_BASE (NX823_IO_BASE + QUART_OFFSET)
	282	#define QUART_TIMING (OR_ACS_DIV4 \| OR_SCY_3_CLK \| OR_CSNT_SAM \| OR_TRLX)
6d0f6bcf JCPV	283	#define CONFIG_SYS_OR4_PRELIM (NX823_IO_OR_AM \| QUART_TIMING \| OR_BI)
6d0f6bcf JCPV	284	#define CONFIG_SYS_BR4_PRELIM (QUART_BASE \| BR_PS_8 \| BR_V)
c12b5a32 WD	285
	286	/*
	287	* BR5 and OR5 (Video DAC)
	288	*/
	289	#define VIDAC_BASE (NX823_IO_BASE + VIDAC_OFFSET)
	290	#define VIDAC_TIMING (OR_ACS_DIV4 \| OR_SCY_3_CLK \| OR_CSNT_SAM \| OR_EHTR)
6d0f6bcf JCPV	291	#define CONFIG_SYS_OR5_PRELIM (NX823_IO_OR_AM \| VIDAC_TIMING \| OR_BI)
6d0f6bcf JCPV	292	#define CONFIG_SYS_BR5_PRELIM (VIDAC_BASE \| BR_PS_8 \| BR_V)
c12b5a32 WD	293
	294	/*
	295	* BR6 and OR6 (CPLD)
	296	* FIXME timing not verified for CPLD
	297	*/
	298	#define CPLD_BASE (NX823_IO_BASE + CPLD_OFFSET)
	299	#define CPLD_TIMING (OR_ACS_DIV4 \| OR_SCY_3_CLK \| OR_CSNT_SAM \| OR_EHTR)
6d0f6bcf JCPV	300	#define CONFIG_SYS_OR6_PRELIM (NX823_IO_OR_AM \| CPLD_TIMING \| OR_BI)
6d0f6bcf JCPV	301	#define CONFIG_SYS_BR6_PRELIM (CPLD_BASE \| BR_PS_8 \| BR_V )
c12b5a32 WD	302
	303	/*
	304	* BR7 and OR7 (SED1386)
	305	* FIXME timing not verified for SED controller
	306	*/
	307	#define SED1386_BASE 0xF7000000
6d0f6bcf JCPV	308	#define CONFIG_SYS_OR7_PRELIM (0xFF000000 \| OR_BI \| OR_SETA)
6d0f6bcf JCPV	309	#define CONFIG_SYS_BR7_PRELIM (SED1386_BASE \| BR_PS_16 \| BR_V )
c12b5a32 WD	310
	311	/*
	312	* Memory Periodic Timer Prescaler
	313	*/
	314
	315	/* periodic timer for refresh */
6d0f6bcf	316	#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */
c12b5a32 WD	317
c12b5a32 WD	318	/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
6d0f6bcf JCPV	319	#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
6d0f6bcf JCPV	320	#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
c12b5a32 WD	321
c12b5a32 WD	322	/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
6d0f6bcf JCPV	323	#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
6d0f6bcf JCPV	324	#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
c12b5a32 WD	325
	326	/*
	327	* MAMR settings for SDRAM
	328	*/
	329
	330	/* 8 column SDRAM */
6d0f6bcf	331	#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
c12b5a32 WD	332	MAMR_AMA_TYPE_0 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A11 \| \
	333	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
	334	/* 9 column SDRAM */
6d0f6bcf	335	#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
c12b5a32 WD	336	MAMR_AMA_TYPE_1 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A10 \| \
	337	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
	338
c12b5a32 WD	339	#define CONFIG_ENV_OVERWRITE /* allow changes to ethaddr (for now) */
	340	#define CONFIG_ETHADDR 00:10:20:30:40:50
	341	#define CONFIG_IPADDR 10.77.77.20
	342	#define CONFIG_SERVERIP 10.77.77.250
	343
	344	#endif /* __CONFIG_H */