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Commit | Line | Data |
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c609719b WD |
1 | /* |
2 | * (C) Copyright 2001 | |
3 | * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com | |
4 | * | |
3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
c609719b WD |
6 | */ |
7 | ||
8 | /* | |
9 | * board/config.h - configuration options, board specific | |
10 | */ | |
11 | ||
12 | #ifndef __CONFIG_H | |
13 | #define __CONFIG_H | |
14 | ||
15 | /* | |
16 | * High Level Configuration Options | |
17 | * (easy to change) | |
18 | */ | |
19 | ||
20 | #define CONFIG_405GP 1 /* This is a PPC405 CPU */ | |
c837dcb1 WD |
21 | #define CONFIG_4xx 1 /* ...member of PPC4xx family */ |
22 | #define CONFIG_OCRTC 1 /* ...on a OCRTC board */ | |
c609719b | 23 | |
2ae18241 WD |
24 | #define CONFIG_SYS_TEXT_BASE 0xFFFD0000 |
25 | ||
c837dcb1 | 26 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ |
c609719b | 27 | |
c837dcb1 | 28 | #define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ |
c609719b WD |
29 | |
30 | #define CONFIG_BAUDRATE 9600 | |
31 | #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ | |
32 | ||
33 | #undef CONFIG_BOOTARGS | |
34 | #define CONFIG_BOOTCOMMAND "go fff00100" | |
35 | ||
36 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 37 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
c609719b | 38 | |
96e21f86 | 39 | #define CONFIG_PPC4xx_EMAC |
c609719b | 40 | #define CONFIG_MII 1 /* MII PHY management */ |
c837dcb1 | 41 | #define CONFIG_PHY_ADDR 0 /* PHY address */ |
a20b27a3 | 42 | #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ |
c609719b | 43 | |
e18a1061 | 44 | |
659e2f67 JL |
45 | /* |
46 | * BOOTP options | |
47 | */ | |
48 | #define CONFIG_BOOTP_BOOTFILESIZE | |
49 | #define CONFIG_BOOTP_BOOTPATH | |
50 | #define CONFIG_BOOTP_GATEWAY | |
51 | #define CONFIG_BOOTP_HOSTNAME | |
52 | ||
53 | ||
e18a1061 JL |
54 | /* |
55 | * Command line configuration. | |
56 | */ | |
57 | #include <config_cmd_default.h> | |
58 | ||
59 | #define CONFIG_CMD_PCI | |
60 | #define CONFIG_CMD_IRQ | |
61 | #define CONFIG_CMD_ASKENV | |
62 | #define CONFIG_CMD_ELF | |
63 | #define CONFIG_CMD_BSP | |
64 | #define CONFIG_CMD_EEPROM | |
65 | ||
c609719b WD |
66 | |
67 | #define CONFIG_MAC_PARTITION | |
68 | #define CONFIG_DOS_PARTITION | |
69 | ||
c837dcb1 | 70 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
c609719b | 71 | |
c837dcb1 | 72 | #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ |
c609719b WD |
73 | |
74 | /* | |
75 | * Miscellaneous configurable options | |
76 | */ | |
6d0f6bcf JCPV |
77 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
78 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
e18a1061 | 79 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 80 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
c609719b | 81 | #else |
6d0f6bcf | 82 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
c609719b | 83 | #endif |
6d0f6bcf JCPV |
84 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
85 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
86 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
c609719b | 87 | |
6d0f6bcf | 88 | #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ |
c609719b | 89 | |
6d0f6bcf JCPV |
90 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
91 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
c609719b | 92 | |
550650dd SR |
93 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
94 | #define CONFIG_SYS_NS16550 | |
95 | #define CONFIG_SYS_NS16550_SERIAL | |
96 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
97 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() | |
98 | ||
6d0f6bcf | 99 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ |
6d0f6bcf | 100 | #define CONFIG_SYS_BASE_BAUD 691200 |
c609719b WD |
101 | |
102 | /* The following table includes the supported baudrates */ | |
6d0f6bcf | 103 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
8bde7f77 WD |
104 | { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ |
105 | 57600, 115200, 230400, 460800, 921600 } | |
c609719b | 106 | |
6d0f6bcf JCPV |
107 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
108 | #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ | |
c609719b | 109 | |
6d0f6bcf | 110 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
c609719b WD |
111 | |
112 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ | |
113 | ||
114 | /*----------------------------------------------------------------------- | |
115 | * PCI stuff | |
116 | *----------------------------------------------------------------------- | |
117 | */ | |
c837dcb1 WD |
118 | #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ |
119 | #define PCI_HOST_FORCE 1 /* configure as pci host */ | |
120 | #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ | |
c609719b | 121 | |
c837dcb1 | 122 | #define CONFIG_PCI /* include pci support */ |
842033e6 | 123 | #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ |
c837dcb1 WD |
124 | #define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ |
125 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
126 | /* resource configuration */ | |
c609719b | 127 | |
c837dcb1 | 128 | #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ |
c609719b | 129 | |
a20b27a3 | 130 | #define CONFIG_PCI_BOOTDELAY 1 /* enable pci bootdelay variable*/ |
ad10dd9a | 131 | |
6d0f6bcf JCPV |
132 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ |
133 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0410 /* PCI Device ID: OCRTC */ | |
134 | #define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ | |
135 | #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ | |
136 | #define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ | |
137 | #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ | |
138 | #define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */ | |
139 | #define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ | |
140 | #define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ | |
c609719b WD |
141 | |
142 | /*----------------------------------------------------------------------- | |
143 | * Start addresses for the final memory configuration | |
144 | * (Set up by the startup code) | |
6d0f6bcf | 145 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
c609719b | 146 | */ |
6d0f6bcf JCPV |
147 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
148 | #define CONFIG_SYS_FLASH_BASE 0xFFFD0000 | |
149 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
150 | #define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Monitor */ | |
151 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ | |
c609719b WD |
152 | |
153 | /* | |
154 | * For booting Linux, the board info and command line data | |
155 | * have to be in the first 8 MB of memory, since this is | |
156 | * the maximum mapped by the Linux kernel during initialization. | |
157 | */ | |
6d0f6bcf | 158 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
c609719b WD |
159 | /*----------------------------------------------------------------------- |
160 | * FLASH organization | |
161 | */ | |
6d0f6bcf JCPV |
162 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
163 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ | |
c609719b | 164 | |
6d0f6bcf JCPV |
165 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
166 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
c609719b | 167 | |
6d0f6bcf JCPV |
168 | #define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ |
169 | #define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ | |
170 | #define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ | |
c609719b WD |
171 | /* |
172 | * The following defines are added for buggy IOP480 byte interface. | |
173 | * All other boards should use the standard values (CPCI405 etc.) | |
174 | */ | |
6d0f6bcf JCPV |
175 | #define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ |
176 | #define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ | |
177 | #define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ | |
c609719b | 178 | |
6d0f6bcf | 179 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
c609719b WD |
180 | |
181 | #if 0 /* Use NVRAM for environment variables */ | |
182 | /*----------------------------------------------------------------------- | |
183 | * NVRAM organization | |
184 | */ | |
9314cee6 | 185 | #define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ |
6d0f6bcf JCPV |
186 | #define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */ |
187 | #define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */ | |
0e8d1586 JCPV |
188 | #define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */ |
189 | #define CONFIG_ENV_ADDR \ | |
6d0f6bcf JCPV |
190 | (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env */ |
191 | #define CONFIG_SYS_NVRAM_VXWORKS_OFFS 0x6900 /* Offset for VxWorks eth-addr */ | |
c609719b WD |
192 | |
193 | #else /* Use EEPROM for environment variables */ | |
194 | ||
bb1f8b4f | 195 | #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ |
0e8d1586 JCPV |
196 | #define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ |
197 | #define CONFIG_ENV_SIZE 0x300 /* 768 bytes may be used for env vars */ | |
8bde7f77 | 198 | /* total size of a CAT24WC08 is 1024 bytes */ |
c609719b WD |
199 | #endif |
200 | ||
201 | /*----------------------------------------------------------------------- | |
202 | * I2C EEPROM (CAT24WC08) for environment | |
203 | */ | |
880540de DE |
204 | #define CONFIG_SYS_I2C |
205 | #define CONFIG_SYS_I2C_PPC4XX | |
206 | #define CONFIG_SYS_I2C_PPC4XX_CH0 | |
207 | #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 | |
208 | #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F | |
c609719b | 209 | |
6d0f6bcf JCPV |
210 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ |
211 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ | |
c837dcb1 | 212 | /* mask of address bits that overflow into the "EEPROM chip address" */ |
6d0f6bcf JCPV |
213 | #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 |
214 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ | |
c609719b | 215 | /* 16 byte page write mode using*/ |
c837dcb1 | 216 | /* last 4 bits of the address */ |
6d0f6bcf | 217 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
c609719b | 218 | |
c609719b WD |
219 | /* |
220 | * Init Memory Controller: | |
221 | * | |
222 | * BR0/1 and OR0/1 (FLASH) | |
223 | */ | |
224 | ||
225 | #define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */ | |
226 | #define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */ | |
227 | ||
228 | /*----------------------------------------------------------------------- | |
229 | * External Bus Controller (EBC) Setup | |
230 | */ | |
231 | ||
c837dcb1 | 232 | /* Memory Bank 0 (Flash Bank 0) initialization */ |
6d0f6bcf JCPV |
233 | #define CONFIG_SYS_EBC_PB0AP 0x92015480 |
234 | #define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ | |
c609719b | 235 | |
c837dcb1 | 236 | /* Memory Bank 1 (Flash Bank 1) initialization */ |
6d0f6bcf JCPV |
237 | #define CONFIG_SYS_EBC_PB1AP 0x92015480 |
238 | #define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */ | |
c609719b | 239 | |
c837dcb1 | 240 | /* Memory Bank 2 (PLD - FPGA-boot) initialization */ |
6d0f6bcf | 241 | #define CONFIG_SYS_EBC_PB2AP 0x02015480 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ |
8bde7f77 | 242 | /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/ |
6d0f6bcf | 243 | #define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ |
c609719b | 244 | |
c837dcb1 | 245 | /* Memory Bank 3 (PLD - OSL) initialization */ |
6d0f6bcf | 246 | #define CONFIG_SYS_EBC_PB3AP 0x02015480 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ |
8bde7f77 | 247 | /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/ |
6d0f6bcf | 248 | #define CONFIG_SYS_EBC_PB3CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */ |
c609719b | 249 | |
c837dcb1 | 250 | /* Memory Bank 4 (Spartan2 1) initialization */ |
6d0f6bcf | 251 | #define CONFIG_SYS_EBC_PB4AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ |
8bde7f77 | 252 | /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ |
6d0f6bcf | 253 | #define CONFIG_SYS_EBC_PB4CR 0xF209C000 /* BAS=0xF20,BS=16MB,BU=R/W,BW=32bit*/ |
c609719b | 254 | |
c837dcb1 | 255 | /* Memory Bank 5 (Spartan2 2) initialization */ |
6d0f6bcf | 256 | #define CONFIG_SYS_EBC_PB5AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ |
8bde7f77 | 257 | /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ |
6d0f6bcf | 258 | #define CONFIG_SYS_EBC_PB5CR 0xF309C000 /* BAS=0xF30,BS=16MB,BU=R/W,BW=32bit*/ |
c609719b | 259 | |
c837dcb1 | 260 | /* Memory Bank 6 (Virtex 1) initialization */ |
6d0f6bcf | 261 | #define CONFIG_SYS_EBC_PB6AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ |
8bde7f77 | 262 | /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ |
6d0f6bcf | 263 | #define CONFIG_SYS_EBC_PB6CR 0xF409A000 /* BAS=0xF40,BS=16MB,BU=R/W,BW=16bit*/ |
c609719b | 264 | |
c837dcb1 | 265 | /* Memory Bank 7 (Virtex 2) initialization */ |
6d0f6bcf | 266 | #define CONFIG_SYS_EBC_PB7AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ |
8bde7f77 | 267 | /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ |
6d0f6bcf | 268 | #define CONFIG_SYS_EBC_PB7CR 0xF509A000 /* BAS=0xF50,BS=16MB,BU=R/W,BW=16bit*/ |
c609719b WD |
269 | |
270 | ||
6d0f6bcf | 271 | #define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */ |
c609719b WD |
272 | |
273 | /*----------------------------------------------------------------------- | |
274 | * Definitions for initial stack pointer and data area (in DPRAM) | |
275 | */ | |
276 | ||
277 | /* use on chip memory ( OCM ) for temperary stack until sdram is tested */ | |
6d0f6bcf | 278 | #define CONFIG_SYS_TEMP_STACK_OCM 1 |
c609719b WD |
279 | |
280 | /* On Chip Memory location */ | |
6d0f6bcf JCPV |
281 | #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 |
282 | #define CONFIG_SYS_OCM_DATA_SIZE 0x1000 | |
283 | ||
284 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ | |
553f0982 | 285 | #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ |
25ddd1fb | 286 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 287 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
c609719b | 288 | |
c609719b | 289 | #endif /* __CONFIG_H */ |