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c609719b WD |
1 | /* |
2 | * (C) Copyright 2001 | |
3 | * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * board/config.h - configuration options, board specific | |
26 | */ | |
27 | ||
28 | #ifndef __CONFIG_H | |
29 | #define __CONFIG_H | |
30 | ||
31 | /* | |
32 | * High Level Configuration Options | |
33 | * (easy to change) | |
34 | */ | |
35 | ||
36 | #define CONFIG_405GP 1 /* This is a PPC405 CPU */ | |
c837dcb1 WD |
37 | #define CONFIG_4xx 1 /* ...member of PPC4xx family */ |
38 | #define CONFIG_ORSG 1 /* ...on a ORSG board */ | |
c609719b | 39 | |
c837dcb1 | 40 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ |
c609719b | 41 | |
c837dcb1 | 42 | #define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ |
c609719b WD |
43 | |
44 | #define CONFIG_BAUDRATE 9600 | |
45 | #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ | |
46 | ||
47 | #undef CONFIG_BOOTARGS | |
48 | #define CONFIG_BOOTCOMMAND "go fff00100" | |
49 | ||
50 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 51 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
c609719b | 52 | |
96e21f86 | 53 | #define CONFIG_PPC4xx_EMAC |
c609719b | 54 | #define CONFIG_MII 1 /* MII PHY management */ |
c837dcb1 | 55 | #define CONFIG_PHY_ADDR 0 /* PHY address */ |
a20b27a3 | 56 | #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ |
18cc7afd | 57 | #define CONFIG_NET_MULTI |
c609719b | 58 | |
e18a1061 | 59 | |
659e2f67 JL |
60 | /* |
61 | * BOOTP options | |
62 | */ | |
63 | #define CONFIG_BOOTP_BOOTFILESIZE | |
64 | #define CONFIG_BOOTP_BOOTPATH | |
65 | #define CONFIG_BOOTP_GATEWAY | |
66 | #define CONFIG_BOOTP_HOSTNAME | |
67 | ||
68 | ||
e18a1061 JL |
69 | /* |
70 | * Command line configuration. | |
71 | */ | |
72 | #include <config_cmd_default.h> | |
73 | ||
74 | #define CONFIG_CMD_PCI | |
75 | #define CONFIG_CMD_IRQ | |
76 | #define CONFIG_CMD_ASKENV | |
77 | #define CONFIG_CMD_ELF | |
78 | #define CONFIG_CMD_BSP | |
79 | #define CONFIG_CMD_EEPROM | |
80 | ||
c609719b WD |
81 | |
82 | #define CONFIG_MAC_PARTITION | |
83 | #define CONFIG_DOS_PARTITION | |
84 | ||
c837dcb1 | 85 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
c609719b | 86 | |
c837dcb1 | 87 | #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ |
c609719b WD |
88 | |
89 | /* | |
90 | * Miscellaneous configurable options | |
91 | */ | |
6d0f6bcf JCPV |
92 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
93 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
e18a1061 | 94 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 95 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
c609719b | 96 | #else |
6d0f6bcf | 97 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
c609719b | 98 | #endif |
6d0f6bcf JCPV |
99 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
100 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
101 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
c609719b | 102 | |
6d0f6bcf | 103 | #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ |
c609719b | 104 | |
6d0f6bcf JCPV |
105 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
106 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
c609719b | 107 | |
6d0f6bcf | 108 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ |
6d0f6bcf | 109 | #define CONFIG_SYS_BASE_BAUD 691200 |
c609719b WD |
110 | |
111 | /* The following table includes the supported baudrates */ | |
6d0f6bcf | 112 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
8bde7f77 WD |
113 | { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ |
114 | 57600, 115200, 230400, 460800, 921600 } | |
c609719b | 115 | |
6d0f6bcf JCPV |
116 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
117 | #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ | |
c609719b | 118 | |
6d0f6bcf | 119 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
c609719b WD |
120 | |
121 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ | |
122 | ||
123 | /*----------------------------------------------------------------------- | |
124 | * PCI stuff | |
125 | *----------------------------------------------------------------------- | |
126 | */ | |
c837dcb1 WD |
127 | #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ |
128 | #define PCI_HOST_FORCE 1 /* configure as pci host */ | |
129 | #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ | |
130 | ||
131 | #define CONFIG_PCI /* include pci support */ | |
132 | #define CONFIG_PCI_HOST PCI_HOST_ADAPTER /* select pci adapter */ | |
133 | #undef CONFIG_PCI_PNP /* no pci plug-and-play */ | |
134 | /* resource configuration */ | |
135 | ||
136 | #undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ | |
137 | ||
6d0f6bcf JCPV |
138 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ |
139 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0411 /* PCI Device ID: ORSG */ | |
140 | #define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ | |
141 | #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ | |
142 | #define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ | |
143 | #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ | |
144 | #define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */ | |
145 | #define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ | |
146 | #define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ | |
c609719b WD |
147 | |
148 | /*----------------------------------------------------------------------- | |
149 | * Start addresses for the final memory configuration | |
150 | * (Set up by the startup code) | |
6d0f6bcf | 151 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
c609719b | 152 | */ |
6d0f6bcf JCPV |
153 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
154 | #define CONFIG_SYS_FLASH_BASE 0xFFFD0000 | |
155 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
156 | #define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Monitor */ | |
157 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ | |
c609719b WD |
158 | |
159 | /* | |
160 | * For booting Linux, the board info and command line data | |
161 | * have to be in the first 8 MB of memory, since this is | |
162 | * the maximum mapped by the Linux kernel during initialization. | |
163 | */ | |
6d0f6bcf | 164 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
c609719b WD |
165 | /*----------------------------------------------------------------------- |
166 | * FLASH organization | |
167 | */ | |
6d0f6bcf JCPV |
168 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
169 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ | |
c609719b | 170 | |
6d0f6bcf JCPV |
171 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
172 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
c609719b | 173 | |
6d0f6bcf JCPV |
174 | #define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ |
175 | #define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ | |
176 | #define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ | |
c609719b WD |
177 | /* |
178 | * The following defines are added for buggy IOP480 byte interface. | |
179 | * All other boards should use the standard values (CPCI405 etc.) | |
180 | */ | |
6d0f6bcf JCPV |
181 | #define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ |
182 | #define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ | |
183 | #define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ | |
c609719b | 184 | |
6d0f6bcf | 185 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
c609719b WD |
186 | |
187 | #if 0 /* Use NVRAM for environment variables */ | |
188 | /*----------------------------------------------------------------------- | |
189 | * NVRAM organization | |
190 | */ | |
9314cee6 | 191 | #define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ |
6d0f6bcf JCPV |
192 | #define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */ |
193 | #define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */ | |
0e8d1586 JCPV |
194 | #define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */ |
195 | #define CONFIG_ENV_ADDR \ | |
6d0f6bcf JCPV |
196 | (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env */ |
197 | #define CONFIG_SYS_NVRAM_VXWORKS_OFFS 0x6900 /* Offset for VxWorks eth-addr */ | |
c609719b WD |
198 | |
199 | #else /* Use EEPROM for environment variables */ | |
200 | ||
bb1f8b4f | 201 | #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ |
0e8d1586 JCPV |
202 | #define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ |
203 | #define CONFIG_ENV_SIZE 0x300 /* 768 bytes may be used for env vars */ | |
8bde7f77 | 204 | /* total size of a CAT24WC08 is 1024 bytes */ |
c609719b WD |
205 | #endif |
206 | ||
207 | /*----------------------------------------------------------------------- | |
208 | * I2C EEPROM (CAT24WC08) for environment | |
209 | */ | |
210 | #define CONFIG_HARD_I2C /* I2c with hardware support */ | |
d0b0dcaa | 211 | #define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ |
6d0f6bcf JCPV |
212 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
213 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
c609719b | 214 | |
6d0f6bcf JCPV |
215 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ |
216 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ | |
c837dcb1 | 217 | /* mask of address bits that overflow into the "EEPROM chip address" */ |
6d0f6bcf JCPV |
218 | #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 |
219 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ | |
c609719b | 220 | /* 16 byte page write mode using*/ |
c837dcb1 | 221 | /* last 4 bits of the address */ |
6d0f6bcf | 222 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
c609719b | 223 | |
c609719b WD |
224 | /* |
225 | * Init Memory Controller: | |
226 | * | |
227 | * BR0/1 and OR0/1 (FLASH) | |
228 | */ | |
229 | ||
230 | #define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */ | |
231 | #define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */ | |
232 | ||
233 | /*----------------------------------------------------------------------- | |
234 | * External Bus Controller (EBC) Setup | |
235 | */ | |
236 | ||
c837dcb1 | 237 | /* Memory Bank 0 (Flash Bank 0) initialization */ |
6d0f6bcf JCPV |
238 | #define CONFIG_SYS_EBC_PB0AP 0x92015480 |
239 | #define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ | |
c609719b | 240 | |
c837dcb1 | 241 | /* Memory Bank 1 (Flash Bank 1) initialization */ |
6d0f6bcf JCPV |
242 | #define CONFIG_SYS_EBC_PB1AP 0x92015480 |
243 | #define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */ | |
c609719b | 244 | |
c837dcb1 | 245 | /* Memory Bank 2 (PLD - FPGA-boot) initialization */ |
6d0f6bcf | 246 | #define CONFIG_SYS_EBC_PB2AP 0x02015480 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ |
8bde7f77 | 247 | /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/ |
6d0f6bcf | 248 | #define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ |
c609719b | 249 | |
c837dcb1 | 250 | /* Memory Bank 3 (PLD - OSL) initialization */ |
6d0f6bcf | 251 | #define CONFIG_SYS_EBC_PB3AP 0x02015480 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ |
8bde7f77 | 252 | /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/ |
6d0f6bcf | 253 | #define CONFIG_SYS_EBC_PB3CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */ |
c609719b | 254 | |
c837dcb1 | 255 | /* Memory Bank 4 (Spartan2 1) initialization */ |
6d0f6bcf | 256 | #define CONFIG_SYS_EBC_PB4AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ |
8bde7f77 | 257 | /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ |
6d0f6bcf | 258 | #define CONFIG_SYS_EBC_PB4CR 0xF209C000 /* BAS=0xF20,BS=16MB,BU=R/W,BW=32bit*/ |
c609719b | 259 | |
c837dcb1 | 260 | /* Memory Bank 5 (Spartan2 2) initialization */ |
6d0f6bcf | 261 | #define CONFIG_SYS_EBC_PB5AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ |
8bde7f77 | 262 | /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ |
6d0f6bcf | 263 | #define CONFIG_SYS_EBC_PB5CR 0xF309C000 /* BAS=0xF30,BS=16MB,BU=R/W,BW=32bit*/ |
c609719b | 264 | |
c837dcb1 | 265 | /* Memory Bank 6 (Virtex 1) initialization */ |
6d0f6bcf | 266 | #define CONFIG_SYS_EBC_PB6AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ |
8bde7f77 | 267 | /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ |
6d0f6bcf | 268 | #define CONFIG_SYS_EBC_PB6CR 0xF409A000 /* BAS=0xF40,BS=16MB,BU=R/W,BW=16bit*/ |
c609719b | 269 | |
c837dcb1 | 270 | /* Memory Bank 7 (Virtex 2) initialization */ |
6d0f6bcf | 271 | #define CONFIG_SYS_EBC_PB7AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ |
8bde7f77 | 272 | /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ |
6d0f6bcf | 273 | #define CONFIG_SYS_EBC_PB7CR 0xF509A000 /* BAS=0xF50,BS=16MB,BU=R/W,BW=16bit*/ |
c609719b WD |
274 | |
275 | ||
6d0f6bcf | 276 | #define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */ |
c609719b WD |
277 | |
278 | /*----------------------------------------------------------------------- | |
279 | * Definitions for initial stack pointer and data area (in DPRAM) | |
280 | */ | |
281 | ||
282 | /* use on chip memory ( OCM ) for temperary stack until sdram is tested */ | |
6d0f6bcf | 283 | #define CONFIG_SYS_TEMP_STACK_OCM 1 |
c609719b WD |
284 | |
285 | /* On Chip Memory location */ | |
6d0f6bcf JCPV |
286 | #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 |
287 | #define CONFIG_SYS_OCM_DATA_SIZE 0x1000 | |
288 | ||
289 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ | |
290 | #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */ | |
291 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ | |
292 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
293 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
c609719b WD |
294 | |
295 | ||
296 | /* | |
297 | * Internal Definitions | |
298 | * | |
299 | * Boot Flags | |
300 | */ | |
301 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
302 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
303 | ||
304 | #endif /* __CONFIG_H */ |