[people/ms/u-boot.git] / include / configs / ORSG.h

/*
 * (C) Copyright 2001
 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
#define CONFIG_ORSG		1	/* ...on a ORSG board		*/

#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/

#define CONFIG_SYS_CLK_FREQ	33000000 /* external frequency to pll	*/

#define CONFIG_BAUDRATE		9600
#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/

#undef	CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND "go fff00100"

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII		1	/* MII PHY management		*/
#define CONFIG_PHY_ADDR		0	/* PHY address			*/
#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_PCI
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_ELF
#define CONFIG_CMD_BSP
#define CONFIG_CMD_EEPROM


#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/

#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_serial_clock()

#undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* no external serial clock used */
#define CONFIG_SYS_BASE_BAUD	    691200

/* The following table includes the supported baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE	\
	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
	 57600, 115200, 230400, 460800, 921600 }

#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */

#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */

#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
#define PCI_HOST_FORCE	1		/* configure as pci host	*/
#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/

#define CONFIG_PCI			/* include pci support		*/
#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
#define CONFIG_PCI_HOST PCI_HOST_ADAPTER /* select pci adapter		*/
#undef	CONFIG_PCI_PNP			/* no pci plug-and-play		*/
					/* resource configuration	*/

#undef	CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/

#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0411	/* PCI Device ID: ORSG		*/
#define CONFIG_SYS_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
#define CONFIG_SYS_PCI_PTM1LA	0x00000000	/* point to sdram		*/
#define CONFIG_SYS_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
#define CONFIG_SYS_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
#define CONFIG_SYS_PCI_PTM2LA	0xffc00000	/* point to flash		*/
#define CONFIG_SYS_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
#define CONFIG_SYS_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH_BASE		0xFFFD0000
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN		(192 * 1024)	/* Reserve 192 kB for Monitor	*/
#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
/*
 * The following defines are added for buggy IOP480 byte interface.
 * All other boards should use the standard values (CPCI405 etc.)
 */
#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/

#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */

#if 0 /* Use NVRAM for environment variables */
/*-----------------------------------------------------------------------
 * NVRAM organization
 */
#define CONFIG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
#define CONFIG_SYS_NVRAM_BASE_ADDR	0xf0200000		/* NVRAM base address	*/
#define CONFIG_SYS_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
#define CONFIG_ENV_SIZE		0x1000		/* Size of Environment vars	*/
#define CONFIG_ENV_ADDR		\
	(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE)	/* Env	*/
#define CONFIG_SYS_NVRAM_VXWORKS_OFFS	0x6900		/* Offset for VxWorks eth-addr	*/

#else /* Use EEPROM for environment variables */

#define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
#define CONFIG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
#define CONFIG_ENV_SIZE		0x300	/* 768 bytes may be used for env vars */
				   /* total size of a CAT24WC08 is 1024 bytes */
#endif

/*-----------------------------------------------------------------------
 * I2C EEPROM (CAT24WC08) for environment
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_PPC4XX
#define CONFIG_SYS_I2C_PPC4XX_CH0
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F

#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
/* mask of address bits that overflow into the "EEPROM chip address"	*/
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
					/* 16 byte page write mode using*/
					/* last 4 bits of the address	*/
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */

#define FLASH_BASE0_PRELIM	0xFF800000	/* FLASH bank #0	*/
#define FLASH_BASE1_PRELIM	0xFFC00000	/* FLASH bank #1	*/

/*-----------------------------------------------------------------------
 * External Bus Controller (EBC) Setup
 */

/* Memory Bank 0 (Flash Bank 0) initialization					*/
#define CONFIG_SYS_EBC_PB0AP		0x92015480
#define CONFIG_SYS_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */

/* Memory Bank 1 (Flash Bank 1) initialization					*/
#define CONFIG_SYS_EBC_PB1AP		0x92015480
#define CONFIG_SYS_EBC_PB1CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */

/* Memory Bank 2 (PLD - FPGA-boot) initialization				*/
#define CONFIG_SYS_EBC_PB2AP		0x02015480  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/
#define CONFIG_SYS_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/

/* Memory Bank 3 (PLD - OSL) initialization					*/
#define CONFIG_SYS_EBC_PB3AP		0x02015480  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/
#define CONFIG_SYS_EBC_PB3CR		0xF0118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit	*/

/* Memory Bank 4 (Spartan2 1) initialization					*/
#define CONFIG_SYS_EBC_PB4AP		0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
#define CONFIG_SYS_EBC_PB4CR		0xF209C000  /* BAS=0xF20,BS=16MB,BU=R/W,BW=32bit*/

/* Memory Bank 5 (Spartan2 2) initialization					*/
#define CONFIG_SYS_EBC_PB5AP		0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
#define CONFIG_SYS_EBC_PB5CR		0xF309C000  /* BAS=0xF30,BS=16MB,BU=R/W,BW=32bit*/

/* Memory Bank 6 (Virtex 1) initialization					*/
#define CONFIG_SYS_EBC_PB6AP		0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
#define CONFIG_SYS_EBC_PB6CR		0xF409A000  /* BAS=0xF40,BS=16MB,BU=R/W,BW=16bit*/

/* Memory Bank 7 (Virtex 2) initialization					*/
#define CONFIG_SYS_EBC_PB7AP		0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
#define CONFIG_SYS_EBC_PB7CR		0xF509A000  /* BAS=0xF50,BS=16MB,BU=R/W,BW=16bit*/


#define CONFIG_SYS_VXWORKS_MAC_PTR	0x00000000	/* Pass Ethernet MAC to VxWorks */

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */

/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
#define CONFIG_SYS_TEMP_STACK_OCM	  1

/* On Chip Memory location */
#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
#define CONFIG_SYS_OCM_DATA_SIZE	0x1000

#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#endif	/* __CONFIG_H */
Commit	Line	Data
c609719b WD	1	/*
	2	* (C) Copyright 2001
	3	* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* board/config.h - configuration options, board specific
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	/*
	32	* High Level Configuration Options
	33	* (easy to change)
	34	*/
	35
	36	#define CONFIG_405GP 1 /* This is a PPC405 CPU */
c837dcb1 WD	37	#define CONFIG_4xx 1 /* ...member of PPC4xx family */
c837dcb1 WD	38	#define CONFIG_ORSG 1 /* ...on a ORSG board */
c609719b	39
c837dcb1	40	#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
c609719b	41
c837dcb1	42	#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
c609719b WD	43
	44	#define CONFIG_BAUDRATE 9600
	45	#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
	46
	47	#undef CONFIG_BOOTARGS
	48	#define CONFIG_BOOTCOMMAND "go fff00100"
	49
	50	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	51	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
c609719b	52
96e21f86	53	#define CONFIG_PPC4xx_EMAC
c609719b	54	#define CONFIG_MII 1 /* MII PHY management */
c837dcb1	55	#define CONFIG_PHY_ADDR 0 /* PHY address */
a20b27a3	56	#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
c609719b	57
e18a1061	58
659e2f67 JL	59	/*
	60	* BOOTP options
	61	*/
	62	#define CONFIG_BOOTP_BOOTFILESIZE
	63	#define CONFIG_BOOTP_BOOTPATH
	64	#define CONFIG_BOOTP_GATEWAY
	65	#define CONFIG_BOOTP_HOSTNAME
	66
	67
e18a1061 JL	68	/*
	69	* Command line configuration.
	70	*/
	71	#include <config_cmd_default.h>
	72
	73	#define CONFIG_CMD_PCI
	74	#define CONFIG_CMD_IRQ
	75	#define CONFIG_CMD_ASKENV
	76	#define CONFIG_CMD_ELF
	77	#define CONFIG_CMD_BSP
	78	#define CONFIG_CMD_EEPROM
	79
c609719b WD	80
	81	#define CONFIG_MAC_PARTITION
	82	#define CONFIG_DOS_PARTITION
	83
c837dcb1	84	#undef CONFIG_WATCHDOG /* watchdog disabled */
c609719b	85
c837dcb1	86	#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
c609719b WD	87
	88	/*
	89	* Miscellaneous configurable options
	90	*/
6d0f6bcf JCPV	91	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	92	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
e18a1061	93	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	94	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
c609719b	95	#else
6d0f6bcf	96	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
c609719b	97	#endif
6d0f6bcf JCPV	98	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	99	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	100	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
c609719b	101
6d0f6bcf	102	#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
c609719b	103
6d0f6bcf JCPV	104	#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
6d0f6bcf JCPV	105	#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
c609719b	106
550650dd SR	107	#define CONFIG_CONS_INDEX 1 /* Use UART0 */
	108	#define CONFIG_SYS_NS16550
	109	#define CONFIG_SYS_NS16550_SERIAL
	110	#define CONFIG_SYS_NS16550_REG_SIZE 1
	111	#define CONFIG_SYS_NS16550_CLK get_serial_clock()
	112
6d0f6bcf	113	#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
6d0f6bcf	114	#define CONFIG_SYS_BASE_BAUD 691200
c609719b WD	115
c609719b WD	116	/* The following table includes the supported baudrates */
6d0f6bcf	117	#define CONFIG_SYS_BAUDRATE_TABLE \
8bde7f77 WD	118	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
8bde7f77 WD	119	57600, 115200, 230400, 460800, 921600 }
c609719b	120
6d0f6bcf JCPV	121	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
6d0f6bcf JCPV	122	#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
c609719b	123
6d0f6bcf	124	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
c609719b WD	125
	126	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
	127
	128	/*-----------------------------------------------------------------------
	129	* PCI stuff
	130	*-----------------------------------------------------------------------
	131	*/
c837dcb1 WD	132	#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
	133	#define PCI_HOST_FORCE 1 /* configure as pci host */
	134	#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
	135
	136	#define CONFIG_PCI /* include pci support */
842033e6	137	#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
c837dcb1 WD	138	#define CONFIG_PCI_HOST PCI_HOST_ADAPTER /* select pci adapter */
	139	#undef CONFIG_PCI_PNP /* no pci plug-and-play */
	140	/* resource configuration */
	141
	142	#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
	143
6d0f6bcf JCPV	144	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
	145	#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0411 /* PCI Device ID: ORSG */
	146	#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
	147	#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
	148	#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
	149	#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
	150	#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
	151	#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
	152	#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
c609719b WD	153
	154	/*-----------------------------------------------------------------------
	155	* Start addresses for the final memory configuration
	156	* (Set up by the startup code)
6d0f6bcf	157	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
c609719b	158	*/
6d0f6bcf JCPV	159	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	160	#define CONFIG_SYS_FLASH_BASE 0xFFFD0000
	161	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	162	#define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Monitor */
	163	#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
c609719b WD	164
	165	/*
	166	* For booting Linux, the board info and command line data
	167	* have to be in the first 8 MB of memory, since this is
	168	* the maximum mapped by the Linux kernel during initialization.
	169	*/
6d0f6bcf	170	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
c609719b WD	171	/*-----------------------------------------------------------------------
	172	* FLASH organization
	173	*/
6d0f6bcf JCPV	174	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
6d0f6bcf JCPV	175	#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
c609719b	176
6d0f6bcf JCPV	177	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	178	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
c609719b	179
6d0f6bcf JCPV	180	#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
	181	#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
	182	#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
c609719b WD	183	/*
	184	* The following defines are added for buggy IOP480 byte interface.
	185	* All other boards should use the standard values (CPCI405 etc.)
	186	*/
6d0f6bcf JCPV	187	#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
	188	#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
	189	#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
c609719b	190
6d0f6bcf	191	#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
c609719b WD	192
	193	#if 0 /* Use NVRAM for environment variables */
	194	/*-----------------------------------------------------------------------
	195	* NVRAM organization
	196	*/
9314cee6	197	#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
6d0f6bcf JCPV	198	#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */
6d0f6bcf JCPV	199	#define CONFIG_SYS_NVRAM_SIZE (321024) / NVRAM size */
0e8d1586 JCPV	200	#define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */
0e8d1586 JCPV	201	#define CONFIG_ENV_ADDR \
6d0f6bcf JCPV	202	(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env */
6d0f6bcf JCPV	203	#define CONFIG_SYS_NVRAM_VXWORKS_OFFS 0x6900 /* Offset for VxWorks eth-addr */
c609719b WD	204
	205	#else /* Use EEPROM for environment variables */
	206
bb1f8b4f	207	#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
0e8d1586 JCPV	208	#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
0e8d1586 JCPV	209	#define CONFIG_ENV_SIZE 0x300 /* 768 bytes may be used for env vars */
8bde7f77	210	/* total size of a CAT24WC08 is 1024 bytes */
c609719b WD	211	#endif
	212
	213	/*-----------------------------------------------------------------------
	214	* I2C EEPROM (CAT24WC08) for environment
	215	*/
880540de DE	216	#define CONFIG_SYS_I2C
	217	#define CONFIG_SYS_I2C_PPC4XX
	218	#define CONFIG_SYS_I2C_PPC4XX_CH0
	219	#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
	220	#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
c609719b	221
6d0f6bcf JCPV	222	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
6d0f6bcf JCPV	223	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
c837dcb1	224	/* mask of address bits that overflow into the "EEPROM chip address" */
6d0f6bcf JCPV	225	#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
6d0f6bcf JCPV	226	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
c609719b	227	/* 16 byte page write mode using*/
c837dcb1	228	/* last 4 bits of the address */
6d0f6bcf	229	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
c609719b	230
c609719b WD	231	/*
	232	* Init Memory Controller:
	233	*
	234	* BR0/1 and OR0/1 (FLASH)
	235	*/
	236
	237	#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
	238	#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */
	239
	240	/*-----------------------------------------------------------------------
	241	* External Bus Controller (EBC) Setup
	242	*/
	243
c837dcb1	244	/* Memory Bank 0 (Flash Bank 0) initialization */
6d0f6bcf JCPV	245	#define CONFIG_SYS_EBC_PB0AP 0x92015480
6d0f6bcf JCPV	246	#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
c609719b	247
c837dcb1	248	/* Memory Bank 1 (Flash Bank 1) initialization */
6d0f6bcf JCPV	249	#define CONFIG_SYS_EBC_PB1AP 0x92015480
6d0f6bcf JCPV	250	#define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
c609719b	251
c837dcb1	252	/* Memory Bank 2 (PLD - FPGA-boot) initialization */
6d0f6bcf	253	#define CONFIG_SYS_EBC_PB2AP 0x02015480 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
8bde7f77	254	/* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/
6d0f6bcf	255	#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
c609719b	256
c837dcb1	257	/* Memory Bank 3 (PLD - OSL) initialization */
6d0f6bcf	258	#define CONFIG_SYS_EBC_PB3AP 0x02015480 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
8bde7f77	259	/* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/
6d0f6bcf	260	#define CONFIG_SYS_EBC_PB3CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */
c609719b	261
c837dcb1	262	/* Memory Bank 4 (Spartan2 1) initialization */
6d0f6bcf	263	#define CONFIG_SYS_EBC_PB4AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
8bde7f77	264	/* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
6d0f6bcf	265	#define CONFIG_SYS_EBC_PB4CR 0xF209C000 /* BAS=0xF20,BS=16MB,BU=R/W,BW=32bit*/
c609719b	266
c837dcb1	267	/* Memory Bank 5 (Spartan2 2) initialization */
6d0f6bcf	268	#define CONFIG_SYS_EBC_PB5AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
8bde7f77	269	/* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
6d0f6bcf	270	#define CONFIG_SYS_EBC_PB5CR 0xF309C000 /* BAS=0xF30,BS=16MB,BU=R/W,BW=32bit*/
c609719b	271
c837dcb1	272	/* Memory Bank 6 (Virtex 1) initialization */
6d0f6bcf	273	#define CONFIG_SYS_EBC_PB6AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
8bde7f77	274	/* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
6d0f6bcf	275	#define CONFIG_SYS_EBC_PB6CR 0xF409A000 /* BAS=0xF40,BS=16MB,BU=R/W,BW=16bit*/
c609719b	276
c837dcb1	277	/* Memory Bank 7 (Virtex 2) initialization */
6d0f6bcf	278	#define CONFIG_SYS_EBC_PB7AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
8bde7f77	279	/* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
6d0f6bcf	280	#define CONFIG_SYS_EBC_PB7CR 0xF509A000 /* BAS=0xF50,BS=16MB,BU=R/W,BW=16bit*/
c609719b WD	281
c609719b WD	282
6d0f6bcf	283	#define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */
c609719b WD	284
	285	/*-----------------------------------------------------------------------
	286	* Definitions for initial stack pointer and data area (in DPRAM)
	287	*/
	288
	289	/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
6d0f6bcf	290	#define CONFIG_SYS_TEMP_STACK_OCM 1
c609719b WD	291
c609719b WD	292	/* On Chip Memory location */
6d0f6bcf JCPV	293	#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
	294	#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
	295
	296	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
553f0982	297	#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
25ddd1fb	298	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	299	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
c609719b	300
c609719b	301	#endif /* __CONFIG_H */