[people/ms/u-boot.git] / include / configs / OXC.h

/*
 * (C) Copyright 2001
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/* ------------------------------------------------------------------------- */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC824X		1
#define CONFIG_MPC8240		1
#define CONFIG_OXC		1

#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/

#define CONFIG_IDENT_STRING     " [oxc] "

#define CONFIG_WATCHDOG		1
#define CONFIG_SHOW_ACTIVITY	1
#define CONFIG_SHOW_BOOT_PROGRESS 1

#define CONFIG_CONS_INDEX	1
#define CONFIG_BAUDRATE		9600
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ELF


/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP		1		/* undef to save memory		*/
#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt	*/
#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size	*/
#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
#define CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address		*/
#define CONFIG_SYS_HZ			1000		/* decrementer freq: 1 ms ticks */

#define CONFIG_MISC_INIT_R	1		/* call misc_init_r() on init	*/

/*-----------------------------------------------------------------------
 * Boot options
 */

#define CONFIG_SERVERIP		10.0.0.1
#define CONFIG_GATEWAYIP	10.0.0.1
#define CONFIG_NETMASK		255.255.255.0
#define CONFIG_LOADADDR		0x10000
#define CONFIG_BOOTFILE		"/mnt/ide0/p2/usr/tftp/oxc.elf"
#define CONFIG_BOOTCOMMAND	"tftp 0x10000 ; bootelf 0x10000"
#define CONFIG_BOOTDELAY	10

#define CONFIG_SYS_OXC_GENERATE_IP	1		/* Generate IP automatically	*/
#define CONFIG_SYS_OXC_IPMASK		0x0A000000	/* 10.0.0.x			*/

/*-----------------------------------------------------------------------
 * PCI stuff
 */

#define CONFIG_PCI				/* include pci support		*/

#define CONFIG_NET_MULTI			/* Multi ethernet cards support */

#define CONFIG_EEPRO100				/* Ethernet Express PRO 100	*/
#define CONFIG_SYS_RX_ETH_BUFFER	8               /* use 8 rx buffer on eepro100  */

#define PCI_ENET0_IOADDR	0x80000000
#define PCI_ENET0_MEMADDR	0x80000000
#define	PCI_ENET1_IOADDR	0x81000000
#define	PCI_ENET1_MEMADDR	0x81000000

/*-----------------------------------------------------------------------
 * FLASH
 */

#define CONFIG_SYS_FLASH_PRELIMBASE	0xFF800000
#define CONFIG_SYS_FLASH_BASE		(0-flash_info[0].size)

#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	32	/* max number of sectors on one chip	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

/*-----------------------------------------------------------------------
 * RAM
 */

#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_MAX_RAM_SIZE	0x10000000

#define CONFIG_SYS_RESET_ADDRESS	0xFFF00100

#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN		0x00030000

#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_PRELIMBASE)
# define CONFIG_SYS_RAMBOOT		1
#else
# undef CONFIG_SYS_RAMBOOT
#endif

#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
#define CONFIG_SYS_INIT_RAM_END	0x1000

#define CONFIG_SYS_GBL_DATA_SIZE	128
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MALLOC_LEN		(512 << 10)	/* Reserve 512 kB for malloc()	*/

#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest works on		*/
#define CONFIG_SYS_MEMTEST_END		0x04000000	/* 0 ... 32 MB in DRAM		*/

/*-----------------------------------------------------------------------
 * Memory mapping
 */

#define CONFIG_SYS_CPLD_BASE		0xff000000	/* CPLD registers */
#define CONFIG_SYS_CPLD_WATCHDOG	(CONFIG_SYS_CPLD_BASE)			/* Watchdog */
#define CONFIG_SYS_CPLD_RESET		(CONFIG_SYS_CPLD_BASE + 0x040000)	/* Minor resets */
#define CONFIG_SYS_UART_BASE		(CONFIG_SYS_CPLD_BASE + 0x700000)	/* debug UART */

/*-----------------------------------------------------------------------
 * NS16550 Configuration
 */

#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	-4
#define CONFIG_SYS_NS16550_CLK		1843200
#define CONFIG_SYS_NS16550_COM1	CONFIG_SYS_UART_BASE

/*-----------------------------------------------------------------------
 * I2C Bus
 */

#define CONFIG_I2C		1		/* I2C support on ... */
#define CONFIG_HARD_I2C		1		/* ... hardware one */
#define CONFIG_SYS_I2C_SPEED		400000		/* I2C speed and slave address	*/
#define CONFIG_SYS_I2C_SLAVE		0x7F		/* I2C slave address */

#define CONFIG_SYS_I2C_EXPANDER0_ADDR	0x20		/* PCF8574 expander 0 addrerr */
#define CONFIG_SYS_I2C_EXPANDER1_ADDR	0x21		/* PCF8574 expander 1 addrerr */
#define CONFIG_SYS_I2C_EXPANDER2_ADDR	0x26		/* PCF8574 expander 2 addrerr */

/*-----------------------------------------------------------------------
 * Environment
 */

#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_ADDR		0xFFF30000	/* Offset of Environment Sector	*/
#define CONFIG_ENV_SIZE		0x00010000	/* Total Size of Environment Sector */
#define	CONFIG_ENV_IS_EMBEDDED	1		/* short-cut compile-time test	*/
#define CONFIG_ENV_OVERWRITE    1		/* Allow modifying the environment */

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */

#define CONFIG_SYS_CLK_FREQ  33000000	/* external frequency to pll */
#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER  2

#define CONFIG_SYS_EUMB_ADDR		0xFC000000

/* MCCR1 */
#define CONFIG_SYS_ROMNAL		0	/* rom/flash next access time		*/
#define CONFIG_SYS_ROMFAL		19	/* rom/flash access time		*/

/* MCCR2 */
#define CONFIG_SYS_ASRISE		15	/* ASRISE=15 clocks			*/
#define CONFIG_SYS_ASFALL		3	/* ASFALL=3 clocks			*/
#define CONFIG_SYS_REFINT		1000	/* REFINT=1000 clocks			*/

/* MCCR3 */
#define CONFIG_SYS_BSTOPRE		0x35c	/* Burst To Precharge			*/
#define CONFIG_SYS_REFREC		7	/* Refresh to activate interval		*/
#define CONFIG_SYS_RDLAT		4	/* data latency from read command	*/

/* MCCR4 */
#define CONFIG_SYS_PRETOACT		2	/* Precharge to activate interval	*/
#define CONFIG_SYS_ACTTOPRE		5	/* Activate to Precharge interval	*/
#define CONFIG_SYS_ACTORW		2	/* Activate to R/W			*/
#define CONFIG_SYS_SDMODE_CAS_LAT	3	/* SDMODE CAS latency			*/
#define CONFIG_SYS_SDMODE_WRAP		0	/* SDMODE wrap type			*/
#define CONFIG_SYS_SDMODE_BURSTLEN	3	/* SDMODE Burst length 2=4, 3=8		*/
#define CONFIG_SYS_REGISTERD_TYPE_BUFFER   1

/* memory bank settings*/
/*
 * only bits 20-29 are actually used from these vales to set the
 * start/end address the upper two bits will be 0, and the lower 20
 * bits will be set to 0x00000 for a start address, or 0xfffff for an
 * end address
 */
#define CONFIG_SYS_BANK0_START		0x00000000
#define CONFIG_SYS_BANK0_END		(CONFIG_SYS_MAX_RAM_SIZE - 1)
#define CONFIG_SYS_BANK0_ENABLE	1
#define CONFIG_SYS_BANK1_START		0x00000000
#define CONFIG_SYS_BANK1_END		0x00000000
#define CONFIG_SYS_BANK1_ENABLE	0
#define CONFIG_SYS_BANK2_START		0x00000000
#define CONFIG_SYS_BANK2_END		0x00000000
#define CONFIG_SYS_BANK2_ENABLE	0
#define CONFIG_SYS_BANK3_START		0x00000000
#define CONFIG_SYS_BANK3_END		0x00000000
#define CONFIG_SYS_BANK3_ENABLE	0
#define CONFIG_SYS_BANK4_START		0x00000000
#define CONFIG_SYS_BANK4_END		0x00000000
#define CONFIG_SYS_BANK4_ENABLE	0
#define CONFIG_SYS_BANK5_START		0x00000000
#define CONFIG_SYS_BANK5_END		0x00000000
#define CONFIG_SYS_BANK5_ENABLE	0
#define CONFIG_SYS_BANK6_START		0x00000000
#define CONFIG_SYS_BANK6_END		0x00000000
#define CONFIG_SYS_BANK6_ENABLE	0
#define CONFIG_SYS_BANK7_START		0x00000000
#define CONFIG_SYS_BANK7_END		0x00000000
#define CONFIG_SYS_BANK7_ENABLE	0
/*
 * Memory bank enable bitmask, specifying which of the banks defined above
 are actually present. MSB is for bank #7, LSB is for bank #0.
 */
#define CONFIG_SYS_BANK_ENABLE		0x01

#define CONFIG_SYS_ODCR		0xff	/* configures line driver impedances,	*/
					/* see 8240 book for bit definitions	*/
#define CONFIG_SYS_PGMAX		0x32	/* how long the 8240 retains the	*/
					/* currently accessed page in memory	*/
					/* see 8240 book for details		*/

/* SDRAM 0 - 256MB */
#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)

/* stack in DCACHE @ 1GB (no backing mem) */
#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)

/* PCI memory */
#define CONFIG_SYS_IBAT2L	(0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT2U	(0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)

/* Flash, config addrs, etc */
#define CONFIG_SYS_IBAT3L	(0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT3U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)

#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8240 CPU			*/
#if defined(CONFIG_CMD_KGDB)
#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM		0x02	/* Software reboot			*/

#endif	/* __CONFIG_H */
Commit	Line	Data
c609719b WD	1	/*
	2	* (C) Copyright 2001
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/* ------------------------------------------------------------------------- */
	25
	26	/*
	27	* board/config.h - configuration options, board specific
	28	*/
	29
	30	#ifndef __CONFIG_H
	31	#define __CONFIG_H
	32
	33	/*
	34	* High Level Configuration Options
	35	* (easy to change)
	36	*/
	37
	38	#define CONFIG_MPC824X 1
	39	#define CONFIG_MPC8240 1
	40	#define CONFIG_OXC 1
	41
c837dcb1	42	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
c609719b WD	43
	44	#define CONFIG_IDENT_STRING " [oxc] "
	45
	46	#define CONFIG_WATCHDOG 1
	47	#define CONFIG_SHOW_ACTIVITY 1
	48	#define CONFIG_SHOW_BOOT_PROGRESS 1
	49
	50	#define CONFIG_CONS_INDEX 1
	51	#define CONFIG_BAUDRATE 9600
6d0f6bcf	52	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
c609719b	53
c609719b	54
659e2f67 JL	55	/*
	56	* BOOTP options
	57	*/
	58	#define CONFIG_BOOTP_BOOTFILESIZE
	59	#define CONFIG_BOOTP_BOOTPATH
	60	#define CONFIG_BOOTP_GATEWAY
	61	#define CONFIG_BOOTP_HOSTNAME
	62
	63
e18a1061 JL	64	/*
	65	* Command line configuration.
	66	*/
	67	#include <config_cmd_default.h>
	68
	69	#define CONFIG_CMD_ELF
	70
c609719b WD	71
	72	/*
	73	* Miscellaneous configurable options
	74	*/
6d0f6bcf JCPV	75	#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */
	76	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
	77	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	78	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	79	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	80	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
	81	#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
	82	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
c609719b WD	83
	84	#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() on init */
	85
	86	/*-----------------------------------------------------------------------
	87	* Boot options
	88	*/
	89
	90	#define CONFIG_SERVERIP 10.0.0.1
	91	#define CONFIG_GATEWAYIP 10.0.0.1
	92	#define CONFIG_NETMASK 255.255.255.0
	93	#define CONFIG_LOADADDR 0x10000
	94	#define CONFIG_BOOTFILE "/mnt/ide0/p2/usr/tftp/oxc.elf"
	95	#define CONFIG_BOOTCOMMAND "tftp 0x10000 ; bootelf 0x10000"
	96	#define CONFIG_BOOTDELAY 10
	97
6d0f6bcf JCPV	98	#define CONFIG_SYS_OXC_GENERATE_IP 1 /* Generate IP automatically */
6d0f6bcf JCPV	99	#define CONFIG_SYS_OXC_IPMASK 0x0A000000 /* 10.0.0.x */
c609719b WD	100
	101	/*-----------------------------------------------------------------------
	102	* PCI stuff
	103	*/
	104
	105	#define CONFIG_PCI /* include pci support */
	106
	107	#define CONFIG_NET_MULTI /* Multi ethernet cards support */
	108
	109	#define CONFIG_EEPRO100 /* Ethernet Express PRO 100 */
6d0f6bcf	110	#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
c609719b WD	111
	112	#define PCI_ENET0_IOADDR 0x80000000
	113	#define PCI_ENET0_MEMADDR 0x80000000
	114	#define PCI_ENET1_IOADDR 0x81000000
	115	#define PCI_ENET1_MEMADDR 0x81000000
	116
	117	/*-----------------------------------------------------------------------
	118	* FLASH
	119	*/
	120
6d0f6bcf JCPV	121	#define CONFIG_SYS_FLASH_PRELIMBASE 0xFF800000
6d0f6bcf JCPV	122	#define CONFIG_SYS_FLASH_BASE (0-flash_info[0].size)
c609719b	123
6d0f6bcf JCPV	124	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
6d0f6bcf JCPV	125	#define CONFIG_SYS_MAX_FLASH_SECT 32 /* max number of sectors on one chip */
c609719b	126
6d0f6bcf JCPV	127	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	128	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
c609719b WD	129
	130	/*-----------------------------------------------------------------------
	131	* RAM
	132	*/
	133
6d0f6bcf JCPV	134	#define CONFIG_SYS_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	135	#define CONFIG_SYS_MAX_RAM_SIZE 0x10000000
c609719b	136
6d0f6bcf	137	#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
c609719b	138
6d0f6bcf JCPV	139	#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
6d0f6bcf JCPV	140	#define CONFIG_SYS_MONITOR_LEN 0x00030000
c609719b	141
6d0f6bcf JCPV	142	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_PRELIMBASE)
6d0f6bcf JCPV	143	# define CONFIG_SYS_RAMBOOT 1
c609719b	144	#else
6d0f6bcf	145	# undef CONFIG_SYS_RAMBOOT
c609719b WD	146	#endif
c609719b WD	147
6d0f6bcf JCPV	148	#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
6d0f6bcf JCPV	149	#define CONFIG_SYS_INIT_RAM_END 0x1000
c609719b	150
6d0f6bcf JCPV	151	#define CONFIG_SYS_GBL_DATA_SIZE 128
	152	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
	153	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
c609719b	154
6d0f6bcf	155	#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
c609719b	156
6d0f6bcf JCPV	157	#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
6d0f6bcf JCPV	158	#define CONFIG_SYS_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */
c609719b WD	159
	160	/*-----------------------------------------------------------------------
	161	* Memory mapping
	162	*/
	163
6d0f6bcf JCPV	164	#define CONFIG_SYS_CPLD_BASE 0xff000000 /* CPLD registers */
	165	#define CONFIG_SYS_CPLD_WATCHDOG (CONFIG_SYS_CPLD_BASE) /* Watchdog */
	166	#define CONFIG_SYS_CPLD_RESET (CONFIG_SYS_CPLD_BASE + 0x040000) /* Minor resets */
	167	#define CONFIG_SYS_UART_BASE (CONFIG_SYS_CPLD_BASE + 0x700000) /* debug UART */
c609719b WD	168
	169	/*-----------------------------------------------------------------------
	170	* NS16550 Configuration
	171	*/
	172
6d0f6bcf JCPV	173	#define CONFIG_SYS_NS16550
	174	#define CONFIG_SYS_NS16550_SERIAL
	175	#define CONFIG_SYS_NS16550_REG_SIZE -4
	176	#define CONFIG_SYS_NS16550_CLK 1843200
	177	#define CONFIG_SYS_NS16550_COM1 CONFIG_SYS_UART_BASE
c609719b WD	178
	179	/*-----------------------------------------------------------------------
	180	* I2C Bus
	181	*/
	182
	183	#define CONFIG_I2C 1 /* I2C support on ... */
	184	#define CONFIG_HARD_I2C 1 /* ... hardware one */
6d0f6bcf JCPV	185	#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
6d0f6bcf JCPV	186	#define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */
c609719b	187
6d0f6bcf JCPV	188	#define CONFIG_SYS_I2C_EXPANDER0_ADDR 0x20 /* PCF8574 expander 0 addrerr */
	189	#define CONFIG_SYS_I2C_EXPANDER1_ADDR 0x21 /* PCF8574 expander 1 addrerr */
	190	#define CONFIG_SYS_I2C_EXPANDER2_ADDR 0x26 /* PCF8574 expander 2 addrerr */
c609719b WD	191
	192	/*-----------------------------------------------------------------------
	193	* Environment
	194	*/
	195
5a1aceb0	196	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	197	#define CONFIG_ENV_ADDR 0xFFF30000 /* Offset of Environment Sector */
	198	#define CONFIG_ENV_SIZE 0x00010000 /* Total Size of Environment Sector */
	199	#define CONFIG_ENV_IS_EMBEDDED 1 /* short-cut compile-time test */
c609719b WD	200	#define CONFIG_ENV_OVERWRITE 1 /* Allow modifying the environment */
	201
	202	/*
	203	* Low Level Configuration Settings
	204	* (address mappings, register initial values, etc.)
	205	* You should know what you are doing if you make changes here.
	206	*/
	207
	208	#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
	209	#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 2
	210
6d0f6bcf	211	#define CONFIG_SYS_EUMB_ADDR 0xFC000000
c609719b WD	212
c609719b WD	213	/* MCCR1 */
6d0f6bcf JCPV	214	#define CONFIG_SYS_ROMNAL 0 /* rom/flash next access time */
6d0f6bcf JCPV	215	#define CONFIG_SYS_ROMFAL 19 /* rom/flash access time */
c609719b WD	216
c609719b WD	217	/* MCCR2 */
6d0f6bcf JCPV	218	#define CONFIG_SYS_ASRISE 15 /* ASRISE=15 clocks */
	219	#define CONFIG_SYS_ASFALL 3 /* ASFALL=3 clocks */
	220	#define CONFIG_SYS_REFINT 1000 /* REFINT=1000 clocks */
c609719b WD	221
c609719b WD	222	/* MCCR3 */
6d0f6bcf JCPV	223	#define CONFIG_SYS_BSTOPRE 0x35c /* Burst To Precharge */
	224	#define CONFIG_SYS_REFREC 7 /* Refresh to activate interval */
	225	#define CONFIG_SYS_RDLAT 4 /* data latency from read command */
c609719b WD	226
c609719b WD	227	/* MCCR4 */
6d0f6bcf JCPV	228	#define CONFIG_SYS_PRETOACT 2 /* Precharge to activate interval */
	229	#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */
	230	#define CONFIG_SYS_ACTORW 2 /* Activate to R/W */
	231	#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */
	232	#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
	233	#define CONFIG_SYS_SDMODE_BURSTLEN 3 /* SDMODE Burst length 2=4, 3=8 */
	234	#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
c609719b WD	235
	236	/* memory bank settings*/
	237	/*
	238	* only bits 20-29 are actually used from these vales to set the
	239	* start/end address the upper two bits will be 0, and the lower 20
	240	* bits will be set to 0x00000 for a start address, or 0xfffff for an
	241	* end address
	242	*/
6d0f6bcf JCPV	243	#define CONFIG_SYS_BANK0_START 0x00000000
	244	#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
	245	#define CONFIG_SYS_BANK0_ENABLE 1
	246	#define CONFIG_SYS_BANK1_START 0x00000000
	247	#define CONFIG_SYS_BANK1_END 0x00000000
	248	#define CONFIG_SYS_BANK1_ENABLE 0
	249	#define CONFIG_SYS_BANK2_START 0x00000000
	250	#define CONFIG_SYS_BANK2_END 0x00000000
	251	#define CONFIG_SYS_BANK2_ENABLE 0
	252	#define CONFIG_SYS_BANK3_START 0x00000000
	253	#define CONFIG_SYS_BANK3_END 0x00000000
	254	#define CONFIG_SYS_BANK3_ENABLE 0
	255	#define CONFIG_SYS_BANK4_START 0x00000000
	256	#define CONFIG_SYS_BANK4_END 0x00000000
	257	#define CONFIG_SYS_BANK4_ENABLE 0
	258	#define CONFIG_SYS_BANK5_START 0x00000000
	259	#define CONFIG_SYS_BANK5_END 0x00000000
	260	#define CONFIG_SYS_BANK5_ENABLE 0
	261	#define CONFIG_SYS_BANK6_START 0x00000000
	262	#define CONFIG_SYS_BANK6_END 0x00000000
	263	#define CONFIG_SYS_BANK6_ENABLE 0
	264	#define CONFIG_SYS_BANK7_START 0x00000000
	265	#define CONFIG_SYS_BANK7_END 0x00000000
	266	#define CONFIG_SYS_BANK7_ENABLE 0
c609719b WD	267	/*
	268	* Memory bank enable bitmask, specifying which of the banks defined above
	269	are actually present. MSB is for bank #7, LSB is for bank #0.
	270	*/
6d0f6bcf	271	#define CONFIG_SYS_BANK_ENABLE 0x01
c609719b	272
6d0f6bcf	273	#define CONFIG_SYS_ODCR 0xff /* configures line driver impedances, */
c609719b	274	/* see 8240 book for bit definitions */
6d0f6bcf	275	#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */
c609719b WD	276	/* currently accessed page in memory */
	277	/* see 8240 book for details */
	278
	279	/* SDRAM 0 - 256MB */
6d0f6bcf JCPV	280	#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \| BATL_PP_10 \| BATL_MEMCOHERENCE)
6d0f6bcf JCPV	281	#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \| BATU_BL_256M \| BATU_VS \| BATU_VP)
c609719b WD	282
c609719b WD	283	/* stack in DCACHE @ 1GB (no backing mem) */
6d0f6bcf JCPV	284	#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR \| BATL_PP_10 \| BATL_MEMCOHERENCE)
6d0f6bcf JCPV	285	#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR \| BATU_BL_128K \| BATU_VS \| BATU_VP)
c609719b WD	286
c609719b WD	287	/* PCI memory */
6d0f6bcf JCPV	288	#define CONFIG_SYS_IBAT2L (0x80000000 \| BATL_PP_10 \| BATL_CACHEINHIBIT)
6d0f6bcf JCPV	289	#define CONFIG_SYS_IBAT2U (0x80000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP)
c609719b WD	290
c609719b WD	291	/* Flash, config addrs, etc */
6d0f6bcf JCPV	292	#define CONFIG_SYS_IBAT3L (0xF0000000 \| BATL_PP_10 \| BATL_CACHEINHIBIT)
	293	#define CONFIG_SYS_IBAT3U (0xF0000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	294
	295	#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
	296	#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
	297	#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
	298	#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
	299	#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
	300	#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
	301	#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
	302	#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
c609719b WD	303
	304	/*
	305	* For booting Linux, the board info and command line data
	306	* have to be in the first 8 MB of memory, since this is
	307	* the maximum mapped by the Linux kernel during initialization.
	308	*/
6d0f6bcf	309	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
c609719b WD	310
	311	/*-----------------------------------------------------------------------
	312	* Cache Configuration
	313	*/
6d0f6bcf	314	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8240 CPU */
e18a1061	315	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	316	# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
c609719b WD	317	#endif
	318
	319	/*
	320	* Internal Definitions
	321	*
	322	* Boot Flags
	323	*/
	324	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	325	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	326
	327	#endif /* __CONFIG_H */