projects / thirdparty / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 49249e13 PA |
2 | /* |
| 3 | * Copyright 2010-2011 Freescale Semiconductor, Inc. | |
| 2703e640 | 4 | * Copyright 2020 NXP |
| 49249e13 PA |
5 | */ |
| 6 | ||
| 7 | /* | |
| 8 | * P010 RDB board configuration file | |
| 9 | */ | |
| 10 | ||
| 11 | #ifndef __CONFIG_H | |
| 12 | #define __CONFIG_H | |
| 13 | ||
| 1af3c7f4 SG |
14 | #include <linux/stringify.h> |
| 15 | ||
| 74fa22ed | 16 | #include <asm/config_mpc85xx.h> |
| d793e5a8 | 17 | #define CONFIG_NAND_FSL_IFC |
| 49249e13 PA |
18 | |
| 19 | #ifdef CONFIG_SDCARD | |
| c9e1f588 YZ |
20 | #define CONFIG_SPL_FLUSH_IMAGE |
| 21 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" | |
| c9e1f588 YZ |
22 | #define CONFIG_SPL_PAD_TO 0x18000 |
| 23 | #define CONFIG_SPL_MAX_SIZE (96 * 1024) | |
| 24 | #define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10) | |
| 25 | #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) | |
| 26 | #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) | |
| 27 | #define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10) | |
| 28 | #define CONFIG_SYS_MPC85XX_NO_RESETVEC | |
| c9e1f588 YZ |
29 | #ifdef CONFIG_SPL_BUILD |
| 30 | #define CONFIG_SPL_COMMON_INIT_DDR | |
| 31 | #endif | |
| 49249e13 PA |
32 | #endif |
| 33 | ||
| 34 | #ifdef CONFIG_SPIFLASH | |
| bef18454 | 35 | #ifdef CONFIG_NXP_ESBC |
| 49249e13 | 36 | #define CONFIG_RAMBOOT_SPIFLASH |
| 84e0fb40 | 37 | #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc |
| c9e1f588 | 38 | #else |
| c9e1f588 YZ |
39 | #define CONFIG_SPL_SPI_FLASH_MINIMAL |
| 40 | #define CONFIG_SPL_FLUSH_IMAGE | |
| 41 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" | |
| c9e1f588 YZ |
42 | #define CONFIG_SPL_PAD_TO 0x18000 |
| 43 | #define CONFIG_SPL_MAX_SIZE (96 * 1024) | |
| 44 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10) | |
| 45 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) | |
| 46 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) | |
| 47 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10) | |
| 48 | #define CONFIG_SYS_MPC85XX_NO_RESETVEC | |
| c9e1f588 YZ |
49 | #ifdef CONFIG_SPL_BUILD |
| 50 | #define CONFIG_SPL_COMMON_INIT_DDR | |
| 51 | #endif | |
| 52 | #endif | |
| 49249e13 PA |
53 | #endif |
| 54 | ||
| 88718be3 | 55 | #ifdef CONFIG_MTD_RAW_NAND |
| bef18454 | 56 | #ifdef CONFIG_NXP_ESBC |
| 0fa934d2 | 57 | #define CONFIG_SPL_INIT_MINIMAL |
| 0fa934d2 PK |
58 | #define CONFIG_SPL_FLUSH_IMAGE |
| 59 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" | |
| 60 | ||
| 0fa934d2 PK |
61 | #define CONFIG_SPL_MAX_SIZE 8192 |
| 62 | #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 | |
| 63 | #define CONFIG_SPL_RELOC_STACK 0x00100000 | |
| e222b1f3 | 64 | #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) |
| 0fa934d2 PK |
65 | #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) |
| 66 | #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 | |
| 67 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 | |
| c9e1f588 | 68 | #else |
| c9e1f588 | 69 | #ifdef CONFIG_TPL_BUILD |
| c9e1f588 | 70 | #define CONFIG_SPL_FLUSH_IMAGE |
| c9e1f588 | 71 | #define CONFIG_SPL_NAND_INIT |
| c9e1f588 YZ |
72 | #define CONFIG_SPL_COMMON_INIT_DDR |
| 73 | #define CONFIG_SPL_MAX_SIZE (128 << 10) | |
| a6d6812a | 74 | #define CONFIG_TPL_TEXT_BASE 0xD0001000 |
| c9e1f588 YZ |
75 | #define CONFIG_SYS_MPC85XX_NO_RESETVEC |
| 76 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10) | |
| 77 | #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) | |
| 78 | #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) | |
| 79 | #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) | |
| 80 | #elif defined(CONFIG_SPL_BUILD) | |
| 81 | #define CONFIG_SPL_INIT_MINIMAL | |
| c9e1f588 YZ |
82 | #define CONFIG_SPL_NAND_MINIMAL |
| 83 | #define CONFIG_SPL_FLUSH_IMAGE | |
| c9e1f588 YZ |
84 | #define CONFIG_SPL_MAX_SIZE 8192 |
| 85 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) | |
| 86 | #define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000 | |
| 87 | #define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000 | |
| 88 | #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) | |
| 89 | #endif | |
| 90 | #define CONFIG_SPL_PAD_TO 0x20000 | |
| 91 | #define CONFIG_TPL_PAD_TO 0x20000 | |
| 92 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" | |
| c9e1f588 | 93 | #endif |
| d793e5a8 | 94 | #endif |
| 2f439e80 RG |
95 | |
| 96 | #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */ | |
| 97 | #define CONFIG_RAMBOOT_NAND | |
| e222b1f3 | 98 | #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc |
| 2f439e80 RG |
99 | #endif |
| 100 | ||
| 49249e13 PA |
101 | #ifndef CONFIG_RESET_VECTOR_ADDRESS |
| 102 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc | |
| 103 | #endif | |
| 104 | ||
| a6d6812a TR |
105 | #ifdef CONFIG_TPL_BUILD |
| 106 | #define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE | |
| 107 | #elif defined(CONFIG_SPL_BUILD) | |
| 0fa934d2 PK |
108 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE |
| 109 | #else | |
| 110 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ | |
| 49249e13 PA |
111 | #endif |
| 112 | ||
| 113 | /* High Level Configuration Options */ | |
| 49249e13 PA |
114 | #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ |
| 115 | ||
| 49249e13 | 116 | #if defined(CONFIG_PCI) |
| b38eaec5 RD |
117 | #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ |
| 118 | #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ | |
| 49249e13 PA |
119 | #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ |
| 120 | ||
| 49249e13 PA |
121 | /* |
| 122 | * PCI Windows | |
| 123 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
| 124 | */ | |
| 125 | /* controller 1, Slot 1, tgtid 1, Base address a000 */ | |
| 49249e13 PA |
126 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 |
| 127 | #ifdef CONFIG_PHYS_64BIT | |
| 49249e13 PA |
128 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull |
| 129 | #else | |
| 49249e13 PA |
130 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 |
| 131 | #endif | |
| 49249e13 | 132 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 |
| 49249e13 PA |
133 | #ifdef CONFIG_PHYS_64BIT |
| 134 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull | |
| 135 | #else | |
| 136 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 | |
| 137 | #endif | |
| 138 | ||
| 139 | /* controller 2, Slot 2, tgtid 2, Base address 9000 */ | |
| 9de7c76b HZ |
140 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 |
| 141 | #ifdef CONFIG_PHYS_64BIT | |
| 142 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull | |
| 143 | #else | |
| 144 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 | |
| 145 | #endif | |
| 146 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 | |
| 147 | #ifdef CONFIG_PHYS_64BIT | |
| 148 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull | |
| 149 | #else | |
| 150 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 | |
| 151 | #endif | |
| 152 | ||
| 153 | #if !defined(CONFIG_DM_PCI) | |
| 154 | #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ | |
| 155 | #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ | |
| 156 | #define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot" | |
| 157 | #ifdef CONFIG_PHYS_64BIT | |
| 158 | #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 | |
| 159 | #else | |
| 160 | #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 | |
| 161 | #endif | |
| 162 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ | |
| 163 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
| 164 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ | |
| 165 | ||
| 7601686c | 166 | #if defined(CONFIG_TARGET_P1010RDB_PA) |
| 49249e13 | 167 | #define CONFIG_SYS_PCIE2_NAME "PCIe Slot" |
| 7601686c | 168 | #elif defined(CONFIG_TARGET_P1010RDB_PB) |
| e512c50b SL |
169 | #define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot" |
| 170 | #endif | |
| 49249e13 PA |
171 | #ifdef CONFIG_PHYS_64BIT |
| 172 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 | |
| 49249e13 PA |
173 | #else |
| 174 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 | |
| 49249e13 PA |
175 | #endif |
| 176 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ | |
| 49249e13 PA |
177 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 |
| 178 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ | |
| 49249e13 PA |
179 | #endif |
| 180 | ||
| 49249e13 | 181 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
| 49249e13 PA |
182 | #endif |
| 183 | ||
| 49249e13 PA |
184 | #define CONFIG_ENV_OVERWRITE |
| 185 | ||
| 186 | #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */ | |
| 187 | #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */ | |
| 188 | ||
| 49249e13 PA |
189 | #define CONFIG_HWCONFIG |
| 190 | /* | |
| 191 | * These can be toggled for performance analysis, otherwise use default. | |
| 192 | */ | |
| 193 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
| 194 | #define CONFIG_BTB /* toggle branch predition */ | |
| 195 | ||
| 49249e13 PA |
196 | |
| 197 | #define CONFIG_ENABLE_36BIT_PHYS | |
| 198 | ||
| 199 | #ifdef CONFIG_PHYS_64BIT | |
| 200 | #define CONFIG_ADDR_MAP 1 | |
| 201 | #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ | |
| 202 | #endif | |
| 203 | ||
| 49249e13 | 204 | /* DDR Setup */ |
| 1ba62f10 | 205 | #define CONFIG_SYS_DDR_RAW_TIMING |
| 49249e13 PA |
206 | #define CONFIG_DDR_SPD |
| 207 | #define CONFIG_SYS_SPD_BUS_NUM 1 | |
| 208 | #define SPD_EEPROM_ADDRESS 0x52 | |
| 209 | ||
| 210 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
| 211 | ||
| 212 | #ifndef __ASSEMBLY__ | |
| 213 | extern unsigned long get_sdram_size(void); | |
| 214 | #endif | |
| 215 | #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ | |
| 216 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
| 217 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
| 218 | ||
| 219 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
| 220 | #define CONFIG_CHIP_SELECTS_PER_CTRL 1 | |
| 221 | ||
| 222 | /* DDR3 Controller Settings */ | |
| 223 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f | |
| 224 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 | |
| 225 | #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 | |
| 226 | #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef | |
| 227 | #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 | |
| 228 | #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 | |
| 229 | #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 | |
| 49249e13 PA |
230 | #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 |
| 231 | #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 | |
| 232 | #define CONFIG_SYS_DDR_RCW_1 0x00000000 | |
| 233 | #define CONFIG_SYS_DDR_RCW_2 0x00000000 | |
| e512c50b SL |
234 | #define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */ |
| 235 | #define CONFIG_SYS_DDR_CONTROL_2 0x24401000 | |
| 49249e13 PA |
236 | #define CONFIG_SYS_DDR_TIMING_4 0x00000001 |
| 237 | #define CONFIG_SYS_DDR_TIMING_5 0x03402400 | |
| 238 | ||
| e512c50b SL |
239 | #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 |
| 240 | #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104 | |
| 241 | #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644 | |
| 49249e13 PA |
242 | #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF |
| 243 | #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 | |
| e512c50b SL |
244 | #define CONFIG_SYS_DDR_MODE_1_800 0x00441420 |
| 245 | #define CONFIG_SYS_DDR_MODE_2_800 0x00000000 | |
| 49249e13 | 246 | #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100 |
| e512c50b | 247 | #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608 |
| 49249e13 PA |
248 | |
| 249 | /* settings for DDR3 at 667MT/s */ | |
| 250 | #define CONFIG_SYS_DDR_TIMING_3_667 0x00010000 | |
| 251 | #define CONFIG_SYS_DDR_TIMING_0_667 0x00110004 | |
| 252 | #define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544 | |
| 253 | #define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD | |
| 254 | #define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000 | |
| 255 | #define CONFIG_SYS_DDR_MODE_1_667 0x00441210 | |
| 256 | #define CONFIG_SYS_DDR_MODE_2_667 0x00000000 | |
| 257 | #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000 | |
| 258 | #define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608 | |
| 259 | ||
| 260 | #define CONFIG_SYS_CCSRBAR 0xffe00000 | |
| 261 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
| 262 | ||
| d793e5a8 | 263 | /* Don't relocate CCSRBAR while in NAND_SPL */ |
| 0fa934d2 | 264 | #ifdef CONFIG_SPL_BUILD |
| d793e5a8 DD |
265 | #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE |
| 266 | #endif | |
| 267 | ||
| 49249e13 PA |
268 | /* |
| 269 | * Memory map | |
| 270 | * | |
| 271 | * 0x0000_0000 0x3fff_ffff DDR 1G cacheable | |
| 272 | * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable | |
| 273 | * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable | |
| 274 | * | |
| 275 | * Localbus non-cacheable | |
| 276 | * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable | |
| 277 | * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable | |
| 278 | * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 | |
| 279 | * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable | |
| 280 | */ | |
| 281 | ||
| 49249e13 PA |
282 | /* |
| 283 | * IFC Definitions | |
| 284 | */ | |
| 285 | /* NOR Flash on IFC */ | |
| 0fa934d2 | 286 | |
| 49249e13 PA |
287 | #define CONFIG_SYS_FLASH_BASE 0xee000000 |
| 288 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ | |
| 289 | ||
| 290 | #ifdef CONFIG_PHYS_64BIT | |
| 291 | #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) | |
| 292 | #else | |
| 293 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE | |
| 294 | #endif | |
| 295 | ||
| 296 | #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ | |
| 297 | CSPR_PORT_SIZE_16 | \ | |
| 298 | CSPR_MSEL_NOR | \ | |
| 299 | CSPR_V) | |
| 300 | #define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024) | |
| 301 | #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7) | |
| 302 | /* NOR Flash Timing Params */ | |
| 303 | #define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \ | |
| 304 | FTIM0_NOR_TEADC(0x5) | \ | |
| 305 | FTIM0_NOR_TEAHC(0x5) | |
| 306 | #define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \ | |
| 307 | FTIM1_NOR_TRAD_NOR(0x0f) | |
| 308 | #define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \ | |
| 309 | FTIM2_NOR_TCH(0x4) | \ | |
| 310 | FTIM2_NOR_TWP(0x1c) | |
| 311 | #define CONFIG_SYS_NOR_FTIM3 0x0 | |
| 312 | ||
| 313 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} | |
| 314 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
| 315 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
| 316 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
| 317 | ||
| 318 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
| 319 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
| 320 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
| 321 | ||
| 322 | /* CFI for NOR Flash */ | |
| 49249e13 | 323 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
| 49249e13 PA |
324 | |
| 325 | /* NAND Flash on IFC */ | |
| 326 | #define CONFIG_SYS_NAND_BASE 0xff800000 | |
| 327 | #ifdef CONFIG_PHYS_64BIT | |
| 328 | #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull | |
| 329 | #else | |
| 330 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE | |
| 331 | #endif | |
| 332 | ||
| ac688078 | 333 | #define CONFIG_MTD_PARTITION |
| ac688078 | 334 | |
| 49249e13 PA |
335 | #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ |
| 336 | | CSPR_PORT_SIZE_8 \ | |
| 337 | | CSPR_MSEL_NAND \ | |
| 338 | | CSPR_V) | |
| 339 | #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) | |
| e512c50b | 340 | |
| 7601686c | 341 | #if defined(CONFIG_TARGET_P1010RDB_PA) |
| 49249e13 PA |
342 | #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ |
| 343 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | |
| 344 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | |
| 345 | | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \ | |
| 346 | | CSOR_NAND_PGS_512 /* Page Size = 512b */ \ | |
| 347 | | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \ | |
| 348 | | CSOR_NAND_PB(32)) /* 32 Pages Per Block */ | |
| e512c50b SL |
349 | #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) |
| 350 | ||
| 7601686c | 351 | #elif defined(CONFIG_TARGET_P1010RDB_PB) |
| e512c50b SL |
352 | #define CONFIG_SYS_NAND_ONFI_DETECTION |
| 353 | #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | |
| 354 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | |
| 355 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | |
| 356 | | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ | |
| 357 | | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ | |
| 358 | | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ | |
| 359 | | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */ | |
| 360 | #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) | |
| 361 | #endif | |
| 49249e13 | 362 | |
| d793e5a8 DD |
363 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } |
| 364 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
| d793e5a8 | 365 | |
| 7601686c | 366 | #if defined(CONFIG_TARGET_P1010RDB_PA) |
| 49249e13 PA |
367 | /* NAND Flash Timing Params */ |
| 368 | #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \ | |
| 369 | FTIM0_NAND_TWP(0x0C) | \ | |
| 370 | FTIM0_NAND_TWCHT(0x04) | \ | |
| 371 | FTIM0_NAND_TWH(0x05) | |
| 372 | #define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \ | |
| 373 | FTIM1_NAND_TWBE(0x1d) | \ | |
| 374 | FTIM1_NAND_TRR(0x07) | \ | |
| 375 | FTIM1_NAND_TRP(0x0c) | |
| 376 | #define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \ | |
| 377 | FTIM2_NAND_TREH(0x05) | \ | |
| 378 | FTIM2_NAND_TWHRE(0x0f) | |
| 379 | #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) | |
| 380 | ||
| 7601686c | 381 | #elif defined(CONFIG_TARGET_P1010RDB_PB) |
| e512c50b SL |
382 | /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */ |
| 383 | /* ONFI NAND Flash mode0 Timing Params */ | |
| 384 | #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \ | |
| 385 | FTIM0_NAND_TWP(0x18) | \ | |
| 386 | FTIM0_NAND_TWCHT(0x07) | \ | |
| 387 | FTIM0_NAND_TWH(0x0a)) | |
| 388 | #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \ | |
| 389 | FTIM1_NAND_TWBE(0x39) | \ | |
| 390 | FTIM1_NAND_TRR(0x0e) | \ | |
| 391 | FTIM1_NAND_TRP(0x18)) | |
| 392 | #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ | |
| 393 | FTIM2_NAND_TREH(0x0a) | \ | |
| 394 | FTIM2_NAND_TWHRE(0x1e)) | |
| 395 | #define CONFIG_SYS_NAND_FTIM3 0x0 | |
| 396 | #endif | |
| 397 | ||
| 49249e13 PA |
398 | #define CONFIG_SYS_NAND_DDR_LAW 11 |
| 399 | ||
| 400 | /* Set up IFC registers for boot location NOR/NAND */ | |
| 88718be3 | 401 | #if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT) |
| d793e5a8 DD |
402 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR |
| 403 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK | |
| 404 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR | |
| 405 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
| 406 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
| 407 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
| 408 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
| 409 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR | |
| 410 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK | |
| 411 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR | |
| 412 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
| 413 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
| 414 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
| 415 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
| 416 | #else | |
| 49249e13 PA |
417 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR |
| 418 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK | |
| 419 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR | |
| 420 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
| 421 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
| 422 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
| 423 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
| 424 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR | |
| 425 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK | |
| 426 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR | |
| 427 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
| 428 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
| 429 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
| 430 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
| d793e5a8 DD |
431 | #endif |
| 432 | ||
| 49249e13 PA |
433 | /* CPLD on IFC */ |
| 434 | #define CONFIG_SYS_CPLD_BASE 0xffb00000 | |
| 435 | ||
| 436 | #ifdef CONFIG_PHYS_64BIT | |
| 437 | #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull | |
| 438 | #else | |
| 439 | #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE | |
| 440 | #endif | |
| 441 | ||
| 442 | #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ | |
| 443 | | CSPR_PORT_SIZE_8 \ | |
| 444 | | CSPR_MSEL_GPCM \ | |
| 445 | | CSPR_V) | |
| 446 | #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) | |
| 447 | #define CONFIG_SYS_CSOR3 0x0 | |
| 448 | /* CPLD Timing parameters for IFC CS3 */ | |
| 449 | #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ | |
| 450 | FTIM0_GPCM_TEADC(0x0e) | \ | |
| 451 | FTIM0_GPCM_TEAHC(0x0e)) | |
| 452 | #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ | |
| 453 | FTIM1_GPCM_TRAD(0x1f)) | |
| 454 | #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ | |
| de519163 | 455 | FTIM2_GPCM_TCH(0x8) | \ |
| 49249e13 PA |
456 | FTIM2_GPCM_TWP(0x1f)) |
| 457 | #define CONFIG_SYS_CS3_FTIM3 0x0 | |
| 49249e13 | 458 | |
| 76c9aaf5 AB |
459 | #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \ |
| 460 | defined(CONFIG_RAMBOOT_NAND) | |
| 49249e13 | 461 | #define CONFIG_SYS_RAMBOOT |
| 49249e13 PA |
462 | #else |
| 463 | #undef CONFIG_SYS_RAMBOOT | |
| 464 | #endif | |
| 465 | ||
| 74fa22ed | 466 | #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399 |
| 50c76367 | 467 | #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) |
| 74fa22ed PK |
468 | #define CONFIG_A003399_NOR_WORKAROUND |
| 469 | #endif | |
| 470 | #endif | |
| 471 | ||
| 49249e13 PA |
472 | #define CONFIG_SYS_INIT_RAM_LOCK |
| 473 | #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ | |
| b39d1213 | 474 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ |
| 49249e13 | 475 | |
| b39d1213 | 476 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ |
| 49249e13 PA |
477 | - GENERATED_GBL_DATA_SIZE) |
| 478 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
| 479 | ||
| 9307cbab | 480 | #define CONFIG_SYS_MONITOR_LEN (768 * 1024) |
| 49249e13 PA |
481 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ |
| 482 | ||
| c9e1f588 YZ |
483 | /* |
| 484 | * Config the L2 Cache as L2 SRAM | |
| 485 | */ | |
| 486 | #if defined(CONFIG_SPL_BUILD) | |
| 487 | #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) | |
| 488 | #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 | |
| 489 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR | |
| 490 | #define CONFIG_SYS_L2_SIZE (256 << 10) | |
| 491 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) | |
| 492 | #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 | |
| 493 | #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) | |
| c9e1f588 YZ |
494 | #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) |
| 495 | #define CONFIG_SPL_RELOC_MALLOC_SIZE (128 << 10) | |
| 496 | #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024) | |
| 88718be3 | 497 | #elif defined(CONFIG_MTD_RAW_NAND) |
| c9e1f588 YZ |
498 | #ifdef CONFIG_TPL_BUILD |
| 499 | #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 | |
| 500 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR | |
| 501 | #define CONFIG_SYS_L2_SIZE (256 << 10) | |
| 502 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) | |
| 503 | #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 | |
| 504 | #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) | |
| 505 | #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) | |
| 506 | #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) | |
| 507 | #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) | |
| 508 | #else | |
| 509 | #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 | |
| 510 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR | |
| 511 | #define CONFIG_SYS_L2_SIZE (256 << 10) | |
| 512 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) | |
| 513 | #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000) | |
| 514 | #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) | |
| 515 | #endif | |
| 516 | #endif | |
| 517 | #endif | |
| 518 | ||
| 49249e13 | 519 | /* Serial Port */ |
| 49249e13 | 520 | #undef CONFIG_SERIAL_SOFTWARE_FIFO |
| 49249e13 PA |
521 | #define CONFIG_SYS_NS16550_SERIAL |
| 522 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
| 523 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
| c9e1f588 | 524 | #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) |
| d793e5a8 DD |
525 | #define CONFIG_NS16550_MIN_FUNCTIONS |
| 526 | #endif | |
| 49249e13 | 527 | |
| 49249e13 PA |
528 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
| 529 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} | |
| 530 | ||
| 531 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) | |
| 532 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
| 533 | ||
| 00f792e0 | 534 | /* I2C */ |
| 2703e640 | 535 | #ifndef CONFIG_DM_I2C |
| 00f792e0 | 536 | #define CONFIG_SYS_I2C |
| 00f792e0 HS |
537 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 |
| 538 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
| 539 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
| 540 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
| 541 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
| 542 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
| 2703e640 BL |
543 | #else |
| 544 | #define CONFIG_I2C_SET_DEFAULT_BUS_NUM | |
| 545 | #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 | |
| 546 | #endif | |
| ad89da0c | 547 | #define I2C_PCA9557_ADDR1 0x18 |
| e512c50b | 548 | #define I2C_PCA9557_ADDR2 0x19 |
| ad89da0c | 549 | #define I2C_PCA9557_BUS_NUM 0 |
| 2703e640 | 550 | #define CONFIG_SYS_I2C_FSL |
| 49249e13 PA |
551 | |
| 552 | /* I2C EEPROM */ | |
| 7601686c | 553 | #if defined(CONFIG_TARGET_P1010RDB_PB) |
| e512c50b SL |
554 | #define CONFIG_ID_EEPROM |
| 555 | #ifdef CONFIG_ID_EEPROM | |
| 556 | #define CONFIG_SYS_I2C_EEPROM_NXID | |
| 557 | #endif | |
| 558 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
| 559 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 | |
| 560 | #define CONFIG_SYS_EEPROM_BUS_NUM 0 | |
| 561 | #define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */ | |
| 562 | #endif | |
| 49249e13 | 563 | /* enable read and write access to EEPROM */ |
| 49249e13 PA |
564 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
| 565 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
| 566 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 | |
| 567 | ||
| 568 | /* RTC */ | |
| 569 | #define CONFIG_RTC_PT7C4338 | |
| 570 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 | |
| 571 | ||
| 49249e13 PA |
572 | /* |
| 573 | * SPI interface will not be available in case of NAND boot SPI CS0 will be | |
| 574 | * used for SLIC | |
| 575 | */ | |
| 88718be3 | 576 | #if !defined(CONFIG_MTD_RAW_NAND) || !defined(CONFIG_NAND_SECBOOT) |
| 49249e13 | 577 | /* eSPI - Enhanced SPI */ |
| d793e5a8 | 578 | #endif |
| 49249e13 PA |
579 | |
| 580 | #if defined(CONFIG_TSEC_ENET) | |
| 49249e13 PA |
581 | #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ |
| 582 | #define CONFIG_TSEC1 1 | |
| 583 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
| 584 | #define CONFIG_TSEC2 1 | |
| 585 | #define CONFIG_TSEC2_NAME "eTSEC2" | |
| 586 | #define CONFIG_TSEC3 1 | |
| 587 | #define CONFIG_TSEC3_NAME "eTSEC3" | |
| 588 | ||
| 589 | #define TSEC1_PHY_ADDR 1 | |
| 590 | #define TSEC2_PHY_ADDR 0 | |
| 591 | #define TSEC3_PHY_ADDR 2 | |
| 592 | ||
| 593 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 594 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 595 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 596 | ||
| 597 | #define TSEC1_PHYIDX 0 | |
| 598 | #define TSEC2_PHYIDX 0 | |
| 599 | #define TSEC3_PHYIDX 0 | |
| 600 | ||
| 601 | #define CONFIG_ETHPRIME "eTSEC1" | |
| 602 | ||
| 49249e13 PA |
603 | /* TBI PHY configuration for SGMII mode */ |
| 604 | #define CONFIG_TSEC_TBICR_SETTINGS ( \ | |
| 605 | TBICR_PHY_RESET \ | |
| 606 | | TBICR_ANEG_ENABLE \ | |
| 607 | | TBICR_FULL_DUPLEX \ | |
| 608 | | TBICR_SPEED1_SET \ | |
| 609 | ) | |
| 610 | ||
| 611 | #endif /* CONFIG_TSEC_ENET */ | |
| 612 | ||
| 49249e13 | 613 | /* SATA */ |
| 9760b274 | 614 | #define CONFIG_FSL_SATA_V2 |
| 49249e13 PA |
615 | |
| 616 | #ifdef CONFIG_FSL_SATA | |
| 617 | #define CONFIG_SYS_SATA_MAX_DEVICE 2 | |
| 618 | #define CONFIG_SATA1 | |
| 619 | #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR | |
| 620 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA | |
| 621 | #define CONFIG_SATA2 | |
| 622 | #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR | |
| 623 | #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA | |
| 624 | ||
| 49249e13 PA |
625 | #define CONFIG_LBA48 |
| 626 | #endif /* #ifdef CONFIG_FSL_SATA */ | |
| 627 | ||
| 49249e13 | 628 | #ifdef CONFIG_MMC |
| 49249e13 PA |
629 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR |
| 630 | #endif | |
| 631 | ||
| 632 | #define CONFIG_HAS_FSL_DR_USB | |
| 633 | ||
| 634 | #if defined(CONFIG_HAS_FSL_DR_USB) | |
| 8850c5d5 | 635 | #ifdef CONFIG_USB_EHCI_HCD |
| 49249e13 PA |
636 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET |
| 637 | #define CONFIG_USB_EHCI_FSL | |
| 49249e13 PA |
638 | #endif |
| 639 | #endif | |
| 640 | ||
| 641 | /* | |
| 642 | * Environment | |
| 643 | */ | |
| c9e1f588 | 644 | #if defined(CONFIG_SDCARD) |
| 4394d0c2 | 645 | #define CONFIG_FSL_FIXED_MMC_LOCATION |
| 49249e13 | 646 | #define CONFIG_SYS_MMC_ENV_DEV 0 |
| 88718be3 | 647 | #elif defined(CONFIG_MTD_RAW_NAND) |
| c9e1f588 | 648 | #ifdef CONFIG_TPL_BUILD |
| a09fea1d | 649 | #define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) |
| c9e1f588 | 650 | #else |
| 7601686c | 651 | #if defined(CONFIG_TARGET_P1010RDB_PA) |
| e512c50b | 652 | #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */ |
| 7601686c | 653 | #elif defined(CONFIG_TARGET_P1010RDB_PB) |
| e512c50b SL |
654 | #define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */ |
| 655 | #endif | |
| c9e1f588 | 656 | #endif |
| 49249e13 PA |
657 | #endif |
| 658 | ||
| 659 | #define CONFIG_LOADS_ECHO /* echo on for serial download */ | |
| 660 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ | |
| 661 | ||
| 49249e13 PA |
662 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
| 663 | ||
| 8850c5d5 | 664 | #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI_HCD) \ |
| 49249e13 | 665 | || defined(CONFIG_FSL_SATA) |
| 49249e13 PA |
666 | #endif |
| 667 | ||
| 668 | /* | |
| 669 | * Miscellaneous configurable options | |
| 670 | */ | |
| 49249e13 | 671 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
| 49249e13 | 672 | |
| 49249e13 PA |
673 | /* |
| 674 | * For booting Linux, the board info and command line data | |
| 675 | * have to be in the first 64 MB of memory, since this is | |
| 676 | * the maximum mapped by the Linux kernel during initialization. | |
| 677 | */ | |
| 678 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ | |
| 679 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
| 680 | ||
| 681 | #if defined(CONFIG_CMD_KGDB) | |
| 682 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
| 49249e13 PA |
683 | #endif |
| 684 | ||
| 685 | /* | |
| 686 | * Environment Configuration | |
| 687 | */ | |
| 688 | ||
| 689 | #if defined(CONFIG_TSEC_ENET) | |
| 690 | #define CONFIG_HAS_ETH0 | |
| 691 | #define CONFIG_HAS_ETH1 | |
| 692 | #define CONFIG_HAS_ETH2 | |
| 693 | #endif | |
| 694 | ||
| 8b3637c6 | 695 | #define CONFIG_ROOTPATH "/opt/nfsroot" |
| b3f44c21 | 696 | #define CONFIG_BOOTFILE "uImage" |
| 49249e13 PA |
697 | #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ |
| 698 | ||
| 699 | /* default location for tftp and bootm */ | |
| 700 | #define CONFIG_LOADADDR 1000000 | |
| 701 | ||
| 49249e13 | 702 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 5368c55d | 703 | "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ |
| 49249e13 | 704 | "netdev=eth0\0" \ |
| 5368c55d | 705 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ |
| 49249e13 PA |
706 | "loadaddr=1000000\0" \ |
| 707 | "consoledev=ttyS0\0" \ | |
| 708 | "ramdiskaddr=2000000\0" \ | |
| 709 | "ramdiskfile=rootfs.ext2.gz.uboot\0" \ | |
| b24a4f62 | 710 | "fdtaddr=1e00000\0" \ |
| 49249e13 PA |
711 | "fdtfile=p1010rdb.dtb\0" \ |
| 712 | "bdev=sda1\0" \ | |
| 713 | "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \ | |
| 714 | "othbootargs=ramdisk_size=600000\0" \ | |
| 715 | "usbfatboot=setenv bootargs root=/dev/ram rw " \ | |
| 716 | "console=$consoledev,$baudrate $othbootargs; " \ | |
| 717 | "usb start;" \ | |
| 718 | "fatload usb 0:2 $loadaddr $bootfile;" \ | |
| 719 | "fatload usb 0:2 $fdtaddr $fdtfile;" \ | |
| 720 | "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ | |
| 721 | "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ | |
| 722 | "usbext2boot=setenv bootargs root=/dev/ram rw " \ | |
| 723 | "console=$consoledev,$baudrate $othbootargs; " \ | |
| 724 | "usb start;" \ | |
| 725 | "ext2load usb 0:4 $loadaddr $bootfile;" \ | |
| 726 | "ext2load usb 0:4 $fdtaddr $fdtfile;" \ | |
| 727 | "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ | |
| e512c50b SL |
728 | "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ |
| 729 | CONFIG_BOOTMODE | |
| 730 | ||
| 7601686c | 731 | #if defined(CONFIG_TARGET_P1010RDB_PA) |
| e512c50b SL |
732 | #define CONFIG_BOOTMODE \ |
| 733 | "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ | |
| 734 | "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \ | |
| 735 | "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ | |
| 736 | "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \ | |
| 737 | "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \ | |
| 738 | "mw.b ffb00011 0; mw.b ffb00017 1; reset\0" | |
| 739 | ||
| 7601686c | 740 | #elif defined(CONFIG_TARGET_P1010RDB_PB) |
| e512c50b SL |
741 | #define CONFIG_BOOTMODE \ |
| 742 | "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ | |
| 743 | "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \ | |
| 744 | "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ | |
| 745 | "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \ | |
| 746 | "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \ | |
| 747 | "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \ | |
| 748 | "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \ | |
| 749 | "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \ | |
| 750 | "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \ | |
| 751 | "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0" | |
| 752 | #endif | |
| 49249e13 PA |
753 | |
| 754 | #define CONFIG_RAMBOOTCOMMAND \ | |
| 755 | "setenv bootargs root=/dev/ram rw " \ | |
| 756 | "console=$consoledev,$baudrate $othbootargs; " \ | |
| 757 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
| 758 | "tftp $loadaddr $bootfile;" \ | |
| 759 | "tftp $fdtaddr $fdtfile;" \ | |
| 760 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
| 761 | ||
| 762 | #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND | |
| 763 | ||
| 2f439e80 | 764 | #include <asm/fsl_secure_boot.h> |
| 2f439e80 | 765 | |
| 49249e13 | 766 | #endif /* __CONFIG_H */ |