projects / thirdparty / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| c59e1b4d | 2 | /* |
| 3d7506fa | 3 | * Copyright 2010-2012 Freescale Semiconductor, Inc. |
| c59e1b4d TT |
4 | * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> |
| 5 | * Timur Tabi <timur@freescale.com> | |
| c59e1b4d TT |
6 | */ |
| 7 | ||
| 8 | #ifndef __CONFIG_H | |
| 9 | #define __CONFIG_H | |
| 10 | ||
| 11 | #include "../board/freescale/common/ics307_clk.h" | |
| 12 | ||
| af253608 | 13 | #ifdef CONFIG_SDCARD |
| 7c8eea59 YZ |
14 | #define CONFIG_SPL_FLUSH_IMAGE |
| 15 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" | |
| ee4d6511 YZ |
16 | #define CONFIG_SPL_PAD_TO 0x20000 |
| 17 | #define CONFIG_SPL_MAX_SIZE (128 * 1024) | |
| e222b1f3 | 18 | #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) |
| 7c8eea59 YZ |
19 | #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) |
| 20 | #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) | |
| ee4d6511 | 21 | #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10) |
| 7c8eea59 | 22 | #define CONFIG_SYS_MPC85XX_NO_RESETVEC |
| 7c8eea59 YZ |
23 | #ifdef CONFIG_SPL_BUILD |
| 24 | #define CONFIG_SPL_COMMON_INIT_DDR | |
| 25 | #endif | |
| af253608 MM |
26 | #endif |
| 27 | ||
| 28 | #ifdef CONFIG_SPIFLASH | |
| 382ce7e9 YZ |
29 | #define CONFIG_SPL_SPI_FLASH_MINIMAL |
| 30 | #define CONFIG_SPL_FLUSH_IMAGE | |
| 31 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" | |
| ee4d6511 YZ |
32 | #define CONFIG_SPL_PAD_TO 0x20000 |
| 33 | #define CONFIG_SPL_MAX_SIZE (128 * 1024) | |
| e222b1f3 | 34 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) |
| 382ce7e9 YZ |
35 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) |
| 36 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) | |
| ee4d6511 | 37 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) |
| 382ce7e9 | 38 | #define CONFIG_SYS_MPC85XX_NO_RESETVEC |
| 382ce7e9 YZ |
39 | #ifdef CONFIG_SPL_BUILD |
| 40 | #define CONFIG_SPL_COMMON_INIT_DDR | |
| 41 | #endif | |
| af253608 MM |
42 | #endif |
| 43 | ||
| f45210d6 | 44 | #define CONFIG_NAND_FSL_ELBC |
| 9407c3fc YS |
45 | #define CONFIG_SYS_NAND_MAX_ECCPOS 56 |
| 46 | #define CONFIG_SYS_NAND_MAX_OOBFREE 5 | |
| f45210d6 MM |
47 | |
| 48 | #ifdef CONFIG_NAND | |
| 5d97fe2a | 49 | #ifdef CONFIG_TPL_BUILD |
| 5d97fe2a | 50 | #define CONFIG_SPL_FLUSH_IMAGE |
| 989e1ced | 51 | #define CONFIG_SPL_NAND_INIT |
| 5d97fe2a YZ |
52 | #define CONFIG_SPL_COMMON_INIT_DDR |
| 53 | #define CONFIG_SPL_MAX_SIZE (128 << 10) | |
| a6d6812a | 54 | #define CONFIG_TPL_TEXT_BASE 0xf8f81000 |
| 5d97fe2a | 55 | #define CONFIG_SYS_MPC85XX_NO_RESETVEC |
| e222b1f3 | 56 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) |
| 5d97fe2a YZ |
57 | #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) |
| 58 | #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) | |
| 59 | #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) | |
| 60 | #elif defined(CONFIG_SPL_BUILD) | |
| f45210d6 | 61 | #define CONFIG_SPL_INIT_MINIMAL |
| f45210d6 | 62 | #define CONFIG_SPL_FLUSH_IMAGE |
| 5d97fe2a YZ |
63 | #define CONFIG_SPL_MAX_SIZE 4096 |
| 64 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) | |
| 65 | #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 | |
| 66 | #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 | |
| 67 | #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) | |
| 68 | #endif | |
| 69 | #define CONFIG_SPL_PAD_TO 0x20000 | |
| 70 | #define CONFIG_TPL_PAD_TO 0x20000 | |
| 71 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" | |
| f45210d6 MM |
72 | #endif |
| 73 | ||
| c59e1b4d | 74 | /* High Level Configuration Options */ |
| c59e1b4d | 75 | |
| 7a577fda KG |
76 | #ifndef CONFIG_RESET_VECTOR_ADDRESS |
| 77 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc | |
| 78 | #endif | |
| 79 | ||
| b38eaec5 RD |
80 | #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ |
| 81 | #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ | |
| 82 | #define CONFIG_PCIE3 /* PCIE controller 3 (ULI bridge) */ | |
| c59e1b4d | 83 | #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ |
| c59e1b4d TT |
84 | #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ |
| 85 | ||
| c59e1b4d | 86 | #define CONFIG_ENABLE_36BIT_PHYS |
| babb348c TT |
87 | |
| 88 | #ifdef CONFIG_PHYS_64BIT | |
| c59e1b4d TT |
89 | #define CONFIG_ADDR_MAP |
| 90 | #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ | |
| 9899ac19 | 91 | #endif |
| c59e1b4d | 92 | |
| c59e1b4d TT |
93 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() |
| 94 | #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() | |
| 95 | #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ | |
| 96 | ||
| 97 | /* | |
| 98 | * These can be toggled for performance analysis, otherwise use default. | |
| 99 | */ | |
| 100 | #define CONFIG_L2_CACHE | |
| 101 | #define CONFIG_BTB | |
| 102 | ||
| 103 | #define CONFIG_SYS_MEMTEST_START 0x00000000 | |
| 104 | #define CONFIG_SYS_MEMTEST_END 0x7fffffff | |
| 105 | ||
| e46fedfe TT |
106 | #define CONFIG_SYS_CCSRBAR 0xffe00000 |
| 107 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
| c59e1b4d | 108 | |
| f45210d6 MM |
109 | /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k |
| 110 | SPL code*/ | |
| 111 | #ifdef CONFIG_SPL_BUILD | |
| 112 | #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE | |
| 113 | #endif | |
| 114 | ||
| c59e1b4d TT |
115 | /* DDR Setup */ |
| 116 | #define CONFIG_DDR_SPD | |
| 117 | #define CONFIG_VERY_BIG_RAM | |
| c59e1b4d TT |
118 | |
| 119 | #ifdef CONFIG_DDR_ECC | |
| 120 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER | |
| 121 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef | |
| 122 | #endif | |
| 123 | ||
| 124 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
| 125 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
| 126 | ||
| c59e1b4d TT |
127 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
| 128 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) | |
| 129 | ||
| 130 | /* I2C addresses of SPD EEPROMs */ | |
| 131 | #define CONFIG_SYS_SPD_BUS_NUM 1 | |
| c39f44dc | 132 | #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ |
| c59e1b4d | 133 | |
| f45210d6 MM |
134 | /* These are used when DDR doesn't use SPD. */ |
| 135 | #define CONFIG_SYS_SDRAM_SIZE 2048 | |
| 136 | #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G | |
| 137 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F | |
| 138 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 | |
| 139 | #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F | |
| 140 | #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202 | |
| 141 | #define CONFIG_SYS_DDR_TIMING_3 0x00010000 | |
| 142 | #define CONFIG_SYS_DDR_TIMING_0 0x40110104 | |
| 143 | #define CONFIG_SYS_DDR_TIMING_1 0x5c5bd746 | |
| 144 | #define CONFIG_SYS_DDR_TIMING_2 0x0fa8d4ca | |
| 145 | #define CONFIG_SYS_DDR_MODE_1 0x00441221 | |
| 146 | #define CONFIG_SYS_DDR_MODE_2 0x00000000 | |
| 147 | #define CONFIG_SYS_DDR_INTERVAL 0x0a280100 | |
| 148 | #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef | |
| 149 | #define CONFIG_SYS_DDR_CLK_CTRL 0x02800000 | |
| 150 | #define CONFIG_SYS_DDR_CONTROL 0xc7000008 | |
| 151 | #define CONFIG_SYS_DDR_CONTROL_2 0x24401041 | |
| 152 | #define CONFIG_SYS_DDR_TIMING_4 0x00220001 | |
| 153 | #define CONFIG_SYS_DDR_TIMING_5 0x02401400 | |
| 154 | #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 | |
| 155 | #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8675f608 | |
| 156 | ||
| c59e1b4d TT |
157 | /* |
| 158 | * Memory map | |
| 159 | * | |
| 160 | * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable | |
| 161 | * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable | |
| 162 | * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable | |
| 163 | * | |
| 164 | * Localbus cacheable (TBD) | |
| 165 | * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable | |
| 166 | * | |
| 167 | * Localbus non-cacheable | |
| 168 | * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable | |
| 169 | * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable | |
| f45210d6 | 170 | * 0xff80_0000 0xff80_7fff NAND 32K non-cacheable |
| c59e1b4d TT |
171 | * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 |
| 172 | * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 | |
| 173 | * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable | |
| 174 | */ | |
| 175 | ||
| 176 | /* | |
| 177 | * Local Bus Definitions | |
| 178 | */ | |
| f45210d6 | 179 | #define CONFIG_SYS_FLASH_BASE 0xe8000000 /* start of FLASH 128M */ |
| 9899ac19 | 180 | #ifdef CONFIG_PHYS_64BIT |
| f45210d6 | 181 | #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull |
| 9899ac19 JY |
182 | #else |
| 183 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE | |
| 184 | #endif | |
| c59e1b4d TT |
185 | |
| 186 | #define CONFIG_FLASH_BR_PRELIM \ | |
| f45210d6 | 187 | (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) |
| c59e1b4d TT |
188 | #define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7) |
| 189 | ||
| f45210d6 MM |
190 | #ifdef CONFIG_NAND |
| 191 | #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ | |
| 192 | #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ | |
| 193 | #else | |
| c59e1b4d TT |
194 | #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ |
| 195 | #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ | |
| f45210d6 | 196 | #endif |
| c59e1b4d | 197 | |
| f45210d6 | 198 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} |
| c59e1b4d TT |
199 | #define CONFIG_SYS_FLASH_QUIET_TEST |
| 200 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
| 201 | ||
| f45210d6 | 202 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 |
| c59e1b4d TT |
203 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 |
| 204 | ||
| f45210d6 | 205 | #ifndef CONFIG_SYS_MONITOR_BASE |
| a6d6812a TR |
206 | #ifdef CONFIG_TPL_BUILD |
| 207 | #define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE | |
| 208 | #elif defined(CONFIG_SPL_BUILD) | |
| f45210d6 MM |
209 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE |
| 210 | #else | |
| 14d0a02a | 211 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
| f45210d6 MM |
212 | #endif |
| 213 | #endif | |
| c59e1b4d | 214 | |
| c59e1b4d TT |
215 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
| 216 | ||
| f45210d6 MM |
217 | /* Nand Flash */ |
| 218 | #if defined(CONFIG_NAND_FSL_ELBC) | |
| 219 | #define CONFIG_SYS_NAND_BASE 0xff800000 | |
| 220 | #ifdef CONFIG_PHYS_64BIT | |
| 221 | #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull | |
| 222 | #else | |
| 223 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE | |
| 224 | #endif | |
| 225 | ||
| 5d97fe2a | 226 | #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} |
| f45210d6 | 227 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
| 5d97fe2a | 228 | #define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024) |
| f45210d6 MM |
229 | #define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE |
| 230 | ||
| 231 | /* NAND flash config */ | |
| 232 | #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | |
| 233 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | |
| 234 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
| 235 | | BR_MS_FCM /* MSEL = FCM */ \ | |
| 236 | | BR_V) /* valid */ | |
| 237 | #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* length 256K */ \ | |
| 238 | | OR_FCM_PGS /* Large Page*/ \ | |
| 239 | | OR_FCM_CSCT \ | |
| 240 | | OR_FCM_CST \ | |
| 241 | | OR_FCM_CHT \ | |
| 242 | | OR_FCM_SCY_1 \ | |
| 243 | | OR_FCM_TRLX \ | |
| 244 | | OR_FCM_EHTR) | |
| 245 | #ifdef CONFIG_NAND | |
| 246 | #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ | |
| 247 | #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ | |
| 248 | #else | |
| 249 | #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ | |
| 250 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ | |
| 251 | #endif | |
| 252 | ||
| 253 | #endif /* CONFIG_NAND_FSL_ELBC */ | |
| 254 | ||
| a2d12f88 | 255 | #define CONFIG_HWCONFIG |
| c59e1b4d TT |
256 | |
| 257 | #define CONFIG_FSL_NGPIXIS | |
| 258 | #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ | |
| 9899ac19 | 259 | #ifdef CONFIG_PHYS_64BIT |
| c59e1b4d | 260 | #define PIXIS_BASE_PHYS 0xfffdf0000ull |
| 9899ac19 JY |
261 | #else |
| 262 | #define PIXIS_BASE_PHYS PIXIS_BASE | |
| 263 | #endif | |
| c59e1b4d TT |
264 | |
| 265 | #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) | |
| 266 | #define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7) | |
| 267 | ||
| 268 | #define PIXIS_LBMAP_SWITCH 7 | |
| 2906845a | 269 | #define PIXIS_LBMAP_MASK 0xF0 |
| c59e1b4d | 270 | #define PIXIS_LBMAP_ALTBANK 0x20 |
| f45210d6 MM |
271 | #define PIXIS_SPD 0x07 |
| 272 | #define PIXIS_SPD_SYSCLK_MASK 0x07 | |
| 9b6e9d1c JY |
273 | #define PIXIS_ELBC_SPI_MASK 0xc0 |
| 274 | #define PIXIS_SPI 0x80 | |
| c59e1b4d TT |
275 | |
| 276 | #define CONFIG_SYS_INIT_RAM_LOCK | |
| 277 | #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ | |
| 553f0982 | 278 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ |
| c59e1b4d | 279 | |
| c59e1b4d | 280 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
| 25ddd1fb | 281 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
| c59e1b4d TT |
282 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
| 283 | ||
| 9307cbab | 284 | #define CONFIG_SYS_MONITOR_LEN (768 * 1024) |
| 07b5edc2 | 285 | #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) |
| c59e1b4d | 286 | |
| 7c8eea59 YZ |
287 | /* |
| 288 | * Config the L2 Cache as L2 SRAM | |
| 289 | */ | |
| 290 | #if defined(CONFIG_SPL_BUILD) | |
| 382ce7e9 | 291 | #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) |
| 7c8eea59 YZ |
292 | #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 |
| 293 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR | |
| 294 | #define CONFIG_SYS_L2_SIZE (256 << 10) | |
| 295 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) | |
| 296 | #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 | |
| 27585bd3 | 297 | #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) |
| 27585bd3 YZ |
298 | #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) |
| 299 | #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) | |
| 7c8eea59 | 300 | #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) |
| 5d97fe2a YZ |
301 | #elif defined(CONFIG_NAND) |
| 302 | #ifdef CONFIG_TPL_BUILD | |
| 303 | #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 | |
| 304 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR | |
| 305 | #define CONFIG_SYS_L2_SIZE (256 << 10) | |
| 306 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) | |
| 307 | #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 | |
| 308 | #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) | |
| 309 | #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) | |
| 310 | #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) | |
| 311 | #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) | |
| 312 | #else | |
| 313 | #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 | |
| 314 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR | |
| 315 | #define CONFIG_SYS_L2_SIZE (256 << 10) | |
| 316 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) | |
| 317 | #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000) | |
| 318 | #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) | |
| 319 | #endif | |
| 7c8eea59 YZ |
320 | #endif |
| 321 | #endif | |
| 322 | ||
| c59e1b4d TT |
323 | /* |
| 324 | * Serial Port | |
| 325 | */ | |
| c59e1b4d TT |
326 | #define CONFIG_SYS_NS16550_SERIAL |
| 327 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
| 328 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
| 7c8eea59 | 329 | #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) |
| f45210d6 MM |
330 | #define CONFIG_NS16550_MIN_FUNCTIONS |
| 331 | #endif | |
| c59e1b4d TT |
332 | |
| 333 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
| 334 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} | |
| 335 | ||
| 336 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) | |
| 337 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
| 338 | ||
| c59e1b4d | 339 | /* Video */ |
| ba8e76bd | 340 | |
| d5e01e49 TT |
341 | #ifdef CONFIG_FSL_DIU_FB |
| 342 | #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000) | |
| d5e01e49 TT |
343 | #define CONFIG_VIDEO_LOGO |
| 344 | #define CONFIG_VIDEO_BMP_LOGO | |
| 55b05237 TT |
345 | #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS |
| 346 | /* | |
| 347 | * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so | |
| 348 | * disable empty flash sector detection, which is I/O-intensive. | |
| 349 | */ | |
| 350 | #undef CONFIG_SYS_FLASH_EMPTY_INFO | |
| c59e1b4d TT |
351 | #endif |
| 352 | ||
| 218a758f JY |
353 | #ifdef CONFIG_ATI |
| 354 | #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT | |
| 218a758f | 355 | #define CONFIG_BIOSEMU |
| 218a758f JY |
356 | #define CONFIG_ATI_RADEON_FB |
| 357 | #define CONFIG_VIDEO_LOGO | |
| 358 | #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET | |
| 218a758f JY |
359 | #endif |
| 360 | ||
| c59e1b4d | 361 | /* I2C */ |
| 00f792e0 HS |
362 | #define CONFIG_SYS_I2C |
| 363 | #define CONFIG_SYS_I2C_FSL | |
| 364 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
| 365 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
| 366 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
| 367 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
| 368 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
| 369 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
| c59e1b4d | 370 | #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} |
| c59e1b4d TT |
371 | |
| 372 | /* | |
| 373 | * I2C2 EEPROM | |
| 374 | */ | |
| 375 | #define CONFIG_ID_EEPROM | |
| 376 | #define CONFIG_SYS_I2C_EEPROM_NXID | |
| 377 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 | |
| 378 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
| 379 | #define CONFIG_SYS_EEPROM_BUS_NUM 1 | |
| 380 | ||
| 381 | /* | |
| 382 | * General PCI | |
| 383 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
| 384 | */ | |
| 385 | ||
| 386 | /* controller 1, Slot 2, tgtid 1, Base address a000 */ | |
| 387 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 | |
| 9899ac19 | 388 | #ifdef CONFIG_PHYS_64BIT |
| c59e1b4d TT |
389 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 |
| 390 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull | |
| 9899ac19 JY |
391 | #else |
| 392 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 | |
| 393 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 | |
| 394 | #endif | |
| c59e1b4d TT |
395 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ |
| 396 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 | |
| 397 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
| 9899ac19 | 398 | #ifdef CONFIG_PHYS_64BIT |
| c59e1b4d | 399 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull |
| 9899ac19 JY |
400 | #else |
| 401 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 | |
| 402 | #endif | |
| c59e1b4d TT |
403 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ |
| 404 | ||
| 405 | /* controller 2, direct to uli, tgtid 2, Base address 9000 */ | |
| 406 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 | |
| 9899ac19 | 407 | #ifdef CONFIG_PHYS_64BIT |
| c59e1b4d TT |
408 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 |
| 409 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull | |
| 9899ac19 JY |
410 | #else |
| 411 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 | |
| 412 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 | |
| 413 | #endif | |
| c59e1b4d TT |
414 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ |
| 415 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 | |
| 416 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 | |
| 9899ac19 | 417 | #ifdef CONFIG_PHYS_64BIT |
| c59e1b4d | 418 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull |
| 9899ac19 JY |
419 | #else |
| 420 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 | |
| 421 | #endif | |
| c59e1b4d TT |
422 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ |
| 423 | ||
| 424 | /* controller 3, Slot 1, tgtid 3, Base address b000 */ | |
| 425 | #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 | |
| 9899ac19 | 426 | #ifdef CONFIG_PHYS_64BIT |
| c59e1b4d TT |
427 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 |
| 428 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull | |
| 9899ac19 JY |
429 | #else |
| 430 | #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 | |
| 431 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 | |
| 432 | #endif | |
| c59e1b4d TT |
433 | #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ |
| 434 | #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 | |
| 435 | #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 | |
| 9899ac19 | 436 | #ifdef CONFIG_PHYS_64BIT |
| c59e1b4d | 437 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull |
| 9899ac19 JY |
438 | #else |
| 439 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 | |
| 440 | #endif | |
| c59e1b4d TT |
441 | #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ |
| 442 | ||
| 443 | #ifdef CONFIG_PCI | |
| 842033e6 | 444 | #define CONFIG_PCI_INDIRECT_BRIDGE |
| c59e1b4d TT |
445 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
| 446 | #endif | |
| 447 | ||
| 448 | /* SATA */ | |
| 9760b274 | 449 | #define CONFIG_FSL_SATA_V2 |
| c59e1b4d TT |
450 | |
| 451 | #define CONFIG_SYS_SATA_MAX_DEVICE 2 | |
| 452 | #define CONFIG_SATA1 | |
| 453 | #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR | |
| 454 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA | |
| 455 | #define CONFIG_SATA2 | |
| 456 | #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR | |
| 457 | #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA | |
| 458 | ||
| 459 | #ifdef CONFIG_FSL_SATA | |
| 460 | #define CONFIG_LBA48 | |
| c59e1b4d TT |
461 | #endif |
| 462 | ||
| c59e1b4d | 463 | #ifdef CONFIG_MMC |
| c59e1b4d TT |
464 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR |
| 465 | #endif | |
| 466 | ||
| c59e1b4d TT |
467 | #ifdef CONFIG_TSEC_ENET |
| 468 | ||
| 469 | #define CONFIG_TSECV2 | |
| c59e1b4d | 470 | |
| c59e1b4d TT |
471 | #define CONFIG_TSEC1 1 |
| 472 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
| 473 | #define CONFIG_TSEC2 1 | |
| 474 | #define CONFIG_TSEC2_NAME "eTSEC2" | |
| 475 | ||
| 476 | #define TSEC1_PHY_ADDR 1 | |
| 477 | #define TSEC2_PHY_ADDR 2 | |
| 478 | ||
| 479 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 480 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 481 | ||
| 482 | #define TSEC1_PHYIDX 0 | |
| 483 | #define TSEC2_PHYIDX 0 | |
| 484 | ||
| 485 | #define CONFIG_ETHPRIME "eTSEC1" | |
| c59e1b4d TT |
486 | #endif |
| 487 | ||
| 94b383e7 YL |
488 | /* |
| 489 | * Dynamic MTD Partition support with mtdparts | |
| 490 | */ | |
| 94b383e7 | 491 | |
| c59e1b4d TT |
492 | /* |
| 493 | * Environment | |
| 494 | */ | |
| a09fea1d | 495 | #if defined(CONFIG_SDCARD) |
| 7c8eea59 | 496 | #define CONFIG_FSL_FIXED_MMC_LOCATION |
| af253608 | 497 | #define CONFIG_SYS_MMC_ENV_DEV 0 |
| f45210d6 | 498 | #elif defined(CONFIG_NAND) |
| a09fea1d | 499 | #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) |
| 5d97fe2a | 500 | #ifdef CONFIG_TPL_BUILD |
| a09fea1d | 501 | #define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) |
| 5d97fe2a | 502 | #endif |
| f45210d6 | 503 | #elif defined(CONFIG_SYS_RAMBOOT) |
| a09fea1d | 504 | #define SPL_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
| af253608 | 505 | #endif |
| c59e1b4d TT |
506 | |
| 507 | #define CONFIG_LOADS_ECHO | |
| 508 | #define CONFIG_SYS_LOADS_BAUD_CHANGE | |
| 509 | ||
| c59e1b4d TT |
510 | /* |
| 511 | * USB | |
| 512 | */ | |
| 3d7506fa | 513 | #define CONFIG_HAS_FSL_DR_USB |
| 514 | #ifdef CONFIG_HAS_FSL_DR_USB | |
| 8850c5d5 | 515 | #ifdef CONFIG_USB_EHCI_HCD |
| c59e1b4d TT |
516 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET |
| 517 | #define CONFIG_USB_EHCI_FSL | |
| c59e1b4d | 518 | #endif |
| 3d7506fa | 519 | #endif |
| c59e1b4d TT |
520 | |
| 521 | /* | |
| 522 | * Miscellaneous configurable options | |
| 523 | */ | |
| c59e1b4d | 524 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
| c59e1b4d TT |
525 | |
| 526 | /* | |
| 527 | * For booting Linux, the board info and command line data | |
| a832ac41 | 528 | * have to be in the first 64 MB of memory, since this is |
| c59e1b4d TT |
529 | * the maximum mapped by the Linux kernel during initialization. |
| 530 | */ | |
| a832ac41 KG |
531 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ |
| 532 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
| c59e1b4d | 533 | |
| c59e1b4d TT |
534 | #ifdef CONFIG_CMD_KGDB |
| 535 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
| c59e1b4d TT |
536 | #endif |
| 537 | ||
| 538 | /* | |
| 539 | * Environment Configuration | |
| 540 | */ | |
| 541 | ||
| 5bc0543d | 542 | #define CONFIG_HOSTNAME "p1022ds" |
| 8b3637c6 | 543 | #define CONFIG_ROOTPATH "/opt/nfsroot" |
| b3f44c21 | 544 | #define CONFIG_BOOTFILE "uImage" |
| c59e1b4d TT |
545 | #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ |
| 546 | ||
| 547 | #define CONFIG_LOADADDR 1000000 | |
| 548 | ||
| 84e34b65 TT |
549 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 550 | "netdev=eth0\0" \ | |
| 5368c55d MV |
551 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ |
| 552 | "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ | |
| 84e34b65 TT |
553 | "tftpflash=tftpboot $loadaddr $uboot && " \ |
| 554 | "protect off $ubootaddr +$filesize && " \ | |
| 555 | "erase $ubootaddr +$filesize && " \ | |
| 556 | "cp.b $loadaddr $ubootaddr $filesize && " \ | |
| 557 | "protect on $ubootaddr +$filesize && " \ | |
| 558 | "cmp.b $loadaddr $ubootaddr $filesize\0" \ | |
| 559 | "consoledev=ttyS0\0" \ | |
| 560 | "ramdiskaddr=2000000\0" \ | |
| 561 | "ramdiskfile=rootfs.ext2.gz.uboot\0" \ | |
| b24a4f62 | 562 | "fdtaddr=1e00000\0" \ |
| 84e34b65 TT |
563 | "fdtfile=p1022ds.dtb\0" \ |
| 564 | "bdev=sda3\0" \ | |
| ba8e76bd | 565 | "hwconfig=esdhc;audclk:12\0" |
| c59e1b4d TT |
566 | |
| 567 | #define CONFIG_HDBOOT \ | |
| 568 | "setenv bootargs root=/dev/$bdev rw " \ | |
| 84e34b65 | 569 | "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ |
| c59e1b4d TT |
570 | "tftp $loadaddr $bootfile;" \ |
| 571 | "tftp $fdtaddr $fdtfile;" \ | |
| 572 | "bootm $loadaddr - $fdtaddr" | |
| 573 | ||
| 574 | #define CONFIG_NFSBOOTCOMMAND \ | |
| 575 | "setenv bootargs root=/dev/nfs rw " \ | |
| 576 | "nfsroot=$serverip:$rootpath " \ | |
| 577 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
| 84e34b65 | 578 | "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ |
| c59e1b4d TT |
579 | "tftp $loadaddr $bootfile;" \ |
| 580 | "tftp $fdtaddr $fdtfile;" \ | |
| 581 | "bootm $loadaddr - $fdtaddr" | |
| 582 | ||
| 583 | #define CONFIG_RAMBOOTCOMMAND \ | |
| 584 | "setenv bootargs root=/dev/ram rw " \ | |
| 84e34b65 | 585 | "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ |
| c59e1b4d TT |
586 | "tftp $ramdiskaddr $ramdiskfile;" \ |
| 587 | "tftp $loadaddr $bootfile;" \ | |
| 588 | "tftp $fdtaddr $fdtfile;" \ | |
| 589 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
| 590 | ||
| 591 | #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND | |
| 592 | ||
| 593 | #endif |