[thirdparty/u-boot.git] / include / configs / P1023RDB.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright 2013 Freescale Semiconductor, Inc.
 *
 * Authors:  Roy Zang <tie-fei.zang@freescale.com>
 *	     Chunhe Lan <Chunhe.Lan@freescale.com>
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#ifndef CONFIG_SYS_MONITOR_BASE
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
#endif

#ifndef CONFIG_RESET_VECTOR_ADDRESS
#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
#endif

/* High Level Configuration Options */
#define CONFIG_MP		/* support multiple processors */

#define CONFIG_PCI_INDIRECT_BRIDGE     /* indirect PCI bridge support */
#define CONFIG_PCIE1		/* PCIE controller 1 (slot 1) */
#define CONFIG_PCIE2		/* PCIE controller 2 (slot 2) */
#define CONFIG_PCIE3		/* PCIE controller 3 (slot 3) */
#define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
#define CONFIG_FSL_PCIE_RESET	/* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */

#ifndef __ASSEMBLY__
extern unsigned long get_clock_freq(void);
#endif

#define CONFIG_SYS_CLK_FREQ	66666666
#define CONFIG_DDR_CLK_FREQ	CONFIG_SYS_CLK_FREQ

/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CONFIG_L2_CACHE			/* toggle L2 cache */
#define CONFIG_BTB			/* toggle branch predition */
#define CONFIG_HWCONFIG

#define CONFIG_ENABLE_36BIT_PHYS

#define CONFIG_SYS_MEMTEST_START	0x01000000	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x02000000

/* Implement conversion of addresses in the LBC */
#define CONFIG_SYS_LBC_LBCR		0x00000000
#define CONFIG_SYS_LBC_LCRR		LCRR_CLKDIV_8

/* DDR Setup */
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE

#define CONFIG_DIMM_SLOTS_PER_CTLR	1
#define CONFIG_CHIP_SELECTS_PER_CTRL	1

#define CONFIG_DDR_SPD
#define CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SYS_SDRAM_SIZE		512u	/* DDR is 512M */
#define CONFIG_SYS_SPD_BUS_NUM          0
#define SPD_EEPROM_ADDRESS              0x50
#define CONFIG_SYS_DDR_RAW_TIMING

/*
 * Memory map
 *
 * 0x0000_0000	0x1fff_ffff	DDR			512M cacheable
 * 0x8000_0000	0xbfff_ffff	PCI Express Mem		1G non-cacheable
 * 0xc000_0000	0xdfff_ffff	PCI			512M non-cacheable
 * 0xe100_0000	0xe3ff_ffff	PCI IO range		4M non-cacheable
 * 0xff00_0000	0xff3f_ffff	DPAA_QBMAN		4M cacheable
 * 0xff60_0000	0xff7f_ffff	CCSR			2M non-cacheable
 * 0xffd0_0000	0xffd0_3fff	L1 for stack		16K cacheable TLB0
 *
 * Localbus non-cacheable
 *
 * 0xec00_0000	0xefff_ffff	NOR flash		64M non-cacheable
 * 0xffa0_0000	0xffaf_ffff	NAND			1M non-cacheable
 */

/*
 * Local Bus Definitions
 */
#define CONFIG_SYS_FLASH_BASE		0xec000000 /* start of FLASH 64M */
#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE

#define CONFIG_FLASH_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
				| BR_PS_16 | BR_V)
#define CONFIG_FLASH_OR_PRELIM	0xfc000ff7

#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	512	/* sectors per device */
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000	/* Initial L1 address */
#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000/* Size of used area in RAM */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
					GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_LEN	(768 * 1024)	  /* Reserve 512 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN	(6 * 1024 * 1024) /* Reserved for malloc */

#define CONFIG_SYS_NAND_BASE		0xffa00000
#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE

#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_NAND_FSL_ELBC
#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)

/* NAND flash config */
#define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
				| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
				| BR_PS_8		/* Port Size = 8bit */ \
				| BR_MS_FCM		/* MSEL = FCM */ \
				| BR_V)			/* valid */
#define CONFIG_SYS_NAND_OR_PRELIM  (OR_AM_256KB		/* length 256K */ \
				| OR_FCM_PGS \
				| OR_FCM_CSCT \
				| OR_FCM_CST \
				| OR_FCM_CHT \
				| OR_FCM_SCY_1 \
				| OR_FCM_TRLX \
				| OR_FCM_EHTR)

#define CONFIG_SYS_BR0_PRELIM	CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
#define CONFIG_SYS_OR0_PRELIM	CONFIG_FLASH_OR_PRELIM	/* NOR Options */
#define CONFIG_SYS_BR1_PRELIM	CONFIG_SYS_NAND_BR_PRELIM
#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */

/* Serial Port */
#undef	CONFIG_SERIAL_SOFTWARE_FIFO
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_BAUDRATE_TABLE	\
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR + 0x4500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR + 0x4600)

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	400000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
#define CONFIG_SYS_FSL_I2C2_SPEED	400000
#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100

/*
 * I2C2 EEPROM
 */
#define CONFIG_ID_EEPROM
#ifdef CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#endif
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
#define CONFIG_SYS_EEPROM_BUS_NUM		0

/*
 * General PCI
 * Memory space is mapped 1-1, but I/O space must start from 0.
 */

/* controller 3, Slot 1, tgtid 3, Base address b000 */
#define CONFIG_SYS_PCIE3_NAME		"Slot 3"
#define CONFIG_SYS_PCIE3_MEM_VIRT	0x80000000
#define CONFIG_SYS_PCIE3_MEM_BUS	0x80000000
#define CONFIG_SYS_PCIE3_MEM_PHYS	0x80000000
#define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
#define CONFIG_SYS_PCIE3_IO_VIRT	0xffc00000
#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
#define CONFIG_SYS_PCIE3_IO_PHYS	0xffc00000
#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */

/* controller 2, direct to uli, tgtid 2, Base address 9000 */
#define CONFIG_SYS_PCIE2_NAME		"Slot 2"
#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
#define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
#define CONFIG_SYS_PCIE2_IO_VIRT	0xffc10000
#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
#define CONFIG_SYS_PCIE2_IO_PHYS	0xffc10000
#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */

/* controller 1, Slot 2, tgtid 1, Base address a000 */
#define CONFIG_SYS_PCIE1_NAME		"Slot 1"
#define CONFIG_SYS_PCIE1_MEM_VIRT	0xc0000000
#define CONFIG_SYS_PCIE1_MEM_BUS	0xc0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc0000000
#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
#define CONFIG_SYS_PCIE1_IO_VIRT	0xffc20000
#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS	0xffc20000
#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */

#if defined(CONFIG_PCI)
#define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
#endif	/* CONFIG_PCI */

/*
 * Environment
 */
#define CONFIG_ENV_OVERWRITE

#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE		0x2000
#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */

#define CONFIG_LOADS_ECHO		/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */

/*
 * USB
 */
#define CONFIG_HAS_FSL_DR_USB
#ifdef CONFIG_HAS_FSL_DR_USB
#ifdef CONFIG_USB_EHCI_HCD
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_USB_EHCI_FSL
#endif
#endif

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 64 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)   /* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTM_LEN	(64 << 20)   /* Increase max gunzip size */

/*
 * Environment Configuration
 */
#define CONFIG_BOOTFILE		"uImage"
#define CONFIG_UBOOTPATH	(u-boot.bin) /* U-Boot image on TFTP server */

/* default location for tftp and bootm */
#define CONFIG_LOADADDR		1000000

/* Qman/Bman */
#define CONFIG_SYS_QMAN_MEM_BASE	0xff000000
#define CONFIG_SYS_QMAN_MEM_PHYS	CONFIG_SYS_QMAN_MEM_BASE
#define CONFIG_SYS_QMAN_MEM_SIZE	0x00200000
#define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
#define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
#define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
#define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
					CONFIG_SYS_QMAN_CENA_SIZE)
#define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_QMAN_SWP_ISDR_REG	0xE08
#define CONFIG_SYS_BMAN_MEM_BASE	0xff200000
#define CONFIG_SYS_BMAN_MEM_PHYS	CONFIG_SYS_BMAN_MEM_BASE
#define CONFIG_SYS_BMAN_MEM_SIZE	0x00200000
#define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
#define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
#define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
#define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
					CONFIG_SYS_BMAN_CENA_SIZE)
#define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_BMAN_SWP_ISDR_REG	0xE08

/* For FM */
#define CONFIG_SYS_DPAA_FMAN

#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_FMAN_ENET
#define CONFIG_PHY_ATHEROS
#endif

/* Default address of microcode for the Linux Fman driver */
/* QE microcode/firmware address */
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
#define CONFIG_SYS_FMAN_FW_ADDR	0xEFF00000
#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)

#ifdef CONFIG_FMAN_ENET
#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR	0x1
#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR	0x2

#define CONFIG_SYS_TBIPA_VALUE	8
#define CONFIG_MII		/* MII PHY management */
#define CONFIG_ETHPRIME		"FM1@DTSEC1"
#endif

#define CONFIG_EXTRA_ENV_SETTINGS	\
	"netdev=eth0\0"						\
	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
	"loadaddr=1000000\0"					\
	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
	"tftpflash=tftpboot $loadaddr $uboot; "			\
		"protect off $ubootaddr +$filesize; "		\
		"erase $ubootaddr +$filesize; "			\
		"cp.b $loadaddr $ubootaddr $filesize; "		\
		"protect on $ubootaddr +$filesize; "		\
		"cmp.b $loadaddr $ubootaddr $filesize\0"	\
	"consoledev=ttyS0\0"					\
	"ramdiskaddr=2000000\0"					\
	"ramdiskfile=rootfs.ext2.gz.uboot\0"			\
	"fdtaddr=1e00000\0"					\
	"fdtfile=p1023rdb.dtb\0"				\
	"othbootargs=ramdisk_size=600000\0"			\
	"bdev=sda1\0"						\
	"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"

#define CONFIG_HDBOOT					\
	"setenv bootargs root=/dev/$bdev rw "		\
	"console=$consoledev,$baudrate $othbootargs;"	\
	"tftp $loadaddr $bootfile;"			\
	"tftp $fdtaddr $fdtfile;"			\
	"bootm $loadaddr - $fdtaddr"

#define CONFIG_NFSBOOTCOMMAND						\
	"setenv bootargs root=/dev/nfs rw "				\
	"nfsroot=$serverip:$rootpath "					\
	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
	"console=$consoledev,$baudrate $othbootargs;"			\
	"tftp $loadaddr $bootfile;"					\
	"tftp $fdtaddr $fdtfile;"					\
	"bootm $loadaddr - $fdtaddr"

#define CONFIG_RAMBOOTCOMMAND						\
	"setenv bootargs root=/dev/ram rw "				\
	"console=$consoledev,$baudrate $othbootargs;"			\
	"tftp $ramdiskaddr $ramdiskfile;"				\
	"tftp $loadaddr $bootfile;"					\
	"tftp $fdtaddr $fdtfile;"					\
	"bootm $loadaddr $ramdiskaddr $fdtaddr"

#define CONFIG_BOOTCOMMAND		CONFIG_RAMBOOTCOMMAND

#endif	/* __CONFIG_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
57072338 CL	2	/*
	3	* Copyright 2013 Freescale Semiconductor, Inc.
	4	*
	5	* Authors: Roy Zang <tie-fei.zang@freescale.com>
	6	* Chunhe Lan <Chunhe.Lan@freescale.com>
57072338 CL	7	*/
	8
	9	#ifndef __CONFIG_H
	10	#define __CONFIG_H
	11
57072338 CL	12	#ifndef CONFIG_SYS_MONITOR_BASE
	13	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
	14	#endif
	15
	16	#ifndef CONFIG_RESET_VECTOR_ADDRESS
	17	#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
	18	#endif
	19
	20	/* High Level Configuration Options */
57072338 CL	21	#define CONFIG_MP /* support multiple processors */
57072338 CL	22
57072338	23	#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
b38eaec5 RD	24	#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
	25	#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
	26	#define CONFIG_PCIE3 /* PCIE controller 3 (slot 3) */
57072338 CL	27	#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
	28	#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
	29	#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
57072338 CL	30
	31	#ifndef __ASSEMBLY__
	32	extern unsigned long get_clock_freq(void);
	33	#endif
	34
	35	#define CONFIG_SYS_CLK_FREQ 66666666
	36	#define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ
	37
	38	/*
	39	* These can be toggled for performance analysis, otherwise use default.
	40	*/
	41	#define CONFIG_L2_CACHE /* toggle L2 cache */
	42	#define CONFIG_BTB /* toggle branch predition */
	43	#define CONFIG_HWCONFIG
	44
	45	#define CONFIG_ENABLE_36BIT_PHYS
	46
	47	#define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */
	48	#define CONFIG_SYS_MEMTEST_END 0x02000000
	49
57072338 CL	50	/* Implement conversion of addresses in the LBC */
	51	#define CONFIG_SYS_LBC_LBCR 0x00000000
	52	#define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
	53
	54	/* DDR Setup */
	55	#define CONFIG_VERY_BIG_RAM
	56	#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
	57	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
	58
	59	#define CONFIG_DIMM_SLOTS_PER_CTLR 1
	60	#define CONFIG_CHIP_SELECTS_PER_CTRL 1
	61
	62	#define CONFIG_DDR_SPD
57072338 CL	63	#define CONFIG_FSL_DDR_INTERACTIVE
	64	#define CONFIG_SYS_SDRAM_SIZE 512u /* DDR is 512M */
	65	#define CONFIG_SYS_SPD_BUS_NUM 0
	66	#define SPD_EEPROM_ADDRESS 0x50
	67	#define CONFIG_SYS_DDR_RAW_TIMING
	68
	69	/*
	70	* Memory map
	71	*
	72	* 0x0000_0000 0x1fff_ffff DDR 512M cacheable
	73	* 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
	74	* 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
	75	* 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
	76	* 0xff00_0000 0xff3f_ffff DPAA_QBMAN 4M cacheable
	77	* 0xff60_0000 0xff7f_ffff CCSR 2M non-cacheable
	78	* 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable TLB0
	79	*
	80	* Localbus non-cacheable
	81	*
	82	* 0xec00_0000 0xefff_ffff NOR flash 64M non-cacheable
	83	* 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
	84	*/
	85
	86	/*
	87	* Local Bus Definitions
	88	*/
	89	#define CONFIG_SYS_FLASH_BASE 0xec000000 /* start of FLASH 64M */
	90	#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
	91
	92	#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
	93	\| BR_PS_16 \| BR_V)
	94	#define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
	95
	96	#define CONFIG_FLASH_CFI_DRIVER
	97	#define CONFIG_SYS_FLASH_CFI
	98	#define CONFIG_SYS_FLASH_EMPTY_INFO
	99	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
	100	#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
	101	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	102	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
	103
57072338 CL	104	#define CONFIG_SYS_INIT_RAM_LOCK
	105	#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
	106	#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000/* Size of used area in RAM */
	107	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
	108	GENERATED_GBL_DATA_SIZE)
	109	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
	110
9307cbab	111	#define CONFIG_SYS_MONITOR_LEN (768 * 1024) /* Reserve 512 kB for Mon */
57072338 CL	112	#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */
	113
	114	#define CONFIG_SYS_NAND_BASE 0xffa00000
	115	#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
	116
	117	#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
	118	#define CONFIG_SYS_MAX_NAND_DEVICE 1
57072338 CL	119	#define CONFIG_NAND_FSL_ELBC
	120	#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
	121
	122	/* NAND flash config */
	123	#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
	124	\| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
	125	\| BR_PS_8 /* Port Size = 8bit */ \
	126	\| BR_MS_FCM /* MSEL = FCM */ \
	127	\| BR_V) /* valid */
	128	#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB /* length 256K */ \
	129	\| OR_FCM_PGS \
	130	\| OR_FCM_CSCT \
	131	\| OR_FCM_CST \
	132	\| OR_FCM_CHT \
	133	\| OR_FCM_SCY_1 \
	134	\| OR_FCM_TRLX \
	135	\| OR_FCM_EHTR)
	136
	137	#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
	138	#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
	139	#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
	140	#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
	141
	142	/* Serial Port */
57072338	143	#undef CONFIG_SERIAL_SOFTWARE_FIFO
57072338 CL	144	#define CONFIG_SYS_NS16550_SERIAL
	145	#define CONFIG_SYS_NS16550_REG_SIZE 1
	146	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
	147
	148	#define CONFIG_SYS_BAUDRATE_TABLE \
	149	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
	150
	151	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
	152	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
	153
57072338	154	/* I2C */
00f792e0 HS	155	#define CONFIG_SYS_I2C
	156	#define CONFIG_SYS_I2C_FSL
	157	#define CONFIG_SYS_FSL_I2C_SPEED 400000
	158	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	159	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
	160	#define CONFIG_SYS_FSL_I2C2_SPEED 400000
	161	#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
	162	#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
57072338 CL	163
	164	/*
	165	* I2C2 EEPROM
	166	*/
	167	#define CONFIG_ID_EEPROM
	168	#ifdef CONFIG_ID_EEPROM
	169	#define CONFIG_SYS_I2C_EEPROM_NXID
	170	#endif
	171	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
	172	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	173	#define CONFIG_SYS_EEPROM_BUS_NUM 0
	174
57072338 CL	175	/*
	176	* General PCI
	177	* Memory space is mapped 1-1, but I/O space must start from 0.
	178	*/
	179
	180	/* controller 3, Slot 1, tgtid 3, Base address b000 */
	181	#define CONFIG_SYS_PCIE3_NAME "Slot 3"
	182	#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
	183	#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
	184	#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
	185	#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
	186	#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
	187	#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
	188	#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
	189	#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
	190
	191	/* controller 2, direct to uli, tgtid 2, Base address 9000 */
	192	#define CONFIG_SYS_PCIE2_NAME "Slot 2"
	193	#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
	194	#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
	195	#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
	196	#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
	197	#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
	198	#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
	199	#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
	200	#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
	201
	202	/* controller 1, Slot 2, tgtid 1, Base address a000 */
	203	#define CONFIG_SYS_PCIE1_NAME "Slot 1"
	204	#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
	205	#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
	206	#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
	207	#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
	208	#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
	209	#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
	210	#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
	211	#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
	212
	213	#if defined(CONFIG_PCI)
57072338 CL	214	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
	215	#endif /* CONFIG_PCI */
	216
	217	/*
	218	* Environment
	219	*/
	220	#define CONFIG_ENV_OVERWRITE
	221
57072338	222	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
57072338 CL	223	#define CONFIG_ENV_SIZE 0x2000
	224	#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
	225
	226	#define CONFIG_LOADS_ECHO /* echo on for serial download */
	227	#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
	228
57072338 CL	229	/*
	230	* USB
	231	*/
	232	#define CONFIG_HAS_FSL_DR_USB
	233	#ifdef CONFIG_HAS_FSL_DR_USB
8850c5d5	234	#ifdef CONFIG_USB_EHCI_HCD
57072338 CL	235	#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
57072338 CL	236	#define CONFIG_USB_EHCI_FSL
57072338 CL	237	#endif
	238	#endif
	239
	240	/*
	241	* Miscellaneous configurable options
	242	*/
57072338	243	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
57072338 CL	244
	245	/*
	246	* For booting Linux, the board info and command line data
	247	* have to be in the first 64 MB of memory, since this is
	248	* the maximum mapped by the Linux kernel during initialization.
	249	*/
	250	#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
	251	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
	252
	253	/*
	254	* Environment Configuration
	255	*/
	256	#define CONFIG_BOOTFILE "uImage"
	257	#define CONFIG_UBOOTPATH (u-boot.bin) /* U-Boot image on TFTP server */
	258
	259	/* default location for tftp and bootm */
	260	#define CONFIG_LOADADDR 1000000
	261
57072338	262	/* Qman/Bman */
57072338 CL	263	#define CONFIG_SYS_QMAN_MEM_BASE 0xff000000
	264	#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
	265	#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
3fa66db4 JL	266	#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
	267	#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
	268	#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
	269	#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
	270	#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
	271	CONFIG_SYS_QMAN_CENA_SIZE)
	272	#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
	273	#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
57072338 CL	274	#define CONFIG_SYS_BMAN_MEM_BASE 0xff200000
	275	#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
	276	#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
3fa66db4 JL	277	#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
	278	#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
	279	#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
	280	#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
	281	#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
	282	CONFIG_SYS_BMAN_CENA_SIZE)
	283	#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
	284	#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
57072338 CL	285
	286	/* For FM */
	287	#define CONFIG_SYS_DPAA_FMAN
57072338 CL	288
	289	#ifdef CONFIG_SYS_DPAA_FMAN
	290	#define CONFIG_FMAN_ENET
	291	#define CONFIG_PHY_ATHEROS
	292	#endif
	293
	294	/* Default address of microcode for the Linux Fman driver */
	295	/* QE microcode/firmware address */
	296	#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
dcf1d774	297	#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
57072338 CL	298	#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
	299	#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
	300
	301	#ifdef CONFIG_FMAN_ENET
	302	#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1
	303	#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x2
	304
	305	#define CONFIG_SYS_TBIPA_VALUE 8
	306	#define CONFIG_MII /* MII PHY management */
	307	#define CONFIG_ETHPRIME "FM1@DTSEC1"
	308	#endif
	309
	310	#define CONFIG_EXTRA_ENV_SETTINGS \
5eabbae0 CL	311	"netdev=eth0\0" \
	312	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
	313	"loadaddr=1000000\0" \
	314	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
	315	"tftpflash=tftpboot $loadaddr $uboot; " \
	316	"protect off $ubootaddr +$filesize; " \
	317	"erase $ubootaddr +$filesize; " \
	318	"cp.b $loadaddr $ubootaddr $filesize; " \
	319	"protect on $ubootaddr +$filesize; " \
	320	"cmp.b $loadaddr $ubootaddr $filesize\0" \
	321	"consoledev=ttyS0\0" \
	322	"ramdiskaddr=2000000\0" \
	323	"ramdiskfile=rootfs.ext2.gz.uboot\0" \
b24a4f62	324	"fdtaddr=1e00000\0" \
5eabbae0 CL	325	"fdtfile=p1023rdb.dtb\0" \
	326	"othbootargs=ramdisk_size=600000\0" \
	327	"bdev=sda1\0" \
57072338 CL	328	"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
57072338 CL	329
5eabbae0 CL	330	#define CONFIG_HDBOOT \
	331	"setenv bootargs root=/dev/$bdev rw " \
	332	"console=$consoledev,$baudrate $othbootargs;" \
	333	"tftp $loadaddr $bootfile;" \
	334	"tftp $fdtaddr $fdtfile;" \
	335	"bootm $loadaddr - $fdtaddr"
	336
	337	#define CONFIG_NFSBOOTCOMMAND \
	338	"setenv bootargs root=/dev/nfs rw " \
	339	"nfsroot=$serverip:$rootpath " \
	340	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
	341	"console=$consoledev,$baudrate $othbootargs;" \
	342	"tftp $loadaddr $bootfile;" \
	343	"tftp $fdtaddr $fdtfile;" \
	344	"bootm $loadaddr - $fdtaddr"
	345
	346	#define CONFIG_RAMBOOTCOMMAND \
	347	"setenv bootargs root=/dev/ram rw " \
	348	"console=$consoledev,$baudrate $othbootargs;" \
	349	"tftp $ramdiskaddr $ramdiskfile;" \
	350	"tftp $loadaddr $bootfile;" \
	351	"tftp $fdtaddr $fdtfile;" \
	352	"bootm $loadaddr $ramdiskaddr $fdtaddr"
	353
	354	#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
	355
57072338	356	#endif /* __CONFIG_H */