projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 3f7f6b85 | 1 | /* |
| 3d7506fa | 2 | * Copyright 2010-2012 Freescale Semiconductor, Inc. |
| 3f7f6b85 RZ |
3 | * |
| 4 | * Authors: Roy Zang <tie-fei.zang@freescale.com> | |
| 5 | * Chunhe Lan <b25806@freescale.com> | |
| 6 | * | |
| 7 | * See file CREDITS for list of people who contributed to this | |
| 8 | * project. | |
| 9 | * | |
| 10 | * This program is free software; you can redistribute it and/or | |
| 11 | * modify it under the terms of the GNU General Public License as | |
| 12 | * published by the Free Software Foundation; either version 2 of | |
| 13 | * the License, or (at your option) any later version. | |
| 14 | * | |
| 15 | * This program is distributed in the hope that it will be useful, | |
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 18 | * GNU General Public License for more details. | |
| 19 | * | |
| 20 | * You should have received a copy of the GNU General Public License | |
| 21 | * along with this program; if not, write to the Free Software | |
| 22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 23 | * MA 02111-1307 USA | |
| 24 | */ | |
| 25 | ||
| 26 | /* | |
| 27 | * p1023rds board configuration file | |
| 28 | * | |
| 29 | */ | |
| 30 | #ifndef __CONFIG_H | |
| 31 | #define __CONFIG_H | |
| 32 | ||
| 33 | #ifdef CONFIG_NAND | |
| 34 | #define CONFIG_NAND_U_BOOT | |
| 35 | #define CONFIG_RAMBOOT_NAND | |
| 36 | #endif | |
| 37 | ||
| 38 | #ifdef CONFIG_NAND_U_BOOT | |
| 39 | #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 | |
| 40 | #define CONFIG_SYS_TEXT_BASE 0x11001000 | |
| 41 | ||
| 42 | #ifdef CONFIG_NAND_SPL | |
| 43 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ | |
| 44 | #else | |
| 45 | #define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds | |
| 46 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ | |
| 47 | #endif /* CONFIG_NAND_SPL */ | |
| 48 | #endif | |
| 49 | ||
| 50 | #ifndef CONFIG_SYS_TEXT_BASE | |
| 51 | #define CONFIG_SYS_TEXT_BASE 0xeff80000 | |
| 52 | #endif | |
| 53 | ||
| 54 | #ifndef CONFIG_SYS_MONITOR_BASE | |
| 55 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ | |
| 56 | #endif | |
| 57 | ||
| 58 | #ifndef CONFIG_RESET_VECTOR_ADDRESS | |
| 59 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc | |
| 60 | #endif | |
| 61 | ||
| 62 | /* High Level Configuration Options */ | |
| 63 | #define CONFIG_BOOKE /* BOOKE */ | |
| 64 | #define CONFIG_E500 /* BOOKE e500 family */ | |
| 65 | #define CONFIG_MPC85xx | |
| 66 | #define CONFIG_P1023 | |
| 67 | #define CONFIG_P1023RDS | |
| 68 | #define CONFIG_MP /* support multiple processors */ | |
| 69 | ||
| 70 | #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ | |
| 71 | #define CONFIG_PCI /* Enable PCI/PCIE */ | |
| 72 | #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ | |
| 73 | #define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */ | |
| 74 | #define CONFIG_PCIE3 /* PCIE controler 3 (slot 3) */ | |
| 75 | #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ | |
| 76 | #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ | |
| 77 | #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ | |
| 78 | #define CONFIG_FSL_LAW /* Use common FSL init code */ | |
| 79 | ||
| 80 | #ifndef __ASSEMBLY__ | |
| 81 | extern unsigned long get_clock_freq(void); | |
| 82 | #endif | |
| 83 | ||
| 84 | #define CONFIG_SYS_CLK_FREQ 66666666 | |
| 85 | #define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ | |
| 86 | ||
| 87 | /* | |
| 88 | * These can be toggled for performance analysis, otherwise use default. | |
| 89 | */ | |
| 90 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
| 91 | #define CONFIG_BTB /* toggle branch predition */ | |
| 92 | #define CONFIG_HWCONFIG | |
| 93 | ||
| 94 | #define CONFIG_ENABLE_36BIT_PHYS | |
| 95 | ||
| 96 | #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ | |
| 97 | #define CONFIG_SYS_MEMTEST_END 0x1fffffff /* fix me, only 1G */ | |
| 98 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ | |
| 99 | ||
| 100 | #define CONFIG_SYS_LBC_LBCR 0x00000000 /* Implement conversion of | |
| 101 | addresses in the LBC */ | |
| 3f7f6b85 RZ |
102 | |
| 103 | /* DDR Setup */ | |
| 104 | #define CONFIG_VERY_BIG_RAM | |
| 105 | ||
| 106 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER | |
| 107 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
| 108 | ||
| 109 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
| 110 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
| 111 | ||
| 112 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
| 113 | #define CONFIG_CHIP_SELECTS_PER_CTRL 2 | |
| 114 | ||
| 115 | /* These are used when DDR doesn't use SPD. */ | |
| 116 | #define CONFIG_SYS_SDRAM_SIZE 2048u /* DDR is 2GB */ | |
| 117 | ||
| 118 | /* Default settings for "stable" mode */ | |
| 119 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F | |
| 120 | #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F | |
| 121 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 | |
| 122 | #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 | |
| 123 | #define CONFIG_SYS_DDR_TIMING_3 0x00020000 | |
| 124 | #define CONFIG_SYS_DDR_TIMING_0 0x40110104 | |
| 125 | #define CONFIG_SYS_DDR_TIMING_1 0x5C59E544 | |
| 126 | #define CONFIG_SYS_DDR_TIMING_2 0x0fA888CA | |
| 127 | #define CONFIG_SYS_DDR_MODE_1 0x00441210 | |
| 128 | #define CONFIG_SYS_DDR_MODE_2 0x00000000 | |
| 129 | #define CONFIG_SYS_DDR_MODE_CTRL 0x00000000 | |
| 130 | #define CONFIG_SYS_DDR_INTERVAL 0x0A280100 | |
| 131 | #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef | |
| 132 | #define CONFIG_SYS_DDR_CLK_CTRL 0x01800000 | |
| 133 | #define CONFIG_SYS_DDR_TIMING_4 0x00000001 | |
| 134 | #define CONFIG_SYS_DDR_TIMING_5 0x01401400 | |
| 135 | #define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 | |
| 136 | #define CONFIG_SYS_DDR_WRLVL_CNTL 0x8675F605 | |
| 137 | #define CONFIG_SYS_DDR_CONTROL 0xC70C0008 /* Type = DDR3: No Interleaving */ | |
| 138 | #define CONFIG_SYS_DDR_CONTROL2 0x24401010 | |
| 139 | #define CONFIG_SYS_DDR_CDR1 0x00000000 | |
| 140 | #define CONFIG_SYS_DDR_CDR2 0x00000000 | |
| 141 | ||
| 142 | #define CONFIG_SYS_DDR_ERR_INT_EN 0x00000000 | |
| 143 | #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 | |
| 144 | #define CONFIG_SYS_DDR_SBE 0x00000000 | |
| 145 | ||
| 146 | /* Settings that differ for "performance" mode */ | |
| 147 | #define CONFIG_SYS_DDR_CS0_BNDS_PERF 0x0000007F /* Interleaving Enabled */ | |
| 148 | #define CONFIG_SYS_DDR_CS1_BNDS_PERF 0x00000000 /* Interleaving Enabled */ | |
| 149 | #define CONFIG_SYS_DDR_CS1_CONFIG_PERF 0x80014302 | |
| 150 | #define CONFIG_SYS_DDR_TIMING_1_PERF 0x5C58E544 | |
| 151 | #define CONFIG_SYS_DDR_TIMING_2_PERF 0x0FA888CA | |
| 152 | /* Type = DDR3: cs0-cs1 interleaving */ | |
| 153 | #define CONFIG_SYS_DDR_CONTROL_PERF 0xC70C4008 | |
| 154 | #define CONFIG_SYS_DDR_CDR_1 0x00000000 | |
| 155 | #define CONFIG_SYS_DDR_CDR_2 0x00000000 | |
| 156 | ||
| 157 | ||
| 158 | /* | |
| 159 | * Memory map | |
| 160 | * | |
| 161 | * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable | |
| 162 | * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable | |
| 163 | * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable | |
| 164 | * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable | |
| 165 | * | |
| 166 | * Localbus non-cacheable | |
| 167 | * 0xe000_0000 0xe003_ffff BCSR 256K BCSR | |
| 168 | * 0xee00_0000 0xefff_ffff NOR flash 32M NOR flash | |
| 169 | * 0xff00_0000 0xff3f_ffff DPAA_QBMAN 4M | |
| 170 | * 0xff60_0000 0xff7f_ffff CCSR 2M non-cacheable | |
| 171 | * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable | |
| 172 | * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 | |
| 173 | */ | |
| 174 | ||
| 175 | /* | |
| 176 | * Local Bus Definitions | |
| 177 | */ | |
| 178 | #define CONFIG_SYS_BCSR_BASE 0xe0000000 /* start of on board FPGA */ | |
| 179 | #define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE | |
| 180 | ||
| 181 | #ifndef CONFIG_NAND | |
| 182 | #define CONFIG_SYS_FLASH_BASE 0xee000000 /* start of FLASH 32M */ | |
| 183 | ||
| 184 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE | |
| 185 | ||
| 186 | #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ | |
| 187 | | BR_PS_16 | BR_V) | |
| 188 | #define CONFIG_FLASH_OR_PRELIM 0xfe000ff7 | |
| 189 | ||
| 190 | #define CONFIG_FLASH_CFI_DRIVER | |
| 191 | #define CONFIG_SYS_FLASH_CFI | |
| 192 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
| 193 | ||
| 194 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
| 195 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ | |
| 196 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
| 197 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
| 198 | #else | |
| 199 | #define CONFIG_SYS_NO_FLASH | |
| 200 | #endif | |
| 201 | ||
| 202 | #if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) | |
| 203 | #define CONFIG_SYS_RAMBOOT | |
| 204 | #endif | |
| 205 | ||
| 206 | #define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f function */ | |
| 207 | #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ | |
| 208 | ||
| 209 | #define CONFIG_SYS_INIT_RAM_LOCK | |
| 210 | #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ | |
| 211 | #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ | |
| 212 | ||
| 213 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ | |
| 214 | #define CONFIG_SYS_GBL_DATA_OFFSET \ | |
| 215 | (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
| 216 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
| 217 | ||
| 218 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ | |
| 219 | #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */ | |
| 220 | ||
| 221 | #ifndef CONFIG_NAND_SPL | |
| 222 | #define CONFIG_SYS_NAND_BASE 0xffa00000 | |
| 223 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE | |
| 224 | #else | |
| 225 | #define CONFIG_SYS_NAND_BASE 0xfff00000 | |
| 226 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE | |
| 227 | #endif | |
| 228 | ||
| 229 | #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} | |
| 230 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
| 231 | #define CONFIG_MTD_NAND_VERIFY_WRITE | |
| 232 | #define CONFIG_CMD_NAND | |
| 233 | #define CONFIG_NAND_FSL_ELBC | |
| 234 | #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) | |
| 235 | ||
| 236 | /* NAND boot: 4K NAND loader config */ | |
| 237 | #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 | |
| 238 | #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) + CONFIG_SYS_NAND_SPL_SIZE) | |
| 239 | #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000 - CONFIG_SYS_NAND_SPL_SIZE) | |
| 240 | #define CONFIG_SYS_NAND_U_BOOT_START 0x11000000 | |
| 241 | #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) | |
| 242 | #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 | |
| 243 | #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000) | |
| 244 | ||
| 245 | /* NAND flash config */ | |
| 246 | #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | |
| 247 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | |
| 248 | | BR_PS_8 /* Port Size = 8bit */ \ | |
| 249 | | BR_MS_FCM /* MSEL = FCM */ \ | |
| 250 | | BR_V) /* valid */ | |
| 251 | #define CONFIG_SYS_NAND_OR_PRELIM (0xFFF80000 /* length 32K */ \ | |
| 252 | | OR_FCM_CSCT \ | |
| 253 | | OR_FCM_CST \ | |
| 254 | | OR_FCM_CHT \ | |
| 255 | | OR_FCM_SCY_1 \ | |
| 256 | | OR_FCM_TRLX \ | |
| 257 | | OR_FCM_EHTR) | |
| 258 | ||
| 259 | #ifdef CONFIG_RAMBOOT_NAND | |
| 260 | /* NAND Base Address */ | |
| 261 | #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM | |
| 262 | #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ | |
| 263 | /* chip select 1 - BCSR */ | |
| 264 | #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_BCSR_BASE_PHYS) \ | |
| 265 | | BR_MS_GPCM | BR_PS_8 | BR_V) | |
| 266 | #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_XACS \ | |
| 267 | | OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR \ | |
| 268 | | OR_GPCM_EAD) | |
| 269 | #else | |
| 270 | #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ | |
| 271 | #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ | |
| 272 | /* chip select 1 - BCSR */ | |
| 273 | #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_BCSR_BASE_PHYS) \ | |
| 274 | | BR_MS_GPCM | BR_PS_8 | BR_V) | |
| 275 | #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_XACS \ | |
| 276 | | OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR \ | |
| 277 | | OR_GPCM_EAD) | |
| 278 | #endif | |
| 279 | ||
| 280 | /* Serial Port | |
| 281 | * open - index 2 | |
| 282 | * shorted - index 1 | |
| 283 | */ | |
| 284 | #define CONFIG_CONS_INDEX 1 | |
| 285 | #undef CONFIG_SERIAL_SOFTWARE_FIFO | |
| 286 | #define CONFIG_SYS_NS16550 | |
| 287 | #define CONFIG_SYS_NS16550_SERIAL | |
| 288 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
| 289 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
| 290 | #ifdef CONFIG_NAND_SPL | |
| 291 | #define CONFIG_NS16550_MIN_FUNCTIONS | |
| 292 | #endif | |
| 293 | ||
| 294 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
| 295 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} | |
| 296 | ||
| 297 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) | |
| 298 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) | |
| 299 | ||
| 300 | /* Use the HUSH parser */ | |
| 301 | #define CONFIG_SYS_HUSH_PARSER | |
| 3f7f6b85 RZ |
302 | |
| 303 | /* | |
| 304 | * Pass open firmware flat tree | |
| 305 | */ | |
| 306 | #define CONFIG_OF_LIBFDT | |
| 307 | #define CONFIG_OF_BOARD_SETUP | |
| 308 | #define CONFIG_OF_STDOUT_VIA_ALIAS | |
| 309 | ||
| 3f7f6b85 RZ |
310 | /* new uImage format support */ |
| 311 | #define CONFIG_FIT | |
| 312 | #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ | |
| 313 | ||
| 314 | /* I2C */ | |
| 315 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
| 316 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
| 317 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
| 318 | #define CONFIG_I2C_MULTI_BUS | |
| 319 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ | |
| 320 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x51 | |
| 321 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
| 322 | #define CONFIG_SYS_I2C_OFFSET 0x3000 | |
| 323 | #define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
| 324 | ||
| 325 | /* | |
| 326 | * I2C2 EEPROM | |
| 327 | */ | |
| 328 | #define CONFIG_ID_EEPROM | |
| 329 | #ifdef CONFIG_ID_EEPROM | |
| 330 | #define CONFIG_SYS_I2C_EEPROM_NXID | |
| 331 | #endif | |
| 332 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x51 | |
| 333 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
| 334 | #define CONFIG_SYS_EEPROM_BUS_NUM 0 | |
| 335 | ||
| 336 | #define CONFIG_CMD_I2C | |
| 337 | ||
| 338 | /* | |
| 339 | * eSPI - Enhanced SPI | |
| 340 | */ | |
| 341 | #define CONFIG_SPI_FLASH | |
| 342 | #define CONFIG_SPI_FLASH_ATMEL | |
| 343 | ||
| 344 | #define CONFIG_HARD_SPI | |
| 345 | #define CONFIG_FSL_ESPI | |
| 346 | ||
| 347 | #define CONFIG_CMD_SF | |
| 348 | #define CONFIG_SF_DEFAULT_SPEED 10000000 | |
| 349 | #define CONFIG_SF_DEFAULT_MODE 0 | |
| 350 | ||
| 351 | /* | |
| 352 | * General PCI | |
| 353 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
| 354 | */ | |
| 355 | ||
| 356 | /* controller 3, Slot 1, tgtid 3, Base address b000 */ | |
| 357 | #define CONFIG_SYS_PCIE3_NAME "Slot 3" | |
| 358 | #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 | |
| 359 | #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 | |
| 360 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 | |
| 361 | #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ | |
| 362 | #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 | |
| 363 | #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 | |
| 364 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 | |
| 365 | #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ | |
| 366 | ||
| 367 | /* controller 2, direct to uli, tgtid 2, Base address 9000 */ | |
| 368 | #define CONFIG_SYS_PCIE2_NAME "Slot 2" | |
| 369 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 | |
| 370 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 | |
| 371 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 | |
| 372 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ | |
| 373 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 | |
| 374 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 | |
| 375 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 | |
| 376 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ | |
| 377 | ||
| 378 | /* controller 1, Slot 2, tgtid 1, Base address a000 */ | |
| 379 | #define CONFIG_SYS_PCIE1_NAME "Slot 1" | |
| 380 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 | |
| 381 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 | |
| 382 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 | |
| 383 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ | |
| 384 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 | |
| 385 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
| 386 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 | |
| 387 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ | |
| 388 | ||
| 389 | #if defined(CONFIG_PCI) | |
| 390 | #define CONFIG_E1000 /* Defind e1000 pci Ethernet card */ | |
| 3f7f6b85 RZ |
391 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
| 392 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
| 393 | #endif /* CONFIG_PCI */ | |
| 394 | ||
| 3f7f6b85 RZ |
395 | /* |
| 396 | * Environment | |
| 397 | */ | |
| 398 | #define CONFIG_ENV_OVERWRITE | |
| 399 | ||
| 400 | #if defined(CONFIG_SYS_RAMBOOT) | |
| 401 | #if defined(CONFIG_RAMBOOT_NAND) | |
| 402 | #define CONFIG_ENV_IS_IN_NAND | |
| 403 | #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE | |
| 404 | #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) | |
| 405 | #else | |
| 406 | #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ | |
| 407 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x4000) | |
| 408 | #define CONFIG_ENV_SIZE 0x2000 | |
| 409 | #endif | |
| 410 | #else | |
| 411 | #define CONFIG_ENV_IS_IN_FLASH | |
| 412 | #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 | |
| 413 | #define CONFIG_ENV_ADDR 0xfff80000 | |
| 414 | #else | |
| 415 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) | |
| 416 | #endif | |
| 417 | #define CONFIG_ENV_SIZE 0x2000 | |
| 418 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ | |
| 419 | #endif | |
| 420 | ||
| 421 | #define CONFIG_LOADS_ECHO /* echo on for serial download */ | |
| 422 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ | |
| 423 | ||
| 424 | /* | |
| 425 | * Command line configuration. | |
| 426 | */ | |
| 427 | #include <config_cmd_default.h> | |
| 428 | ||
| 429 | #define CONFIG_CMD_IRQ | |
| 430 | #define CONFIG_CMD_PING | |
| 431 | #define CONFIG_CMD_MII | |
| 432 | #define CONFIG_CMD_ELF | |
| 433 | #define CONFIG_CMD_SETEXPR | |
| 434 | #define CONFIG_CMD_REGINFO | |
| 435 | ||
| 436 | #if defined(CONFIG_PCI) | |
| 437 | #define CONFIG_CMD_PCI | |
| 438 | #define CONFIG_CMD_NET | |
| 439 | #endif | |
| 440 | ||
| 441 | /* | |
| 442 | * USB | |
| 443 | */ | |
| 3d7506fa | 444 | #define CONFIG_HAS_FSL_DR_USB |
| 445 | #ifdef CONFIG_HAS_FSL_DR_USB | |
| 3f7f6b85 RZ |
446 | #define CONFIG_USB_EHCI |
| 447 | ||
| 448 | #ifdef CONFIG_USB_EHCI | |
| 449 | #define CONFIG_CMD_USB | |
| 450 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
| 451 | #define CONFIG_USB_EHCI_FSL | |
| 452 | #define CONFIG_USB_STORAGE | |
| 453 | #define CONFIG_CMD_FAT | |
| 454 | #define CONFIG_CMD_EXT2 | |
| 455 | #define CONFIG_CMD_FAT | |
| 456 | #define CONFIG_DOS_PARTITION | |
| 457 | #endif | |
| 3d7506fa | 458 | #endif |
| 3f7f6b85 RZ |
459 | |
| 460 | /* | |
| 461 | * Miscellaneous configurable options | |
| 462 | */ | |
| 463 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
| 464 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ | |
| 465 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
| 466 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
| 467 | #if defined(CONFIG_CMD_KGDB) | |
| 468 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
| 469 | #else | |
| 470 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
| 471 | #endif | |
| 472 | /* Print Buffer Size */ | |
| 473 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16) | |
| 474 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
| 475 | /* Boot Argument Buffer Size */ | |
| 476 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
| 477 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ | |
| 478 | ||
| 479 | /* | |
| 480 | * For booting Linux, the board info and command line data | |
| 481 | * have to be in the first 16 MB of memory, since this is | |
| 482 | * the maximum mapped by the Linux kernel during initialization. | |
| 483 | */ | |
| 484 | #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ | |
| 485 | #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ | |
| 486 | ||
| 487 | #if defined(CONFIG_CMD_KGDB) | |
| 488 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
| 489 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
| 490 | #endif | |
| 491 | ||
| 492 | /* | |
| 493 | * Environment Configuration | |
| 494 | */ | |
| b3f44c21 | 495 | #define CONFIG_BOOTFILE "uImage" |
| 3f7f6b85 RZ |
496 | #define CONFIG_UBOOTPATH (u-boot.bin) /* U-Boot image on TFTP server */ |
| 497 | ||
| 498 | /* default location for tftp and bootm */ | |
| 499 | #define CONFIG_LOADADDR 1000000 | |
| 500 | ||
| 501 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ | |
| 502 | ||
| 503 | #define CONFIG_BAUDRATE 115200 | |
| 504 | ||
| 505 | /* Qman/Bman */ | |
| 506 | #define CONFIG_SYS_DPAA_QBMAN /* support Q/Bman */ | |
| 507 | #define CONFIG_SYS_QMAN_MEM_BASE 0xff000000 | |
| 508 | #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE | |
| 509 | #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 | |
| 510 | #define CONFIG_SYS_BMAN_MEM_BASE 0xff200000 | |
| 511 | #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE | |
| 512 | #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 | |
| 513 | ||
| 514 | /* For FM */ | |
| 515 | #define CONFIG_SYS_DPAA_FMAN | |
| 516 | #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ | |
| 517 | ||
| 518 | #ifdef CONFIG_SYS_DPAA_FMAN | |
| 519 | #define CONFIG_FMAN_ENET | |
| fe1a1da0 | 520 | #define CONFIG_PHY_MARVELL |
| 3f7f6b85 RZ |
521 | #endif |
| 522 | ||
| 523 | #ifndef CONFIG_NAND | |
| 524 | /* Default address of microcode for the Linux Fman driver */ | |
| 525 | /* QE microcode/firmware address */ | |
| f2717b47 | 526 | #define CONFIG_SYS_QE_FMAN_FW_IN_NOR |
| 021382ca | 527 | #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000 |
| 3f7f6b85 | 528 | #else |
| f2717b47 TT |
529 | #define CONFIG_SYS_QE_FMAN_FW_IN_NAND |
| 530 | #define CONFIG_SYS_QE_FMAN_FW_ADDR 0x1f00000 | |
| 3f7f6b85 | 531 | #endif |
| f2717b47 TT |
532 | #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 |
| 533 | #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) | |
| 3f7f6b85 RZ |
534 | |
| 535 | #ifdef CONFIG_FMAN_ENET | |
| 536 | #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2 | |
| 537 | #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x7 | |
| 538 | ||
| 539 | #define CONFIG_SYS_TBIPA_VALUE 8 | |
| 540 | #define CONFIG_MII /* MII PHY management */ | |
| 541 | #define CONFIG_ETHPRIME "FM1@DTSEC1" | |
| 542 | #endif | |
| 543 | ||
| 544 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 545 | "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" | |
| 546 | ||
| 547 | #endif /* __CONFIG_H */ |