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728ece34 | 1 | /* |
7c57f3e8 | 2 | * Copyright 2009-2011 Freescale Semiconductor, Inc. |
728ece34 | 3 | * |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
728ece34 PA |
5 | */ |
6 | ||
7 | /* | |
8 | * P1 P2 RDB board configuration file | |
9 | * This file is intended to address a set of Low End and Ultra Low End | |
10 | * Freescale SOCs of QorIQ series(RDB platforms). | |
11 | * Currently only P2020RDB | |
12 | */ | |
13 | ||
14 | #ifndef __CONFIG_H | |
15 | #define __CONFIG_H | |
16 | ||
e0082f7c PA |
17 | #ifdef CONFIG_36BIT |
18 | #define CONFIG_PHYS_64BIT | |
19 | #endif | |
20 | ||
d24f2d32 | 21 | #ifdef CONFIG_P1011RDB |
62ca21c4 | 22 | #define CONFIG_P1011 |
bc2d40ca | 23 | #define CONFIG_SYS_L2_SIZE (256 << 10) |
62ca21c4 | 24 | #endif |
d24f2d32 | 25 | #ifdef CONFIG_P1020RDB |
62ca21c4 | 26 | #define CONFIG_P1020 |
bc2d40ca | 27 | #define CONFIG_SYS_L2_SIZE (256 << 10) |
62ca21c4 | 28 | #endif |
d24f2d32 | 29 | #ifdef CONFIG_P2010RDB |
62ca21c4 | 30 | #define CONFIG_P2010 |
bc2d40ca | 31 | #define CONFIG_SYS_L2_SIZE (512 << 10) |
62ca21c4 | 32 | #endif |
d24f2d32 | 33 | #ifdef CONFIG_P2020RDB |
62ca21c4 | 34 | #define CONFIG_P2020 |
bc2d40ca | 35 | #define CONFIG_SYS_L2_SIZE (512 << 10) |
f7780ec9 DD |
36 | #endif |
37 | ||
d24f2d32 | 38 | #ifdef CONFIG_SDCARD |
bc2d40ca PK |
39 | #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT |
40 | #define CONFIG_SPL_ENV_SUPPORT | |
41 | #define CONFIG_SPL_SERIAL_SUPPORT | |
42 | #define CONFIG_SPL_MMC_SUPPORT | |
43 | #define CONFIG_SPL_MMC_MINIMAL | |
44 | #define CONFIG_SPL_FLUSH_IMAGE | |
45 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" | |
46 | #define CONFIG_SPL_LIBGENERIC_SUPPORT | |
47 | #define CONFIG_SPL_LIBCOMMON_SUPPORT | |
48 | #define CONFIG_SPL_I2C_SUPPORT | |
49 | #define CONFIG_SYS_TEXT_BASE 0x11001000 | |
50 | #define CONFIG_SPL_TEXT_BASE 0xf8f81000 | |
51 | #define CONFIG_SPL_PAD_TO 0x20000 | |
52 | #define CONFIG_SPL_MAX_SIZE (128 * 1024) | |
53 | #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) | |
54 | #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) | |
55 | #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) | |
56 | #define CONFIG_SYS_MMC_U_BOOT_OFFS (129 << 10) | |
57 | #define CONFIG_SYS_MPC85XX_NO_RESETVEC | |
58 | #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" | |
59 | #define CONFIG_SPL_MMC_BOOT | |
60 | #ifdef CONFIG_SPL_BUILD | |
61 | #define CONFIG_SPL_COMMON_INIT_DDR | |
62 | #endif | |
fad15096 DD |
63 | #endif |
64 | ||
d24f2d32 | 65 | #ifdef CONFIG_SPIFLASH |
bc2d40ca PK |
66 | #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT |
67 | #define CONFIG_SPL_ENV_SUPPORT | |
68 | #define CONFIG_SPL_SERIAL_SUPPORT | |
69 | #define CONFIG_SPL_SPI_SUPPORT | |
70 | #define CONFIG_SPL_SPI_FLASH_SUPPORT | |
71 | #define CONFIG_SPL_SPI_FLASH_MINIMAL | |
72 | #define CONFIG_SPL_FLUSH_IMAGE | |
73 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" | |
74 | #define CONFIG_SPL_LIBGENERIC_SUPPORT | |
75 | #define CONFIG_SPL_LIBCOMMON_SUPPORT | |
76 | #define CONFIG_SPL_I2C_SUPPORT | |
77 | #define CONFIG_SYS_TEXT_BASE 0x11001000 | |
78 | #define CONFIG_SPL_TEXT_BASE 0xf8f81000 | |
79 | #define CONFIG_SPL_PAD_TO 0x20000 | |
80 | #define CONFIG_SPL_MAX_SIZE (128 * 1024) | |
81 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) | |
82 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) | |
83 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) | |
84 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) | |
85 | #define CONFIG_SYS_MPC85XX_NO_RESETVEC | |
86 | #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" | |
87 | #define CONFIG_SPL_SPI_BOOT | |
88 | #ifdef CONFIG_SPL_BUILD | |
89 | #define CONFIG_SPL_COMMON_INIT_DDR | |
90 | #endif | |
91 | #endif | |
92 | ||
93 | #ifdef CONFIG_NAND | |
bc2d40ca PK |
94 | #ifdef CONFIG_TPL_BUILD |
95 | #define CONFIG_SPL_NAND_BOOT | |
96 | #define CONFIG_SPL_FLUSH_IMAGE | |
97 | #define CONFIG_SPL_ENV_SUPPORT | |
98 | #define CONFIG_SPL_NAND_INIT | |
99 | #define CONFIG_SPL_SERIAL_SUPPORT | |
100 | #define CONFIG_SPL_LIBGENERIC_SUPPORT | |
101 | #define CONFIG_SPL_LIBCOMMON_SUPPORT | |
102 | #define CONFIG_SPL_I2C_SUPPORT | |
103 | #define CONFIG_SPL_NAND_SUPPORT | |
104 | #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT | |
105 | #define CONFIG_SPL_COMMON_INIT_DDR | |
106 | #define CONFIG_SPL_MAX_SIZE (128 << 10) | |
107 | #define CONFIG_SPL_TEXT_BASE 0xf8f81000 | |
108 | #define CONFIG_SYS_MPC85XX_NO_RESETVEC | |
109 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) | |
110 | #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) | |
111 | #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) | |
112 | #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) | |
113 | #elif defined(CONFIG_SPL_BUILD) | |
114 | #define CONFIG_SPL_INIT_MINIMAL | |
115 | #define CONFIG_SPL_SERIAL_SUPPORT | |
116 | #define CONFIG_SPL_NAND_SUPPORT | |
117 | #define CONFIG_SPL_FLUSH_IMAGE | |
118 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" | |
119 | #define CONFIG_SPL_TEXT_BASE 0xff800000 | |
120 | #define CONFIG_SPL_MAX_SIZE 4096 | |
121 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) | |
122 | #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 | |
123 | #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 | |
124 | #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) | |
125 | #endif /* not CONFIG_TPL_BUILD */ | |
126 | ||
127 | #define CONFIG_SPL_PAD_TO 0x20000 | |
128 | #define CONFIG_TPL_PAD_TO 0x20000 | |
129 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" | |
130 | #define CONFIG_SYS_TEXT_BASE 0x11001000 | |
131 | #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" | |
2ae18241 WD |
132 | #endif |
133 | ||
134 | #ifndef CONFIG_SYS_TEXT_BASE | |
e222b1f3 | 135 | #define CONFIG_SYS_TEXT_BASE 0xeff40000 |
fad15096 DD |
136 | #endif |
137 | ||
7a577fda KG |
138 | #ifndef CONFIG_RESET_VECTOR_ADDRESS |
139 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc | |
140 | #endif | |
141 | ||
96196a1f | 142 | #ifndef CONFIG_SYS_MONITOR_BASE |
bc2d40ca PK |
143 | #ifdef CONFIG_SPL_BUILD |
144 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE | |
145 | #else | |
96196a1f HW |
146 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
147 | #endif | |
bc2d40ca | 148 | #endif |
96196a1f | 149 | |
728ece34 PA |
150 | /* High Level Configuration Options */ |
151 | #define CONFIG_BOOKE 1 /* BOOKE */ | |
152 | #define CONFIG_E500 1 /* BOOKE e500 family */ | |
728ece34 | 153 | #define CONFIG_FSL_ELBC 1 /* Enable eLBC Support */ |
b7070904 | 154 | |
33f3f342 | 155 | #define CONFIG_PCI 1 /* Enable PCI/PCIE */ |
b7070904 | 156 | #if defined(CONFIG_PCI) |
33f3f342 PA |
157 | #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ |
158 | #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ | |
159 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ | |
842033e6 | 160 | #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ |
33f3f342 PA |
161 | #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ |
162 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ | |
b7070904 | 163 | #endif /* #if defined(CONFIG_PCI) */ |
728ece34 PA |
164 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ |
165 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ | |
166 | #define CONFIG_ENV_OVERWRITE | |
167 | ||
b7070904 | 168 | #if defined(CONFIG_PCI) |
ddac6f08 | 169 | #define CONFIG_E1000 1 /* E1000 pci Ethernet card*/ |
b7070904 PK |
170 | #endif |
171 | ||
728ece34 PA |
172 | #ifndef __ASSEMBLY__ |
173 | extern unsigned long get_board_sys_clk(unsigned long dummy); | |
174 | #endif | |
175 | #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1_P2 RDB */ | |
176 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /*sysclk for P1_P2 RDB */ | |
177 | ||
178 | #if defined(CONFIG_P2020) || defined(CONFIG_P1020) | |
179 | #define CONFIG_MP | |
180 | #endif | |
181 | ||
525f6c3a PA |
182 | #define CONFIG_HWCONFIG |
183 | ||
728ece34 PA |
184 | /* |
185 | * These can be toggled for performance analysis, otherwise use default. | |
186 | */ | |
187 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
188 | #define CONFIG_BTB /* toggle branch predition */ | |
189 | ||
190 | #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ | |
191 | ||
192 | #define CONFIG_ENABLE_36BIT_PHYS 1 | |
193 | ||
e0082f7c PA |
194 | #ifdef CONFIG_PHYS_64BIT |
195 | #define CONFIG_ADDR_MAP 1 | |
196 | #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ | |
197 | #endif | |
198 | ||
728ece34 PA |
199 | #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ |
200 | #define CONFIG_SYS_MEMTEST_END 0x1fffffff | |
201 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ | |
202 | ||
bc2d40ca PK |
203 | /* |
204 | * Config the L2 Cache as L2 SRAM | |
205 | */ | |
206 | #if defined(CONFIG_SPL_BUILD) | |
207 | #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) | |
f7780ec9 | 208 | #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 |
bc2d40ca PK |
209 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR |
210 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) | |
211 | #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 | |
212 | #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) | |
213 | #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) | |
214 | #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) | |
215 | #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) | |
216 | #if defined(CONFIG_P2020RDB) | |
217 | #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10) | |
218 | #else | |
219 | #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) | |
220 | #endif | |
221 | #elif defined(CONFIG_NAND) | |
222 | #ifdef CONFIG_TPL_BUILD | |
223 | #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 | |
224 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR | |
225 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) | |
226 | #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 | |
227 | #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) | |
228 | #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) | |
229 | #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) | |
230 | #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) | |
f7780ec9 | 231 | #else |
bc2d40ca | 232 | #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 |
f7780ec9 | 233 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR |
bc2d40ca PK |
234 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) |
235 | #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000) | |
236 | #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) | |
237 | #endif /* CONFIG_TPL_BUILD */ | |
238 | #endif | |
f7780ec9 | 239 | #endif |
f7780ec9 | 240 | |
bc2d40ca | 241 | #ifdef CONFIG_SPL_BUILD |
e46fedfe | 242 | #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE |
f7780ec9 DD |
243 | #endif |
244 | ||
728ece34 | 245 | /* DDR Setup */ |
5614e71b | 246 | #define CONFIG_SYS_FSL_DDR2 |
728ece34 PA |
247 | #undef CONFIG_FSL_DDR_INTERACTIVE |
248 | #undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ | |
728ece34 PA |
249 | |
250 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
251 | ||
bc2d40ca PK |
252 | #if defined(CONFIG_P1011RDB) || defined(CONFIG_P1020RDB) |
253 | /* | |
254 | * P1020 and it's derivatives support max 32bit DDR width | |
255 | * So Reduce available DDR size | |
256 | */ | |
257 | #define CONFIG_SYS_SDRAM_SIZE 512 | |
258 | #else | |
259 | #define CONFIG_SYS_SDRAM_SIZE 1024 | |
260 | #endif | |
728ece34 PA |
261 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 |
262 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
263 | ||
264 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
265 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
266 | #define CONFIG_CHIP_SELECTS_PER_CTRL 1 | |
267 | ||
268 | #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d | |
269 | #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 | |
270 | #define CONFIG_SYS_DDR_SBE 0x00FF0000 | |
271 | ||
728ece34 PA |
272 | /* |
273 | * Memory map | |
274 | * | |
275 | * 0x0000_0000 0x3fff_ffff DDR 1G cacheablen | |
b0c5ceb3 PK |
276 | * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable |
277 | * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable | |
728ece34 PA |
278 | * |
279 | * Localbus cacheable (TBD) | |
280 | * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable | |
281 | * | |
282 | * Localbus non-cacheable | |
283 | * 0xef00_0000 0xefff_ffff FLASH 16M non-cacheable | |
284 | * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable | |
285 | * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable | |
286 | * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 | |
287 | * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable | |
288 | */ | |
289 | ||
290 | /* | |
291 | * Local Bus Definitions | |
292 | */ | |
293 | #define CONFIG_SYS_FLASH_BASE 0xef000000 /* start of FLASH 16M */ | |
294 | ||
e0082f7c PA |
295 | #ifdef CONFIG_PHYS_64BIT |
296 | #define CONFIG_SYS_FLASH_BASE_PHYS 0xfef000000ull | |
297 | #else | |
728ece34 | 298 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE |
e0082f7c | 299 | #endif |
728ece34 PA |
300 | |
301 | #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ | |
302 | BR_PS_16 | BR_V) | |
303 | #define CONFIG_FLASH_OR_PRELIM 0xff000ff7 | |
304 | ||
e0082f7c | 305 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} |
728ece34 PA |
306 | #define CONFIG_SYS_FLASH_QUIET_TEST |
307 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
308 | ||
309 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
310 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ | |
311 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
312 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
313 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
314 | ||
728ece34 PA |
315 | #define CONFIG_FLASH_CFI_DRIVER |
316 | #define CONFIG_SYS_FLASH_CFI | |
317 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
318 | #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 | |
319 | ||
320 | #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ | |
2bad42a0 | 321 | #define CONFIG_MISC_INIT_R |
66e821eb | 322 | #define CONFIG_HWCONFIG |
728ece34 PA |
323 | |
324 | #define CONFIG_SYS_INIT_RAM_LOCK 1 | |
325 | #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ | |
e0082f7c PA |
326 | #ifdef CONFIG_PHYS_64BIT |
327 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf | |
328 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR | |
329 | /* The assembler doesn't like typecast */ | |
330 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ | |
331 | ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ | |
332 | CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) | |
333 | #else | |
334 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ | |
335 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 | |
336 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS | |
337 | #endif | |
553f0982 | 338 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ |
728ece34 | 339 | |
553f0982 | 340 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ |
25ddd1fb | 341 | - GENERATED_GBL_DATA_SIZE) |
728ece34 PA |
342 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
343 | ||
9307cbab | 344 | #define CONFIG_SYS_MONITOR_LEN (768 * 1024) |
728ece34 PA |
345 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ |
346 | ||
bc2d40ca | 347 | #define CONFIG_SYS_NAND_BASE 0xff800000 |
e0082f7c | 348 | #ifdef CONFIG_PHYS_64BIT |
bc2d40ca | 349 | #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull |
f7780ec9 | 350 | #else |
e0082f7c | 351 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE |
f7780ec9 | 352 | #endif |
e0082f7c | 353 | |
6bbb3e93 | 354 | #define CONFIG_CMD_NAND |
728ece34 PA |
355 | #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} |
356 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
728ece34 | 357 | #define CONFIG_MTD_NAND_VERIFY_WRITE |
728ece34 PA |
358 | #define CONFIG_NAND_FSL_ELBC 1 |
359 | #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) | |
360 | ||
361 | /* NAND flash config */ | |
a3055c58 | 362 | #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ |
728ece34 PA |
363 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
364 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
365 | | BR_MS_FCM /* MSEL = FCM */ \ | |
366 | | BR_V) /* valid */ | |
367 | ||
a3055c58 | 368 | #define CONFIG_SYS_NAND_OR_PRELIM (0xFFF80000 /* length 32K */ \ |
728ece34 PA |
369 | | OR_FCM_CSCT \ |
370 | | OR_FCM_CST \ | |
371 | | OR_FCM_CHT \ | |
372 | | OR_FCM_SCY_1 \ | |
373 | | OR_FCM_TRLX \ | |
374 | | OR_FCM_EHTR) | |
375 | ||
bc2d40ca | 376 | #ifdef CONFIG_NAND |
a3055c58 MM |
377 | #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ |
378 | #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ | |
f7780ec9 DD |
379 | #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ |
380 | #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ | |
381 | #else | |
728ece34 PA |
382 | #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ |
383 | #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ | |
a3055c58 MM |
384 | #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ |
385 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ | |
f7780ec9 | 386 | #endif |
728ece34 PA |
387 | |
388 | #define CONFIG_SYS_VSC7385_BASE 0xffb00000 | |
389 | ||
e0082f7c PA |
390 | #ifdef CONFIG_PHYS_64BIT |
391 | #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull | |
392 | #else | |
728ece34 | 393 | #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE |
e0082f7c | 394 | #endif |
728ece34 | 395 | |
09f9ee16 PA |
396 | #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE) \ |
397 | | BR_PS_8 | BR_V) | |
728ece34 PA |
398 | #define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ |
399 | OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \ | |
400 | OR_GPCM_EHTR | OR_GPCM_EAD) | |
401 | ||
402 | /* Serial Port - controlled on board with jumper J8 | |
403 | * open - index 2 | |
404 | * shorted - index 1 | |
405 | */ | |
406 | #define CONFIG_CONS_INDEX 1 | |
728ece34 PA |
407 | #define CONFIG_SYS_NS16550 |
408 | #define CONFIG_SYS_NS16550_SERIAL | |
409 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
410 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
bc2d40ca | 411 | #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) |
93341909 KG |
412 | #define CONFIG_NS16550_MIN_FUNCTIONS |
413 | #endif | |
728ece34 | 414 | |
728ece34 PA |
415 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ |
416 | ||
417 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
418 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} | |
419 | ||
420 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) | |
421 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
422 | ||
423 | /* Use the HUSH parser */ | |
424 | #define CONFIG_SYS_HUSH_PARSER | |
728ece34 PA |
425 | |
426 | /* | |
427 | * Pass open firmware flat tree | |
428 | */ | |
429 | #define CONFIG_OF_LIBFDT 1 | |
430 | #define CONFIG_OF_BOARD_SETUP 1 | |
431 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 | |
432 | ||
728ece34 PA |
433 | /* new uImage format support */ |
434 | #define CONFIG_FIT 1 | |
435 | #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ | |
436 | ||
437 | /* I2C */ | |
00f792e0 HS |
438 | #define CONFIG_SYS_I2C |
439 | #define CONFIG_SYS_I2C_FSL | |
440 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
441 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
442 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
443 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
444 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
445 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
446 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } | |
728ece34 PA |
447 | |
448 | /* | |
449 | * I2C2 EEPROM | |
450 | */ | |
451 | #define CONFIG_ID_EEPROM | |
452 | #ifdef CONFIG_ID_EEPROM | |
453 | #define CONFIG_SYS_I2C_EEPROM_NXID | |
454 | #endif | |
b1d67857 | 455 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 |
728ece34 PA |
456 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
457 | #define CONFIG_SYS_EEPROM_BUS_NUM 1 | |
458 | ||
cac29f25 PJ |
459 | #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 |
460 | ||
728ece34 | 461 | #define CONFIG_RTC_DS1337 |
39c2a6eb | 462 | #define CONFIG_SYS_RTC_DS1337_NOOSC |
728ece34 | 463 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 |
c62a6cfb PJ |
464 | |
465 | /* eSPI - Enhanced SPI */ | |
466 | #define CONFIG_FSL_ESPI | |
467 | #define CONFIG_SPI_FLASH | |
468 | #define CONFIG_SPI_FLASH_SPANSION | |
469 | #define CONFIG_CMD_SF | |
470 | #define CONFIG_SF_DEFAULT_SPEED 10000000 | |
471 | #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 | |
472 | ||
728ece34 PA |
473 | /* |
474 | * General PCI | |
475 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
476 | */ | |
477 | ||
b7070904 | 478 | #if defined(CONFIG_PCI) |
b0c5ceb3 | 479 | /* controller 2, Slot 2, tgtid 2, Base address 9000 */ |
06eb4d8c | 480 | #define CONFIG_SYS_PCIE2_NAME "Slot 1" |
728ece34 | 481 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 |
e0082f7c PA |
482 | #ifdef CONFIG_PHYS_64BIT |
483 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 | |
484 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull | |
485 | #else | |
728ece34 PA |
486 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 |
487 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 | |
e0082f7c | 488 | #endif |
728ece34 | 489 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ |
b0c5ceb3 PK |
490 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 |
491 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 | |
e0082f7c PA |
492 | #ifdef CONFIG_PHYS_64BIT |
493 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull | |
494 | #else | |
b0c5ceb3 | 495 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 |
e0082f7c | 496 | #endif |
728ece34 PA |
497 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ |
498 | ||
499 | /* controller 1, Slot 1, tgtid 1, Base address a000 */ | |
06eb4d8c | 500 | #define CONFIG_SYS_PCIE1_NAME "Slot 2" |
b0c5ceb3 | 501 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 |
e0082f7c PA |
502 | #ifdef CONFIG_PHYS_64BIT |
503 | #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 | |
504 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull | |
505 | #else | |
b0c5ceb3 PK |
506 | #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 |
507 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 | |
e0082f7c | 508 | #endif |
728ece34 | 509 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ |
b0c5ceb3 PK |
510 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 |
511 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
e0082f7c PA |
512 | #ifdef CONFIG_PHYS_64BIT |
513 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull | |
514 | #else | |
b0c5ceb3 | 515 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 |
e0082f7c | 516 | #endif |
728ece34 PA |
517 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ |
518 | ||
728ece34 PA |
519 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
520 | ||
521 | #undef CONFIG_EEPRO100 | |
522 | #undef CONFIG_TULIP | |
523 | #undef CONFIG_RTL8139 | |
524 | ||
525 | #ifdef CONFIG_RTL8139 | |
526 | /* This macro is used by RTL8139 but not defined in PPC architecture */ | |
527 | #define KSEG1ADDR(x) (x) | |
528 | #define _IO_BASE 0x00000000 | |
529 | #endif | |
530 | ||
531 | ||
532 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
533 | #define CONFIG_DOS_PARTITION | |
534 | ||
535 | #endif /* CONFIG_PCI */ | |
536 | ||
728ece34 | 537 | |
b7070904 | 538 | #if defined(CONFIG_TSEC_ENET) |
728ece34 PA |
539 | #define CONFIG_MII 1 /* MII PHY management */ |
540 | #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ | |
541 | #define CONFIG_TSEC1 1 | |
542 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
543 | #define CONFIG_TSEC2 1 | |
544 | #define CONFIG_TSEC2_NAME "eTSEC2" | |
545 | #define CONFIG_TSEC3 1 | |
546 | #define CONFIG_TSEC3_NAME "eTSEC3" | |
547 | ||
548 | #define TSEC1_PHY_ADDR 2 | |
549 | #define TSEC2_PHY_ADDR 0 | |
550 | #define TSEC3_PHY_ADDR 1 | |
551 | ||
552 | #define CONFIG_VSC7385_ENET | |
553 | ||
554 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
555 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
556 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
557 | ||
558 | #define TSEC1_PHYIDX 0 | |
559 | #define TSEC2_PHYIDX 0 | |
560 | #define TSEC3_PHYIDX 0 | |
561 | ||
562 | /* Vitesse 7385 */ | |
563 | ||
564 | #ifdef CONFIG_VSC7385_ENET | |
565 | /* The size of the VSC7385 firmware image */ | |
566 | #define CONFIG_VSC7385_IMAGE_SIZE 8192 | |
567 | #endif | |
568 | ||
569 | #define CONFIG_ETHPRIME "eTSEC1" | |
570 | ||
571 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ | |
90b5bf21 | 572 | |
728ece34 PA |
573 | #endif /* CONFIG_TSEC_ENET */ |
574 | ||
575 | /* | |
576 | * Environment | |
577 | */ | |
bc2d40ca PK |
578 | #ifdef CONFIG_SPIFLASH |
579 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
580 | #define CONFIG_ENV_SPI_BUS 0 | |
581 | #define CONFIG_ENV_SPI_CS 0 | |
582 | #define CONFIG_ENV_SPI_MAX_HZ 10000000 | |
583 | #define CONFIG_ENV_SPI_MODE 0 | |
584 | #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ | |
585 | #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ | |
586 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
587 | #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) | |
588 | #elif defined(CONFIG_SDCARD) | |
e59a93e7 | 589 | #define CONFIG_ENV_IS_IN_MMC |
4394d0c2 | 590 | #define CONFIG_FSL_FIXED_MMC_LOCATION |
bc2d40ca PK |
591 | #define CONFIG_ENV_SIZE 0x2000 |
592 | #define CONFIG_SYS_MMC_ENV_DEV 0 | |
593 | #define CONFIG_ENV_OFFSET (512 * 0x800) | |
594 | #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) | |
595 | #elif defined(CONFIG_NAND) | |
596 | #ifdef CONFIG_TPL_BUILD | |
597 | #define CONFIG_ENV_SIZE 0x2000 | |
598 | #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) | |
728ece34 | 599 | #else |
bc2d40ca PK |
600 | #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE |
601 | #endif | |
602 | #define CONFIG_ENV_IS_IN_NAND | |
603 | #define CONFIG_ENV_OFFSET (1024 * 1024) | |
604 | #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) | |
605 | #elif defined(CONFIG_SYS_RAMBOOT) | |
606 | #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ | |
607 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) | |
608 | #define CONFIG_ENV_SIZE 0x2000 | |
609 | #else | |
610 | #define CONFIG_ENV_IS_IN_FLASH | |
611 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) | |
612 | #define CONFIG_ENV_SIZE 0x2000 | |
613 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ | |
728ece34 | 614 | #endif |
728ece34 | 615 | |
bc2d40ca | 616 | |
728ece34 PA |
617 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
618 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
619 | ||
620 | /* | |
621 | * Command line configuration. | |
622 | */ | |
623 | #include <config_cmd_default.h> | |
624 | ||
625 | #define CONFIG_CMD_DATE | |
626 | #define CONFIG_CMD_ELF | |
627 | #define CONFIG_CMD_I2C | |
628 | #define CONFIG_CMD_IRQ | |
629 | #define CONFIG_CMD_MII | |
630 | #define CONFIG_CMD_PING | |
631 | #define CONFIG_CMD_SETEXPR | |
199e262e | 632 | #define CONFIG_CMD_REGINFO |
728ece34 PA |
633 | |
634 | #if defined(CONFIG_PCI) | |
728ece34 PA |
635 | #define CONFIG_CMD_NET |
636 | #define CONFIG_CMD_PCI | |
637 | #endif | |
638 | ||
639 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
640 | ||
641 | #define CONFIG_MMC 1 | |
642 | ||
643 | #ifdef CONFIG_MMC | |
644 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ | |
645 | #define CONFIG_CMD_MMC | |
646 | #define CONFIG_DOS_PARTITION | |
647 | #define CONFIG_FSL_ESDHC | |
648 | #define CONFIG_GENERIC_MMC | |
649 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR | |
650 | #ifdef CONFIG_P2020 | |
651 | #define CONFIG_SYS_FSL_ESDHC_USE_PIO /* P2020 eSDHC DMA is not functional*/ | |
652 | #endif | |
653 | #endif | |
654 | ||
1120ad60 RM |
655 | #define CONFIG_HAS_FSL_DR_USB |
656 | ||
657 | #if defined(CONFIG_HAS_FSL_DR_USB) | |
728ece34 PA |
658 | #define CONFIG_USB_EHCI |
659 | ||
660 | #ifdef CONFIG_USB_EHCI | |
661 | #define CONFIG_CMD_USB | |
662 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
663 | #define CONFIG_USB_EHCI_FSL | |
664 | #define CONFIG_USB_STORAGE | |
1120ad60 | 665 | #endif |
728ece34 PA |
666 | #endif |
667 | ||
668 | #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) | |
669 | #define CONFIG_CMD_EXT2 | |
670 | #define CONFIG_CMD_FAT | |
671 | #define CONFIG_DOS_PARTITION | |
672 | #endif | |
673 | ||
674 | /* | |
675 | * Miscellaneous configurable options | |
676 | */ | |
677 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
678 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ | |
5be58f5f | 679 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
728ece34 | 680 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
728ece34 PA |
681 | #if defined(CONFIG_CMD_KGDB) |
682 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
683 | #else | |
684 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
685 | #endif | |
686 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
687 | /* Print Buffer Size */ | |
688 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
689 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ | |
728ece34 PA |
690 | |
691 | /* | |
692 | * For booting Linux, the board info and command line data | |
a832ac41 | 693 | * have to be in the first 64 MB of memory, since this is |
728ece34 PA |
694 | * the maximum mapped by the Linux kernel during initialization. |
695 | */ | |
a832ac41 KG |
696 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20)/* Initial Memory map for Linux*/ |
697 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
728ece34 | 698 | |
728ece34 PA |
699 | #if defined(CONFIG_CMD_KGDB) |
700 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
728ece34 PA |
701 | #endif |
702 | ||
703 | /* | |
704 | * Environment Configuration | |
705 | */ | |
706 | ||
707 | #if defined(CONFIG_TSEC_ENET) | |
708 | #define CONFIG_HAS_ETH0 | |
709 | #define CONFIG_HAS_ETH1 | |
710 | #define CONFIG_HAS_ETH2 | |
711 | #endif | |
712 | ||
713 | #define CONFIG_HOSTNAME P2020RDB | |
8b3637c6 | 714 | #define CONFIG_ROOTPATH "/opt/nfsroot" |
b3f44c21 | 715 | #define CONFIG_BOOTFILE "uImage" |
728ece34 PA |
716 | #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ |
717 | ||
718 | /* default location for tftp and bootm */ | |
719 | #define CONFIG_LOADADDR 1000000 | |
720 | ||
721 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ | |
722 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ | |
723 | ||
724 | #define CONFIG_BAUDRATE 115200 | |
725 | ||
726 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
727 | "netdev=eth0\0" \ | |
5368c55d MV |
728 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ |
729 | "loadaddr=1000000\0" \ | |
728ece34 | 730 | "tftpflash=tftpboot $loadaddr $uboot; " \ |
5368c55d MV |
731 | "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ |
732 | " +$filesize; " \ | |
733 | "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
734 | " +$filesize; " \ | |
735 | "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
736 | " $filesize; " \ | |
737 | "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
738 | " +$filesize; " \ | |
739 | "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
740 | " $filesize\0" \ | |
728ece34 PA |
741 | "consoledev=ttyS0\0" \ |
742 | "ramdiskaddr=2000000\0" \ | |
743 | "ramdiskfile=rootfs.ext2.gz.uboot\0" \ | |
744 | "fdtaddr=c00000\0" \ | |
745 | "fdtfile=p2020rdb.dtb\0" \ | |
746 | "bdev=sda1\0" \ | |
747 | "jffs2nor=mtdblock3\0" \ | |
748 | "norbootaddr=ef080000\0" \ | |
749 | "norfdtaddr=ef040000\0" \ | |
750 | "jffs2nand=mtdblock9\0" \ | |
751 | "nandbootaddr=100000\0" \ | |
752 | "nandfdtaddr=80000\0" \ | |
753 | "nandimgsize=400000\0" \ | |
754 | "nandfdtsize=80000\0" \ | |
68d4230c | 755 | "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \ |
728ece34 PA |
756 | "vscfw_addr=ef000000\0" \ |
757 | "othbootargs=ramdisk_size=600000\0" \ | |
758 | "usbfatboot=setenv bootargs root=/dev/ram rw " \ | |
759 | "console=$consoledev,$baudrate $othbootargs; " \ | |
760 | "usb start;" \ | |
761 | "fatload usb 0:2 $loadaddr $bootfile;" \ | |
762 | "fatload usb 0:2 $fdtaddr $fdtfile;" \ | |
763 | "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ | |
764 | "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ | |
765 | "usbext2boot=setenv bootargs root=/dev/ram rw " \ | |
766 | "console=$consoledev,$baudrate $othbootargs; " \ | |
767 | "usb start;" \ | |
768 | "ext2load usb 0:4 $loadaddr $bootfile;" \ | |
769 | "ext2load usb 0:4 $fdtaddr $fdtfile;" \ | |
770 | "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ | |
771 | "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ | |
772 | "norboot=setenv bootargs root=/dev/$jffs2nor rw " \ | |
773 | "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ | |
774 | "bootm $norbootaddr - $norfdtaddr\0" \ | |
775 | "nandboot=setenv bootargs root=/dev/$jffs2nand rw rootfstype=jffs2 " \ | |
776 | "console=$consoledev,$baudrate $othbootargs;" \ | |
777 | "nand read 2000000 $nandbootaddr $nandimgsize;" \ | |
778 | "nand read 3000000 $nandfdtaddr $nandfdtsize;" \ | |
779 | "bootm 2000000 - 3000000;\0" | |
780 | ||
781 | #define CONFIG_NFSBOOTCOMMAND \ | |
782 | "setenv bootargs root=/dev/nfs rw " \ | |
783 | "nfsroot=$serverip:$rootpath " \ | |
784 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
785 | "console=$consoledev,$baudrate $othbootargs;" \ | |
786 | "tftp $loadaddr $bootfile;" \ | |
787 | "tftp $fdtaddr $fdtfile;" \ | |
788 | "bootm $loadaddr - $fdtaddr" | |
789 | ||
790 | #define CONFIG_HDBOOT \ | |
791 | "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ | |
792 | "console=$consoledev,$baudrate $othbootargs;" \ | |
793 | "usb start;" \ | |
794 | "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ | |
795 | "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ | |
796 | "bootm $loadaddr - $fdtaddr" | |
797 | ||
798 | #define CONFIG_RAMBOOTCOMMAND \ | |
799 | "setenv bootargs root=/dev/ram rw " \ | |
800 | "console=$consoledev,$baudrate $othbootargs; " \ | |
801 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
802 | "tftp $loadaddr $bootfile;" \ | |
803 | "tftp $fdtaddr $fdtfile;" \ | |
804 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
805 | ||
806 | #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT | |
807 | ||
808 | #endif /* __CONFIG_H */ |