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728ece34 PA |
1 | /* |
2 | * Copyright 2009 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * See file CREDITS for list of people who contributed to this | |
5 | * project. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
20 | * MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | /* | |
24 | * P1 P2 RDB board configuration file | |
25 | * This file is intended to address a set of Low End and Ultra Low End | |
26 | * Freescale SOCs of QorIQ series(RDB platforms). | |
27 | * Currently only P2020RDB | |
28 | */ | |
29 | ||
30 | #ifndef __CONFIG_H | |
31 | #define __CONFIG_H | |
32 | ||
62ca21c4 KG |
33 | #ifdef CONFIG_MK_P1011RDB |
34 | #define CONFIG_P1011 | |
35 | #endif | |
36 | #ifdef CONFIG_MK_P1020RDB | |
37 | #define CONFIG_P1020 | |
38 | #endif | |
39 | #ifdef CONFIG_MK_P2010RDB | |
40 | #define CONFIG_P2010 | |
41 | #endif | |
42 | #ifdef CONFIG_MK_P2020RDB | |
43 | #define CONFIG_P2020 | |
44 | #endif | |
45 | ||
f7780ec9 DD |
46 | #ifdef CONFIG_MK_NAND |
47 | #define CONFIG_NAND_U_BOOT 1 | |
48 | #define CONFIG_RAMBOOT_NAND 1 | |
49 | #define CONFIG_RAMBOOT_TEXT_BASE 0xf8f82000 | |
50 | #endif | |
51 | ||
fad15096 DD |
52 | #ifdef CONFIG_MK_SDCARD |
53 | #define CONFIG_RAMBOOT_SDCARD 1 | |
54 | #define CONFIG_RAMBOOT_TEXT_BASE 0xf8f80000 | |
55 | #endif | |
56 | ||
57 | #ifdef CONFIG_MK_SPIFLASH | |
58 | #define CONFIG_RAMBOOT_SPIFLASH 1 | |
59 | #define CONFIG_RAMBOOT_TEXT_BASE 0xf8f80000 | |
60 | #endif | |
61 | ||
728ece34 PA |
62 | /* High Level Configuration Options */ |
63 | #define CONFIG_BOOKE 1 /* BOOKE */ | |
64 | #define CONFIG_E500 1 /* BOOKE e500 family */ | |
65 | #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/P1020/P2020,etc*/ | |
66 | #define CONFIG_FSL_ELBC 1 /* Enable eLBC Support */ | |
33f3f342 PA |
67 | #define CONFIG_PCI 1 /* Enable PCI/PCIE */ |
68 | #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ | |
69 | #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ | |
70 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ | |
71 | #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ | |
72 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ | |
728ece34 PA |
73 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ |
74 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ | |
75 | #define CONFIG_ENV_OVERWRITE | |
76 | ||
77 | #ifndef __ASSEMBLY__ | |
78 | extern unsigned long get_board_sys_clk(unsigned long dummy); | |
79 | #endif | |
80 | #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1_P2 RDB */ | |
81 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /*sysclk for P1_P2 RDB */ | |
82 | ||
83 | #if defined(CONFIG_P2020) || defined(CONFIG_P1020) | |
84 | #define CONFIG_MP | |
85 | #endif | |
86 | ||
525f6c3a PA |
87 | #define CONFIG_HWCONFIG |
88 | ||
728ece34 PA |
89 | /* |
90 | * These can be toggled for performance analysis, otherwise use default. | |
91 | */ | |
92 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
93 | #define CONFIG_BTB /* toggle branch predition */ | |
94 | ||
95 | #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ | |
96 | ||
97 | #define CONFIG_ENABLE_36BIT_PHYS 1 | |
98 | ||
99 | #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ | |
100 | #define CONFIG_SYS_MEMTEST_END 0x1fffffff | |
101 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ | |
102 | ||
f7780ec9 DD |
103 | /* |
104 | * Config the L2 Cache as L2 SRAM | |
105 | */ | |
106 | #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 | |
107 | #ifdef CONFIG_PHYS_64BIT | |
108 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull | |
109 | #else | |
110 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR | |
111 | #endif | |
112 | #define CONFIG_SYS_L2_SIZE (512 << 10) | |
113 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) | |
114 | ||
728ece34 PA |
115 | /* |
116 | * Base addresses -- Note these are effective addresses where the | |
117 | * actual resources get mapped (not physical addresses) | |
118 | */ | |
728ece34 PA |
119 | #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ |
120 | #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of */ | |
121 | /* CCSRBAR */ | |
122 | #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */ | |
123 | /* CONFIG_SYS_IMMR */ | |
f7780ec9 DD |
124 | |
125 | #if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL) | |
126 | #define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR | |
127 | #else | |
128 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ | |
129 | #endif | |
130 | ||
728ece34 PA |
131 | #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) |
132 | #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) | |
133 | ||
134 | /* DDR Setup */ | |
135 | #define CONFIG_FSL_DDR2 | |
136 | #undef CONFIG_FSL_DDR_INTERACTIVE | |
137 | #undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ | |
138 | #undef CONFIG_DDR_DLL | |
139 | ||
140 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
141 | ||
142 | #define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR size on P1_P2 RDBs */ | |
143 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
144 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
145 | ||
146 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
147 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
148 | #define CONFIG_CHIP_SELECTS_PER_CTRL 1 | |
149 | ||
150 | #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d | |
151 | #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 | |
152 | #define CONFIG_SYS_DDR_SBE 0x00FF0000 | |
153 | ||
728ece34 PA |
154 | /* |
155 | * Memory map | |
156 | * | |
157 | * 0x0000_0000 0x3fff_ffff DDR 1G cacheablen | |
158 | * 0xa000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable | |
159 | * 0xffc2_0000 0xffc5_ffff PCI IO range 256K non-cacheable | |
160 | * | |
161 | * Localbus cacheable (TBD) | |
162 | * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable | |
163 | * | |
164 | * Localbus non-cacheable | |
165 | * 0xef00_0000 0xefff_ffff FLASH 16M non-cacheable | |
166 | * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable | |
167 | * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable | |
168 | * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 | |
169 | * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable | |
170 | */ | |
171 | ||
172 | /* | |
173 | * Local Bus Definitions | |
174 | */ | |
175 | #define CONFIG_SYS_FLASH_BASE 0xef000000 /* start of FLASH 16M */ | |
176 | ||
177 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE | |
178 | ||
179 | #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ | |
180 | BR_PS_16 | BR_V) | |
181 | #define CONFIG_FLASH_OR_PRELIM 0xff000ff7 | |
182 | ||
183 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} | |
184 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
185 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
186 | ||
187 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
188 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ | |
189 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
190 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
191 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
192 | ||
193 | #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ | |
194 | ||
fad15096 DD |
195 | #if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) \ |
196 | || defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) | |
f7780ec9 DD |
197 | #define CONFIG_SYS_RAMBOOT |
198 | #else | |
199 | #undef CONFIG_SYS_RAMBOOT | |
200 | #endif | |
201 | ||
728ece34 PA |
202 | #define CONFIG_FLASH_CFI_DRIVER |
203 | #define CONFIG_SYS_FLASH_CFI | |
204 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
205 | #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 | |
206 | ||
207 | #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ | |
66e821eb | 208 | #define CONFIG_HWCONFIG |
728ece34 PA |
209 | |
210 | #define CONFIG_SYS_INIT_RAM_LOCK 1 | |
211 | #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ | |
212 | #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ | |
213 | ||
214 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ | |
215 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \ | |
216 | - CONFIG_SYS_GBL_DATA_SIZE) | |
217 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
218 | ||
219 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/ | |
220 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ | |
221 | ||
f7780ec9 | 222 | #ifndef CONFIG_NAND_SPL |
728ece34 | 223 | #define CONFIG_SYS_NAND_BASE 0xffa00000 |
f7780ec9 DD |
224 | #else |
225 | #define CONFIG_SYS_NAND_BASE 0xfff00000 | |
226 | #endif | |
728ece34 PA |
227 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE |
228 | #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} | |
229 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
230 | #define NAND_MAX_CHIPS 1 | |
231 | #define CONFIG_MTD_NAND_VERIFY_WRITE | |
232 | #define CONFIG_CMD_NAND 1 | |
233 | #define CONFIG_NAND_FSL_ELBC 1 | |
234 | #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) | |
235 | ||
f7780ec9 DD |
236 | /* NAND boot: 4K NAND loader config */ |
237 | #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 | |
238 | #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) | |
239 | #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) | |
240 | #define CONFIG_SYS_NAND_U_BOOT_START (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) | |
241 | #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) | |
242 | #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) | |
243 | #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) | |
244 | ||
728ece34 PA |
245 | /* NAND flash config */ |
246 | #define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \ | |
247 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | |
248 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
249 | | BR_MS_FCM /* MSEL = FCM */ \ | |
250 | | BR_V) /* valid */ | |
251 | ||
252 | #define CONFIG_NAND_OR_PRELIM (0xFFF80000 /* length 32K */ \ | |
253 | | OR_FCM_CSCT \ | |
254 | | OR_FCM_CST \ | |
255 | | OR_FCM_CHT \ | |
256 | | OR_FCM_SCY_1 \ | |
257 | | OR_FCM_TRLX \ | |
258 | | OR_FCM_EHTR) | |
259 | ||
f7780ec9 DD |
260 | #ifdef CONFIG_RAMBOOT_NAND |
261 | #define CONFIG_SYS_BR0_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ | |
262 | #define CONFIG_SYS_OR0_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ | |
263 | #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ | |
264 | #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ | |
265 | #else | |
728ece34 PA |
266 | #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ |
267 | #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ | |
268 | #define CONFIG_SYS_BR1_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ | |
269 | #define CONFIG_SYS_OR1_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ | |
f7780ec9 | 270 | #endif |
728ece34 PA |
271 | |
272 | #define CONFIG_SYS_VSC7385_BASE 0xffb00000 | |
273 | ||
274 | #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE | |
275 | ||
276 | #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE | BR_PS_8 | BR_V) | |
277 | #define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ | |
278 | OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \ | |
279 | OR_GPCM_EHTR | OR_GPCM_EAD) | |
280 | ||
281 | /* Serial Port - controlled on board with jumper J8 | |
282 | * open - index 2 | |
283 | * shorted - index 1 | |
284 | */ | |
285 | #define CONFIG_CONS_INDEX 1 | |
728ece34 PA |
286 | #undef CONFIG_SERIAL_SOFTWARE_FIFO |
287 | #define CONFIG_SYS_NS16550 | |
288 | #define CONFIG_SYS_NS16550_SERIAL | |
289 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
290 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
93341909 KG |
291 | #ifdef CONFIG_NAND_SPL |
292 | #define CONFIG_NS16550_MIN_FUNCTIONS | |
293 | #endif | |
728ece34 PA |
294 | |
295 | #define CONFIG_SERIAL_MULTI 1 /* Enable both serial ports */ | |
296 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ | |
297 | ||
298 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
299 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} | |
300 | ||
301 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) | |
302 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
303 | ||
304 | /* Use the HUSH parser */ | |
305 | #define CONFIG_SYS_HUSH_PARSER | |
306 | #ifdef CONFIG_SYS_HUSH_PARSER | |
307 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
308 | #endif | |
309 | ||
310 | /* | |
311 | * Pass open firmware flat tree | |
312 | */ | |
313 | #define CONFIG_OF_LIBFDT 1 | |
314 | #define CONFIG_OF_BOARD_SETUP 1 | |
315 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 | |
316 | ||
728ece34 PA |
317 | /* new uImage format support */ |
318 | #define CONFIG_FIT 1 | |
319 | #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ | |
320 | ||
321 | /* I2C */ | |
322 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
323 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
324 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
325 | #define CONFIG_I2C_MULTI_BUS | |
326 | #define CONFIG_I2C_CMD_TREE | |
327 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address*/ | |
328 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 | |
329 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
330 | #define CONFIG_SYS_I2C_NOPROBES {{0,0x29}} /* Don't probe these addrs */ | |
331 | #define CONFIG_SYS_I2C_OFFSET 0x3000 | |
332 | #define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
333 | ||
334 | /* | |
335 | * I2C2 EEPROM | |
336 | */ | |
337 | #define CONFIG_ID_EEPROM | |
338 | #ifdef CONFIG_ID_EEPROM | |
339 | #define CONFIG_SYS_I2C_EEPROM_NXID | |
340 | #endif | |
341 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 | |
342 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
343 | #define CONFIG_SYS_EEPROM_BUS_NUM 1 | |
344 | ||
345 | #define CONFIG_RTC_DS1337 | |
346 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 | |
347 | /* | |
348 | * General PCI | |
349 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
350 | */ | |
351 | ||
352 | /* controller 2, Slot 2, tgtid 2, Base address 9000 */ | |
353 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 | |
354 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 | |
355 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 | |
356 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ | |
357 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000 | |
358 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 | |
359 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000 | |
360 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ | |
361 | ||
362 | /* controller 1, Slot 1, tgtid 1, Base address a000 */ | |
363 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 | |
364 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 | |
365 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 | |
366 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ | |
367 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc30000 | |
368 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
369 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc30000 | |
370 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ | |
371 | ||
372 | #if defined(CONFIG_PCI) | |
373 | #define CONFIG_NET_MULTI | |
374 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
375 | ||
376 | #undef CONFIG_EEPRO100 | |
377 | #undef CONFIG_TULIP | |
378 | #undef CONFIG_RTL8139 | |
379 | ||
380 | #ifdef CONFIG_RTL8139 | |
381 | /* This macro is used by RTL8139 but not defined in PPC architecture */ | |
382 | #define KSEG1ADDR(x) (x) | |
383 | #define _IO_BASE 0x00000000 | |
384 | #endif | |
385 | ||
386 | ||
387 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
388 | #define CONFIG_DOS_PARTITION | |
389 | ||
390 | #endif /* CONFIG_PCI */ | |
391 | ||
392 | #if defined(CONFIG_TSEC_ENET) | |
393 | #ifndef CONFIG_NET_MULTI | |
394 | #define CONFIG_NET_MULTI 1 | |
395 | #endif | |
396 | ||
397 | #define CONFIG_MII 1 /* MII PHY management */ | |
398 | #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ | |
399 | #define CONFIG_TSEC1 1 | |
400 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
401 | #define CONFIG_TSEC2 1 | |
402 | #define CONFIG_TSEC2_NAME "eTSEC2" | |
403 | #define CONFIG_TSEC3 1 | |
404 | #define CONFIG_TSEC3_NAME "eTSEC3" | |
405 | ||
406 | #define TSEC1_PHY_ADDR 2 | |
407 | #define TSEC2_PHY_ADDR 0 | |
408 | #define TSEC3_PHY_ADDR 1 | |
409 | ||
410 | #define CONFIG_VSC7385_ENET | |
411 | ||
412 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
413 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
414 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
415 | ||
416 | #define TSEC1_PHYIDX 0 | |
417 | #define TSEC2_PHYIDX 0 | |
418 | #define TSEC3_PHYIDX 0 | |
419 | ||
420 | /* Vitesse 7385 */ | |
421 | ||
422 | #ifdef CONFIG_VSC7385_ENET | |
423 | /* The size of the VSC7385 firmware image */ | |
424 | #define CONFIG_VSC7385_IMAGE_SIZE 8192 | |
425 | #endif | |
426 | ||
427 | #define CONFIG_ETHPRIME "eTSEC1" | |
428 | ||
429 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ | |
90b5bf21 FR |
430 | |
431 | /* TBI PHY configuration for SGMII mode */ | |
432 | #define CONFIG_TSEC_TBICR_SETTINGS ( \ | |
433 | TBICR_PHY_RESET \ | |
434 | | TBICR_ANEG_ENABLE \ | |
435 | | TBICR_FULL_DUPLEX \ | |
436 | | TBICR_SPEED1_SET \ | |
437 | ) | |
438 | ||
728ece34 PA |
439 | #endif /* CONFIG_TSEC_ENET */ |
440 | ||
441 | /* | |
442 | * Environment | |
443 | */ | |
f7780ec9 DD |
444 | #if defined(CONFIG_SYS_RAMBOOT) |
445 | #if defined(CONFIG_RAMBOOT_NAND) | |
446 | #define CONFIG_ENV_IS_IN_NAND 1 | |
447 | #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE | |
448 | #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) | |
fad15096 DD |
449 | #elif defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) |
450 | #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ | |
451 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) | |
452 | #define CONFIG_ENV_SIZE 0x2000 | |
f7780ec9 | 453 | #endif |
728ece34 | 454 | #else |
f7780ec9 DD |
455 | #define CONFIG_ENV_IS_IN_FLASH 1 |
456 | #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 | |
457 | #define CONFIG_ENV_ADDR 0xfff80000 | |
458 | #else | |
459 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) | |
460 | #endif | |
461 | #define CONFIG_ENV_SIZE 0x2000 | |
462 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ | |
728ece34 | 463 | #endif |
728ece34 PA |
464 | |
465 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
466 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
467 | ||
468 | /* | |
469 | * Command line configuration. | |
470 | */ | |
471 | #include <config_cmd_default.h> | |
472 | ||
473 | #define CONFIG_CMD_DATE | |
474 | #define CONFIG_CMD_ELF | |
475 | #define CONFIG_CMD_I2C | |
476 | #define CONFIG_CMD_IRQ | |
477 | #define CONFIG_CMD_MII | |
478 | #define CONFIG_CMD_PING | |
479 | #define CONFIG_CMD_SETEXPR | |
199e262e | 480 | #define CONFIG_CMD_REGINFO |
728ece34 PA |
481 | |
482 | #if defined(CONFIG_PCI) | |
728ece34 PA |
483 | #define CONFIG_CMD_NET |
484 | #define CONFIG_CMD_PCI | |
485 | #endif | |
486 | ||
487 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
488 | ||
489 | #define CONFIG_MMC 1 | |
490 | ||
491 | #ifdef CONFIG_MMC | |
492 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ | |
493 | #define CONFIG_CMD_MMC | |
494 | #define CONFIG_DOS_PARTITION | |
495 | #define CONFIG_FSL_ESDHC | |
496 | #define CONFIG_GENERIC_MMC | |
497 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR | |
498 | #ifdef CONFIG_P2020 | |
499 | #define CONFIG_SYS_FSL_ESDHC_USE_PIO /* P2020 eSDHC DMA is not functional*/ | |
500 | #endif | |
501 | #endif | |
502 | ||
503 | #define CONFIG_USB_EHCI | |
504 | ||
505 | #ifdef CONFIG_USB_EHCI | |
506 | #define CONFIG_CMD_USB | |
507 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
508 | #define CONFIG_USB_EHCI_FSL | |
509 | #define CONFIG_USB_STORAGE | |
510 | #endif | |
511 | ||
512 | #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) | |
513 | #define CONFIG_CMD_EXT2 | |
514 | #define CONFIG_CMD_FAT | |
515 | #define CONFIG_DOS_PARTITION | |
516 | #endif | |
517 | ||
518 | /* | |
519 | * Miscellaneous configurable options | |
520 | */ | |
521 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
522 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ | |
523 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
524 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
525 | #if defined(CONFIG_CMD_KGDB) | |
526 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
527 | #else | |
528 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
529 | #endif | |
530 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
531 | /* Print Buffer Size */ | |
532 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
533 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ | |
534 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ | |
535 | ||
536 | /* | |
537 | * For booting Linux, the board info and command line data | |
538 | * have to be in the first 16 MB of memory, since this is | |
539 | * the maximum mapped by the Linux kernel during initialization. | |
540 | */ | |
541 | #define CONFIG_SYS_BOOTMAPSZ (16 << 20)/* Initial Memory map for Linux*/ | |
542 | ||
543 | /* | |
544 | * Internal Definitions | |
545 | * | |
546 | * Boot Flags | |
547 | */ | |
548 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
549 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
550 | ||
551 | #if defined(CONFIG_CMD_KGDB) | |
552 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
553 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
554 | #endif | |
555 | ||
556 | /* | |
557 | * Environment Configuration | |
558 | */ | |
559 | ||
560 | #if defined(CONFIG_TSEC_ENET) | |
561 | #define CONFIG_HAS_ETH0 | |
562 | #define CONFIG_HAS_ETH1 | |
563 | #define CONFIG_HAS_ETH2 | |
564 | #endif | |
565 | ||
566 | #define CONFIG_HOSTNAME P2020RDB | |
567 | #define CONFIG_ROOTPATH /opt/nfsroot | |
568 | #define CONFIG_BOOTFILE uImage | |
569 | #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ | |
570 | ||
571 | /* default location for tftp and bootm */ | |
572 | #define CONFIG_LOADADDR 1000000 | |
573 | ||
574 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ | |
575 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ | |
576 | ||
577 | #define CONFIG_BAUDRATE 115200 | |
578 | ||
579 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
580 | "netdev=eth0\0" \ | |
581 | "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ | |
582 | "loadaddr=1000000\0" \ | |
728ece34 PA |
583 | "tftpflash=tftpboot $loadaddr $uboot; " \ |
584 | "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ | |
585 | "erase " MK_STR(TEXT_BASE) " +$filesize; " \ | |
586 | "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ | |
587 | "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ | |
588 | "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ | |
589 | "consoledev=ttyS0\0" \ | |
590 | "ramdiskaddr=2000000\0" \ | |
591 | "ramdiskfile=rootfs.ext2.gz.uboot\0" \ | |
592 | "fdtaddr=c00000\0" \ | |
593 | "fdtfile=p2020rdb.dtb\0" \ | |
594 | "bdev=sda1\0" \ | |
595 | "jffs2nor=mtdblock3\0" \ | |
596 | "norbootaddr=ef080000\0" \ | |
597 | "norfdtaddr=ef040000\0" \ | |
598 | "jffs2nand=mtdblock9\0" \ | |
599 | "nandbootaddr=100000\0" \ | |
600 | "nandfdtaddr=80000\0" \ | |
601 | "nandimgsize=400000\0" \ | |
602 | "nandfdtsize=80000\0" \ | |
603 | "usb_phy_type=ulpi\0" \ | |
604 | "vscfw_addr=ef000000\0" \ | |
605 | "othbootargs=ramdisk_size=600000\0" \ | |
606 | "usbfatboot=setenv bootargs root=/dev/ram rw " \ | |
607 | "console=$consoledev,$baudrate $othbootargs; " \ | |
608 | "usb start;" \ | |
609 | "fatload usb 0:2 $loadaddr $bootfile;" \ | |
610 | "fatload usb 0:2 $fdtaddr $fdtfile;" \ | |
611 | "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ | |
612 | "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ | |
613 | "usbext2boot=setenv bootargs root=/dev/ram rw " \ | |
614 | "console=$consoledev,$baudrate $othbootargs; " \ | |
615 | "usb start;" \ | |
616 | "ext2load usb 0:4 $loadaddr $bootfile;" \ | |
617 | "ext2load usb 0:4 $fdtaddr $fdtfile;" \ | |
618 | "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ | |
619 | "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ | |
620 | "norboot=setenv bootargs root=/dev/$jffs2nor rw " \ | |
621 | "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ | |
622 | "bootm $norbootaddr - $norfdtaddr\0" \ | |
623 | "nandboot=setenv bootargs root=/dev/$jffs2nand rw rootfstype=jffs2 " \ | |
624 | "console=$consoledev,$baudrate $othbootargs;" \ | |
625 | "nand read 2000000 $nandbootaddr $nandimgsize;" \ | |
626 | "nand read 3000000 $nandfdtaddr $nandfdtsize;" \ | |
627 | "bootm 2000000 - 3000000;\0" | |
628 | ||
629 | #define CONFIG_NFSBOOTCOMMAND \ | |
630 | "setenv bootargs root=/dev/nfs rw " \ | |
631 | "nfsroot=$serverip:$rootpath " \ | |
632 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
633 | "console=$consoledev,$baudrate $othbootargs;" \ | |
634 | "tftp $loadaddr $bootfile;" \ | |
635 | "tftp $fdtaddr $fdtfile;" \ | |
636 | "bootm $loadaddr - $fdtaddr" | |
637 | ||
638 | #define CONFIG_HDBOOT \ | |
639 | "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ | |
640 | "console=$consoledev,$baudrate $othbootargs;" \ | |
641 | "usb start;" \ | |
642 | "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ | |
643 | "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ | |
644 | "bootm $loadaddr - $fdtaddr" | |
645 | ||
646 | #define CONFIG_RAMBOOTCOMMAND \ | |
647 | "setenv bootargs root=/dev/ram rw " \ | |
648 | "console=$consoledev,$baudrate $othbootargs; " \ | |
649 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
650 | "tftp $loadaddr $bootfile;" \ | |
651 | "tftp $fdtaddr $fdtfile;" \ | |
652 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
653 | ||
654 | #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT | |
655 | ||
656 | #endif /* __CONFIG_H */ |