projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 728ece34 | 1 | /* |
| 7c57f3e8 | 2 | * Copyright 2009-2011 Freescale Semiconductor, Inc. |
| 728ece34 PA |
3 | * |
| 4 | * See file CREDITS for list of people who contributed to this | |
| 5 | * project. | |
| 6 | * | |
| 7 | * This program is free software; you can redistribute it and/or | |
| 8 | * modify it under the terms of the GNU General Public License as | |
| 9 | * published by the Free Software Foundation; either version 2 of | |
| 10 | * the License, or (at your option) any later version. | |
| 11 | * | |
| 12 | * This program is distributed in the hope that it will be useful, | |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the | |
| 15 | * GNU General Public License for more details. | |
| 16 | * | |
| 17 | * You should have received a copy of the GNU General Public License | |
| 18 | * along with this program; if not, write to the Free Software | |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 20 | * MA 02111-1307 USA | |
| 21 | */ | |
| 22 | ||
| 23 | /* | |
| 24 | * P1 P2 RDB board configuration file | |
| 25 | * This file is intended to address a set of Low End and Ultra Low End | |
| 26 | * Freescale SOCs of QorIQ series(RDB platforms). | |
| 27 | * Currently only P2020RDB | |
| 28 | */ | |
| 29 | ||
| 30 | #ifndef __CONFIG_H | |
| 31 | #define __CONFIG_H | |
| 32 | ||
| e0082f7c PA |
33 | #ifdef CONFIG_36BIT |
| 34 | #define CONFIG_PHYS_64BIT | |
| 35 | #endif | |
| 36 | ||
| d24f2d32 | 37 | #ifdef CONFIG_P1011RDB |
| 62ca21c4 KG |
38 | #define CONFIG_P1011 |
| 39 | #endif | |
| d24f2d32 | 40 | #ifdef CONFIG_P1020RDB |
| 62ca21c4 KG |
41 | #define CONFIG_P1020 |
| 42 | #endif | |
| d24f2d32 | 43 | #ifdef CONFIG_P2010RDB |
| 62ca21c4 KG |
44 | #define CONFIG_P2010 |
| 45 | #endif | |
| d24f2d32 | 46 | #ifdef CONFIG_P2020RDB |
| 62ca21c4 KG |
47 | #define CONFIG_P2020 |
| 48 | #endif | |
| 49 | ||
| d24f2d32 | 50 | #ifdef CONFIG_NAND |
| f7780ec9 DD |
51 | #define CONFIG_NAND_U_BOOT 1 |
| 52 | #define CONFIG_RAMBOOT_NAND 1 | |
| 96196a1f HW |
53 | #ifdef CONFIG_NAND_SPL |
| 54 | #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 | |
| 55 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ | |
| 56 | #else | |
| 00203c64 | 57 | #define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds |
| 2ae18241 | 58 | #define CONFIG_SYS_TEXT_BASE 0xf8f82000 |
| 96196a1f | 59 | #endif /* CONFIG_NAND_SPL */ |
| f7780ec9 DD |
60 | #endif |
| 61 | ||
| d24f2d32 | 62 | #ifdef CONFIG_SDCARD |
| fad15096 | 63 | #define CONFIG_RAMBOOT_SDCARD 1 |
| 0c871e95 PJ |
64 | #define CONFIG_SYS_TEXT_BASE 0x11000000 |
| 65 | #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc | |
| fad15096 DD |
66 | #endif |
| 67 | ||
| d24f2d32 | 68 | #ifdef CONFIG_SPIFLASH |
| fad15096 | 69 | #define CONFIG_RAMBOOT_SPIFLASH 1 |
| 0c871e95 PJ |
70 | #define CONFIG_SYS_TEXT_BASE 0x11000000 |
| 71 | #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc | |
| 2ae18241 WD |
72 | #endif |
| 73 | ||
| 74 | #ifndef CONFIG_SYS_TEXT_BASE | |
| 75 | #define CONFIG_SYS_TEXT_BASE 0xeff80000 | |
| fad15096 DD |
76 | #endif |
| 77 | ||
| 7a577fda KG |
78 | #ifndef CONFIG_RESET_VECTOR_ADDRESS |
| 79 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc | |
| 80 | #endif | |
| 81 | ||
| 96196a1f HW |
82 | #ifndef CONFIG_SYS_MONITOR_BASE |
| 83 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ | |
| 84 | #endif | |
| 85 | ||
| 728ece34 PA |
86 | /* High Level Configuration Options */ |
| 87 | #define CONFIG_BOOKE 1 /* BOOKE */ | |
| 88 | #define CONFIG_E500 1 /* BOOKE e500 family */ | |
| 89 | #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/P1020/P2020,etc*/ | |
| 90 | #define CONFIG_FSL_ELBC 1 /* Enable eLBC Support */ | |
| b7070904 | 91 | |
| 33f3f342 | 92 | #define CONFIG_PCI 1 /* Enable PCI/PCIE */ |
| b7070904 | 93 | #if defined(CONFIG_PCI) |
| 33f3f342 PA |
94 | #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ |
| 95 | #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ | |
| 96 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ | |
| 97 | #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ | |
| 98 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ | |
| b7070904 | 99 | #endif /* #if defined(CONFIG_PCI) */ |
| 728ece34 PA |
100 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ |
| 101 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ | |
| 102 | #define CONFIG_ENV_OVERWRITE | |
| 103 | ||
| b7070904 | 104 | #if defined(CONFIG_PCI) |
| ddac6f08 | 105 | #define CONFIG_E1000 1 /* E1000 pci Ethernet card*/ |
| b7070904 PK |
106 | #endif |
| 107 | ||
| 728ece34 PA |
108 | #ifndef __ASSEMBLY__ |
| 109 | extern unsigned long get_board_sys_clk(unsigned long dummy); | |
| 110 | #endif | |
| 111 | #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1_P2 RDB */ | |
| 112 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /*sysclk for P1_P2 RDB */ | |
| 113 | ||
| 114 | #if defined(CONFIG_P2020) || defined(CONFIG_P1020) | |
| 115 | #define CONFIG_MP | |
| 116 | #endif | |
| 117 | ||
| 525f6c3a PA |
118 | #define CONFIG_HWCONFIG |
| 119 | ||
| 728ece34 PA |
120 | /* |
| 121 | * These can be toggled for performance analysis, otherwise use default. | |
| 122 | */ | |
| 123 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
| 124 | #define CONFIG_BTB /* toggle branch predition */ | |
| 125 | ||
| 126 | #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ | |
| 127 | ||
| 128 | #define CONFIG_ENABLE_36BIT_PHYS 1 | |
| 129 | ||
| e0082f7c PA |
130 | #ifdef CONFIG_PHYS_64BIT |
| 131 | #define CONFIG_ADDR_MAP 1 | |
| 132 | #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ | |
| 133 | #endif | |
| 134 | ||
| 728ece34 PA |
135 | #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ |
| 136 | #define CONFIG_SYS_MEMTEST_END 0x1fffffff | |
| 137 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ | |
| 138 | ||
| f7780ec9 DD |
139 | /* |
| 140 | * Config the L2 Cache as L2 SRAM | |
| 141 | */ | |
| 142 | #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 | |
| 143 | #ifdef CONFIG_PHYS_64BIT | |
| 144 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull | |
| 145 | #else | |
| 146 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR | |
| 147 | #endif | |
| 148 | #define CONFIG_SYS_L2_SIZE (512 << 10) | |
| 149 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) | |
| 150 | ||
| 728ece34 PA |
151 | /* |
| 152 | * Base addresses -- Note these are effective addresses where the | |
| 153 | * actual resources get mapped (not physical addresses) | |
| 154 | */ | |
| 728ece34 | 155 | #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ |
| e0082f7c PA |
156 | #ifdef CONFIG_PHYS_64BIT |
| 157 | #define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull | |
| 158 | #else | |
| 159 | #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR | |
| 160 | #endif | |
| 728ece34 PA |
161 | /* CCSRBAR */ |
| 162 | #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */ | |
| 163 | /* CONFIG_SYS_IMMR */ | |
| f7780ec9 DD |
164 | |
| 165 | #if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL) | |
| 166 | #define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR | |
| 167 | #else | |
| 168 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ | |
| 169 | #endif | |
| 170 | ||
| 728ece34 PA |
171 | /* DDR Setup */ |
| 172 | #define CONFIG_FSL_DDR2 | |
| 173 | #undef CONFIG_FSL_DDR_INTERACTIVE | |
| 174 | #undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ | |
| 728ece34 PA |
175 | |
| 176 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
| 177 | ||
| 178 | #define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR size on P1_P2 RDBs */ | |
| 179 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
| 180 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
| 181 | ||
| 182 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
| 183 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
| 184 | #define CONFIG_CHIP_SELECTS_PER_CTRL 1 | |
| 185 | ||
| 186 | #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d | |
| 187 | #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 | |
| 188 | #define CONFIG_SYS_DDR_SBE 0x00FF0000 | |
| 189 | ||
| 728ece34 PA |
190 | /* |
| 191 | * Memory map | |
| 192 | * | |
| 193 | * 0x0000_0000 0x3fff_ffff DDR 1G cacheablen | |
| b0c5ceb3 PK |
194 | * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable |
| 195 | * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable | |
| 728ece34 PA |
196 | * |
| 197 | * Localbus cacheable (TBD) | |
| 198 | * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable | |
| 199 | * | |
| 200 | * Localbus non-cacheable | |
| 201 | * 0xef00_0000 0xefff_ffff FLASH 16M non-cacheable | |
| 202 | * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable | |
| 203 | * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable | |
| 204 | * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 | |
| 205 | * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable | |
| 206 | */ | |
| 207 | ||
| 208 | /* | |
| 209 | * Local Bus Definitions | |
| 210 | */ | |
| 211 | #define CONFIG_SYS_FLASH_BASE 0xef000000 /* start of FLASH 16M */ | |
| 212 | ||
| e0082f7c PA |
213 | #ifdef CONFIG_PHYS_64BIT |
| 214 | #define CONFIG_SYS_FLASH_BASE_PHYS 0xfef000000ull | |
| 215 | #else | |
| 728ece34 | 216 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE |
| e0082f7c | 217 | #endif |
| 728ece34 PA |
218 | |
| 219 | #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ | |
| 220 | BR_PS_16 | BR_V) | |
| 221 | #define CONFIG_FLASH_OR_PRELIM 0xff000ff7 | |
| 222 | ||
| e0082f7c | 223 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} |
| 728ece34 PA |
224 | #define CONFIG_SYS_FLASH_QUIET_TEST |
| 225 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
| 226 | ||
| 227 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
| 228 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ | |
| 229 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
| 230 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
| 231 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
| 232 | ||
| a55bb834 KG |
233 | #if defined(CONFIG_RAMBOOT_NAND) || defined(CONFIG_RAMBOOT_SDCARD) || \ |
| 234 | defined(CONFIG_RAMBOOT_SPIFLASH) | |
| f7780ec9 | 235 | #define CONFIG_SYS_RAMBOOT |
| a55bb834 | 236 | #define CONFIG_SYS_EXTRA_ENV_RELOC |
| f7780ec9 DD |
237 | #else |
| 238 | #undef CONFIG_SYS_RAMBOOT | |
| 239 | #endif | |
| 240 | ||
| 728ece34 PA |
241 | #define CONFIG_FLASH_CFI_DRIVER |
| 242 | #define CONFIG_SYS_FLASH_CFI | |
| 243 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
| 244 | #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 | |
| 245 | ||
| 246 | #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ | |
| 2bad42a0 | 247 | #define CONFIG_MISC_INIT_R |
| 66e821eb | 248 | #define CONFIG_HWCONFIG |
| 728ece34 PA |
249 | |
| 250 | #define CONFIG_SYS_INIT_RAM_LOCK 1 | |
| 251 | #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ | |
| e0082f7c PA |
252 | #ifdef CONFIG_PHYS_64BIT |
| 253 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf | |
| 254 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR | |
| 255 | /* The assembler doesn't like typecast */ | |
| 256 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ | |
| 257 | ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ | |
| 258 | CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) | |
| 259 | #else | |
| 260 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ | |
| 261 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 | |
| 262 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS | |
| 263 | #endif | |
| 553f0982 | 264 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ |
| 728ece34 | 265 | |
| 553f0982 | 266 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ |
| 25ddd1fb | 267 | - GENERATED_GBL_DATA_SIZE) |
| 728ece34 PA |
268 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
| 269 | ||
| 270 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/ | |
| 271 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ | |
| 272 | ||
| f7780ec9 | 273 | #ifndef CONFIG_NAND_SPL |
| 728ece34 | 274 | #define CONFIG_SYS_NAND_BASE 0xffa00000 |
| e0082f7c PA |
275 | #ifdef CONFIG_PHYS_64BIT |
| 276 | #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull | |
| f7780ec9 | 277 | #else |
| e0082f7c | 278 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE |
| f7780ec9 | 279 | #endif |
| e0082f7c PA |
280 | #else |
| 281 | #define CONFIG_SYS_NAND_BASE 0xfff00000 | |
| 282 | #ifdef CONFIG_PHYS_64BIT | |
| 283 | #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull | |
| 284 | #else | |
| 728ece34 | 285 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE |
| e0082f7c PA |
286 | #endif |
| 287 | #endif | |
| 288 | ||
| 728ece34 PA |
289 | #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} |
| 290 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
| 291 | #define NAND_MAX_CHIPS 1 | |
| 292 | #define CONFIG_MTD_NAND_VERIFY_WRITE | |
| 293 | #define CONFIG_CMD_NAND 1 | |
| 294 | #define CONFIG_NAND_FSL_ELBC 1 | |
| 295 | #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) | |
| 296 | ||
| f7780ec9 DD |
297 | /* NAND boot: 4K NAND loader config */ |
| 298 | #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 | |
| 299 | #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) | |
| 300 | #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) | |
| 301 | #define CONFIG_SYS_NAND_U_BOOT_START (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) | |
| 302 | #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) | |
| 303 | #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) | |
| 304 | #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) | |
| 305 | ||
| 728ece34 | 306 | /* NAND flash config */ |
| a3055c58 | 307 | #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ |
| 728ece34 PA |
308 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
| 309 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
| 310 | | BR_MS_FCM /* MSEL = FCM */ \ | |
| 311 | | BR_V) /* valid */ | |
| 312 | ||
| a3055c58 | 313 | #define CONFIG_SYS_NAND_OR_PRELIM (0xFFF80000 /* length 32K */ \ |
| 728ece34 PA |
314 | | OR_FCM_CSCT \ |
| 315 | | OR_FCM_CST \ | |
| 316 | | OR_FCM_CHT \ | |
| 317 | | OR_FCM_SCY_1 \ | |
| 318 | | OR_FCM_TRLX \ | |
| 319 | | OR_FCM_EHTR) | |
| 320 | ||
| f7780ec9 | 321 | #ifdef CONFIG_RAMBOOT_NAND |
| a3055c58 MM |
322 | #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ |
| 323 | #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ | |
| f7780ec9 DD |
324 | #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ |
| 325 | #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ | |
| 326 | #else | |
| 728ece34 PA |
327 | #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ |
| 328 | #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ | |
| a3055c58 MM |
329 | #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ |
| 330 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ | |
| f7780ec9 | 331 | #endif |
| 728ece34 PA |
332 | |
| 333 | #define CONFIG_SYS_VSC7385_BASE 0xffb00000 | |
| 334 | ||
| e0082f7c PA |
335 | #ifdef CONFIG_PHYS_64BIT |
| 336 | #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull | |
| 337 | #else | |
| 728ece34 | 338 | #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE |
| e0082f7c | 339 | #endif |
| 728ece34 | 340 | |
| 09f9ee16 PA |
341 | #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE) \ |
| 342 | | BR_PS_8 | BR_V) | |
| 728ece34 PA |
343 | #define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ |
| 344 | OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \ | |
| 345 | OR_GPCM_EHTR | OR_GPCM_EAD) | |
| 346 | ||
| 347 | /* Serial Port - controlled on board with jumper J8 | |
| 348 | * open - index 2 | |
| 349 | * shorted - index 1 | |
| 350 | */ | |
| 351 | #define CONFIG_CONS_INDEX 1 | |
| 728ece34 PA |
352 | #define CONFIG_SYS_NS16550 |
| 353 | #define CONFIG_SYS_NS16550_SERIAL | |
| 354 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
| 355 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
| 93341909 KG |
356 | #ifdef CONFIG_NAND_SPL |
| 357 | #define CONFIG_NS16550_MIN_FUNCTIONS | |
| 358 | #endif | |
| 728ece34 PA |
359 | |
| 360 | #define CONFIG_SERIAL_MULTI 1 /* Enable both serial ports */ | |
| 361 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ | |
| 362 | ||
| 363 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
| 364 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} | |
| 365 | ||
| 366 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) | |
| 367 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
| 368 | ||
| 369 | /* Use the HUSH parser */ | |
| 370 | #define CONFIG_SYS_HUSH_PARSER | |
| 371 | #ifdef CONFIG_SYS_HUSH_PARSER | |
| 372 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
| 373 | #endif | |
| 374 | ||
| 375 | /* | |
| 376 | * Pass open firmware flat tree | |
| 377 | */ | |
| 378 | #define CONFIG_OF_LIBFDT 1 | |
| 379 | #define CONFIG_OF_BOARD_SETUP 1 | |
| 380 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 | |
| 381 | ||
| 728ece34 PA |
382 | /* new uImage format support */ |
| 383 | #define CONFIG_FIT 1 | |
| 384 | #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ | |
| 385 | ||
| 386 | /* I2C */ | |
| 387 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
| 388 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
| 389 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
| 390 | #define CONFIG_I2C_MULTI_BUS | |
| 391 | #define CONFIG_I2C_CMD_TREE | |
| 392 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address*/ | |
| 728ece34 PA |
393 | #define CONFIG_SYS_I2C_SLAVE 0x7F |
| 394 | #define CONFIG_SYS_I2C_NOPROBES {{0,0x29}} /* Don't probe these addrs */ | |
| 395 | #define CONFIG_SYS_I2C_OFFSET 0x3000 | |
| 396 | #define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
| 397 | ||
| 398 | /* | |
| 399 | * I2C2 EEPROM | |
| 400 | */ | |
| 401 | #define CONFIG_ID_EEPROM | |
| 402 | #ifdef CONFIG_ID_EEPROM | |
| 403 | #define CONFIG_SYS_I2C_EEPROM_NXID | |
| 404 | #endif | |
| b1d67857 | 405 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 |
| 728ece34 PA |
406 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
| 407 | #define CONFIG_SYS_EEPROM_BUS_NUM 1 | |
| 408 | ||
| cac29f25 PJ |
409 | #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 |
| 410 | ||
| 728ece34 | 411 | #define CONFIG_RTC_DS1337 |
| 39c2a6eb | 412 | #define CONFIG_SYS_RTC_DS1337_NOOSC |
| 728ece34 | 413 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 |
| c62a6cfb PJ |
414 | |
| 415 | /* eSPI - Enhanced SPI */ | |
| 416 | #define CONFIG_FSL_ESPI | |
| 417 | #define CONFIG_SPI_FLASH | |
| 418 | #define CONFIG_SPI_FLASH_SPANSION | |
| 419 | #define CONFIG_CMD_SF | |
| 420 | #define CONFIG_SF_DEFAULT_SPEED 10000000 | |
| 421 | #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 | |
| 422 | ||
| 728ece34 PA |
423 | /* |
| 424 | * General PCI | |
| 425 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
| 426 | */ | |
| 427 | ||
| b7070904 | 428 | #if defined(CONFIG_PCI) |
| b0c5ceb3 | 429 | /* controller 2, Slot 2, tgtid 2, Base address 9000 */ |
| 06eb4d8c | 430 | #define CONFIG_SYS_PCIE2_NAME "Slot 1" |
| 728ece34 | 431 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 |
| e0082f7c PA |
432 | #ifdef CONFIG_PHYS_64BIT |
| 433 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 | |
| 434 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull | |
| 435 | #else | |
| 728ece34 PA |
436 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 |
| 437 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 | |
| e0082f7c | 438 | #endif |
| 728ece34 | 439 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ |
| b0c5ceb3 PK |
440 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 |
| 441 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 | |
| e0082f7c PA |
442 | #ifdef CONFIG_PHYS_64BIT |
| 443 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull | |
| 444 | #else | |
| b0c5ceb3 | 445 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 |
| e0082f7c | 446 | #endif |
| 728ece34 PA |
447 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ |
| 448 | ||
| 449 | /* controller 1, Slot 1, tgtid 1, Base address a000 */ | |
| 06eb4d8c | 450 | #define CONFIG_SYS_PCIE1_NAME "Slot 2" |
| b0c5ceb3 | 451 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 |
| e0082f7c PA |
452 | #ifdef CONFIG_PHYS_64BIT |
| 453 | #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 | |
| 454 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull | |
| 455 | #else | |
| b0c5ceb3 PK |
456 | #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 |
| 457 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 | |
| e0082f7c | 458 | #endif |
| 728ece34 | 459 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ |
| b0c5ceb3 PK |
460 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 |
| 461 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
| e0082f7c PA |
462 | #ifdef CONFIG_PHYS_64BIT |
| 463 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull | |
| 464 | #else | |
| b0c5ceb3 | 465 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 |
| e0082f7c | 466 | #endif |
| 728ece34 PA |
467 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ |
| 468 | ||
| 728ece34 PA |
469 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
| 470 | ||
| 471 | #undef CONFIG_EEPRO100 | |
| 472 | #undef CONFIG_TULIP | |
| 473 | #undef CONFIG_RTL8139 | |
| 474 | ||
| 475 | #ifdef CONFIG_RTL8139 | |
| 476 | /* This macro is used by RTL8139 but not defined in PPC architecture */ | |
| 477 | #define KSEG1ADDR(x) (x) | |
| 478 | #define _IO_BASE 0x00000000 | |
| 479 | #endif | |
| 480 | ||
| 481 | ||
| 482 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
| 483 | #define CONFIG_DOS_PARTITION | |
| 484 | ||
| 485 | #endif /* CONFIG_PCI */ | |
| 486 | ||
| 728ece34 | 487 | #define CONFIG_NET_MULTI 1 |
| 728ece34 | 488 | |
| b7070904 | 489 | #if defined(CONFIG_TSEC_ENET) |
| 728ece34 PA |
490 | #define CONFIG_MII 1 /* MII PHY management */ |
| 491 | #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ | |
| 492 | #define CONFIG_TSEC1 1 | |
| 493 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
| 494 | #define CONFIG_TSEC2 1 | |
| 495 | #define CONFIG_TSEC2_NAME "eTSEC2" | |
| 496 | #define CONFIG_TSEC3 1 | |
| 497 | #define CONFIG_TSEC3_NAME "eTSEC3" | |
| 498 | ||
| 499 | #define TSEC1_PHY_ADDR 2 | |
| 500 | #define TSEC2_PHY_ADDR 0 | |
| 501 | #define TSEC3_PHY_ADDR 1 | |
| 502 | ||
| 503 | #define CONFIG_VSC7385_ENET | |
| 504 | ||
| 505 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 506 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 507 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 508 | ||
| 509 | #define TSEC1_PHYIDX 0 | |
| 510 | #define TSEC2_PHYIDX 0 | |
| 511 | #define TSEC3_PHYIDX 0 | |
| 512 | ||
| 513 | /* Vitesse 7385 */ | |
| 514 | ||
| 515 | #ifdef CONFIG_VSC7385_ENET | |
| 516 | /* The size of the VSC7385 firmware image */ | |
| 517 | #define CONFIG_VSC7385_IMAGE_SIZE 8192 | |
| 518 | #endif | |
| 519 | ||
| 520 | #define CONFIG_ETHPRIME "eTSEC1" | |
| 521 | ||
| 522 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ | |
| 90b5bf21 | 523 | |
| 728ece34 PA |
524 | #endif /* CONFIG_TSEC_ENET */ |
| 525 | ||
| 526 | /* | |
| 527 | * Environment | |
| 528 | */ | |
| f7780ec9 DD |
529 | #if defined(CONFIG_SYS_RAMBOOT) |
| 530 | #if defined(CONFIG_RAMBOOT_NAND) | |
| 531 | #define CONFIG_ENV_IS_IN_NAND 1 | |
| 532 | #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE | |
| 533 | #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) | |
| e59a93e7 PJ |
534 | #elif defined(CONFIG_RAMBOOT_SDCARD) |
| 535 | #define CONFIG_ENV_IS_IN_MMC | |
| 536 | #define CONFIG_ENV_SIZE 0x2000 | |
| 537 | #define CONFIG_SYS_MMC_ENV_DEV 0 | |
| 538 | #elif defined(CONFIG_RAMBOOT_SPIFLASH) | |
| c62a6cfb PJ |
539 | #define CONFIG_ENV_IS_IN_SPI_FLASH |
| 540 | #define CONFIG_ENV_SPI_BUS 0 | |
| 541 | #define CONFIG_ENV_SPI_CS 0 | |
| 542 | #define CONFIG_ENV_SPI_MAX_HZ 10000000 | |
| 543 | #define CONFIG_ENV_SPI_MODE 0 | |
| 544 | #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ | |
| 545 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
| fad15096 | 546 | #define CONFIG_ENV_SIZE 0x2000 |
| f7780ec9 | 547 | #endif |
| 728ece34 | 548 | #else |
| f7780ec9 DD |
549 | #define CONFIG_ENV_IS_IN_FLASH 1 |
| 550 | #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 | |
| 551 | #define CONFIG_ENV_ADDR 0xfff80000 | |
| 552 | #else | |
| 553 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) | |
| 554 | #endif | |
| 555 | #define CONFIG_ENV_SIZE 0x2000 | |
| 556 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ | |
| 728ece34 | 557 | #endif |
| 728ece34 PA |
558 | |
| 559 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
| 560 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
| 561 | ||
| 562 | /* | |
| 563 | * Command line configuration. | |
| 564 | */ | |
| 565 | #include <config_cmd_default.h> | |
| 566 | ||
| 567 | #define CONFIG_CMD_DATE | |
| 568 | #define CONFIG_CMD_ELF | |
| 569 | #define CONFIG_CMD_I2C | |
| 570 | #define CONFIG_CMD_IRQ | |
| 571 | #define CONFIG_CMD_MII | |
| 572 | #define CONFIG_CMD_PING | |
| 573 | #define CONFIG_CMD_SETEXPR | |
| 199e262e | 574 | #define CONFIG_CMD_REGINFO |
| 728ece34 PA |
575 | |
| 576 | #if defined(CONFIG_PCI) | |
| 728ece34 PA |
577 | #define CONFIG_CMD_NET |
| 578 | #define CONFIG_CMD_PCI | |
| 579 | #endif | |
| 580 | ||
| 581 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
| 582 | ||
| 583 | #define CONFIG_MMC 1 | |
| 584 | ||
| 585 | #ifdef CONFIG_MMC | |
| 586 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ | |
| 587 | #define CONFIG_CMD_MMC | |
| 588 | #define CONFIG_DOS_PARTITION | |
| 589 | #define CONFIG_FSL_ESDHC | |
| 590 | #define CONFIG_GENERIC_MMC | |
| 591 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR | |
| 592 | #ifdef CONFIG_P2020 | |
| 593 | #define CONFIG_SYS_FSL_ESDHC_USE_PIO /* P2020 eSDHC DMA is not functional*/ | |
| 594 | #endif | |
| 595 | #endif | |
| 596 | ||
| 597 | #define CONFIG_USB_EHCI | |
| 598 | ||
| 599 | #ifdef CONFIG_USB_EHCI | |
| 600 | #define CONFIG_CMD_USB | |
| 601 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
| 602 | #define CONFIG_USB_EHCI_FSL | |
| 603 | #define CONFIG_USB_STORAGE | |
| 604 | #endif | |
| 605 | ||
| 606 | #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) | |
| 607 | #define CONFIG_CMD_EXT2 | |
| 608 | #define CONFIG_CMD_FAT | |
| 609 | #define CONFIG_DOS_PARTITION | |
| 610 | #endif | |
| 611 | ||
| 612 | /* | |
| 613 | * Miscellaneous configurable options | |
| 614 | */ | |
| 615 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
| 616 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ | |
| 5be58f5f | 617 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
| 728ece34 PA |
618 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
| 619 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
| 620 | #if defined(CONFIG_CMD_KGDB) | |
| 621 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
| 622 | #else | |
| 623 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
| 624 | #endif | |
| 625 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
| 626 | /* Print Buffer Size */ | |
| 627 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
| 628 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ | |
| 629 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ | |
| 630 | ||
| 631 | /* | |
| 632 | * For booting Linux, the board info and command line data | |
| a832ac41 | 633 | * have to be in the first 64 MB of memory, since this is |
| 728ece34 PA |
634 | * the maximum mapped by the Linux kernel during initialization. |
| 635 | */ | |
| a832ac41 KG |
636 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20)/* Initial Memory map for Linux*/ |
| 637 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
| 728ece34 | 638 | |
| 728ece34 PA |
639 | #if defined(CONFIG_CMD_KGDB) |
| 640 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
| 641 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
| 642 | #endif | |
| 643 | ||
| 644 | /* | |
| 645 | * Environment Configuration | |
| 646 | */ | |
| 647 | ||
| 648 | #if defined(CONFIG_TSEC_ENET) | |
| 649 | #define CONFIG_HAS_ETH0 | |
| 650 | #define CONFIG_HAS_ETH1 | |
| 651 | #define CONFIG_HAS_ETH2 | |
| 652 | #endif | |
| 653 | ||
| 654 | #define CONFIG_HOSTNAME P2020RDB | |
| 655 | #define CONFIG_ROOTPATH /opt/nfsroot | |
| 656 | #define CONFIG_BOOTFILE uImage | |
| 657 | #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ | |
| 658 | ||
| 659 | /* default location for tftp and bootm */ | |
| 660 | #define CONFIG_LOADADDR 1000000 | |
| 661 | ||
| 662 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ | |
| 663 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ | |
| 664 | ||
| 665 | #define CONFIG_BAUDRATE 115200 | |
| 666 | ||
| 667 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 668 | "netdev=eth0\0" \ | |
| 669 | "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ | |
| 670 | "loadaddr=1000000\0" \ | |
| 728ece34 | 671 | "tftpflash=tftpboot $loadaddr $uboot; " \ |
| 14d0a02a WD |
672 | "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ |
| 673 | "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ | |
| 674 | "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \ | |
| 675 | "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ | |
| 676 | "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ | |
| 728ece34 PA |
677 | "consoledev=ttyS0\0" \ |
| 678 | "ramdiskaddr=2000000\0" \ | |
| 679 | "ramdiskfile=rootfs.ext2.gz.uboot\0" \ | |
| 680 | "fdtaddr=c00000\0" \ | |
| 681 | "fdtfile=p2020rdb.dtb\0" \ | |
| 682 | "bdev=sda1\0" \ | |
| 683 | "jffs2nor=mtdblock3\0" \ | |
| 684 | "norbootaddr=ef080000\0" \ | |
| 685 | "norfdtaddr=ef040000\0" \ | |
| 686 | "jffs2nand=mtdblock9\0" \ | |
| 687 | "nandbootaddr=100000\0" \ | |
| 688 | "nandfdtaddr=80000\0" \ | |
| 689 | "nandimgsize=400000\0" \ | |
| 690 | "nandfdtsize=80000\0" \ | |
| 691 | "usb_phy_type=ulpi\0" \ | |
| 692 | "vscfw_addr=ef000000\0" \ | |
| 693 | "othbootargs=ramdisk_size=600000\0" \ | |
| 694 | "usbfatboot=setenv bootargs root=/dev/ram rw " \ | |
| 695 | "console=$consoledev,$baudrate $othbootargs; " \ | |
| 696 | "usb start;" \ | |
| 697 | "fatload usb 0:2 $loadaddr $bootfile;" \ | |
| 698 | "fatload usb 0:2 $fdtaddr $fdtfile;" \ | |
| 699 | "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ | |
| 700 | "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ | |
| 701 | "usbext2boot=setenv bootargs root=/dev/ram rw " \ | |
| 702 | "console=$consoledev,$baudrate $othbootargs; " \ | |
| 703 | "usb start;" \ | |
| 704 | "ext2load usb 0:4 $loadaddr $bootfile;" \ | |
| 705 | "ext2load usb 0:4 $fdtaddr $fdtfile;" \ | |
| 706 | "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ | |
| 707 | "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ | |
| 708 | "norboot=setenv bootargs root=/dev/$jffs2nor rw " \ | |
| 709 | "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ | |
| 710 | "bootm $norbootaddr - $norfdtaddr\0" \ | |
| 711 | "nandboot=setenv bootargs root=/dev/$jffs2nand rw rootfstype=jffs2 " \ | |
| 712 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 713 | "nand read 2000000 $nandbootaddr $nandimgsize;" \ | |
| 714 | "nand read 3000000 $nandfdtaddr $nandfdtsize;" \ | |
| 715 | "bootm 2000000 - 3000000;\0" | |
| 716 | ||
| 717 | #define CONFIG_NFSBOOTCOMMAND \ | |
| 718 | "setenv bootargs root=/dev/nfs rw " \ | |
| 719 | "nfsroot=$serverip:$rootpath " \ | |
| 720 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
| 721 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 722 | "tftp $loadaddr $bootfile;" \ | |
| 723 | "tftp $fdtaddr $fdtfile;" \ | |
| 724 | "bootm $loadaddr - $fdtaddr" | |
| 725 | ||
| 726 | #define CONFIG_HDBOOT \ | |
| 727 | "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ | |
| 728 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 729 | "usb start;" \ | |
| 730 | "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ | |
| 731 | "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ | |
| 732 | "bootm $loadaddr - $fdtaddr" | |
| 733 | ||
| 734 | #define CONFIG_RAMBOOTCOMMAND \ | |
| 735 | "setenv bootargs root=/dev/ram rw " \ | |
| 736 | "console=$consoledev,$baudrate $othbootargs; " \ | |
| 737 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
| 738 | "tftp $loadaddr $bootfile;" \ | |
| 739 | "tftp $fdtaddr $fdtfile;" \ | |
| 740 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
| 741 | ||
| 742 | #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT | |
| 743 | ||
| 744 | #endif /* __CONFIG_H */ |