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9839709e | 1 | /* |
3d7506fa | 2 | * Copyright 2009-2010,2012 Freescale Semiconductor, Inc. |
9839709e | 3 | * |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
9839709e IS |
5 | */ |
6 | ||
7 | #ifndef __CONFIG_H | |
8 | #define __CONFIG_H | |
9 | ||
10 | /* The P2020COME board is only booted via the Freescale On-Chip ROM */ | |
11 | #define CONFIG_SYS_RAMBOOT | |
12 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
13 | ||
14 | #define CONFIG_SYS_TEXT_BASE 0xf8f80000 | |
15 | #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc | |
16 | ||
17 | #ifdef CONFIG_SDCARD | |
18 | #define CONFIG_RAMBOOT_SDCARD 1 | |
19 | #endif | |
20 | ||
21 | #ifdef CONFIG_SPIFLASH | |
22 | #define CONFIG_RAMBOOT_SPIFLASH 1 | |
23 | #endif | |
24 | ||
25 | #ifndef CONFIG_SYS_MONITOR_BASE | |
26 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ | |
27 | #endif | |
28 | ||
29 | /* High Level Configuration Options */ | |
30 | #define CONFIG_BOOKE 1 /* BOOKE */ | |
31 | #define CONFIG_E500 1 /* BOOKE e500 family */ | |
32 | #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/P1020/P2020,etc*/ | |
33 | #define CONFIG_P2020 1 | |
34 | #define CONFIG_P2020COME 1 | |
35 | #define CONFIG_FSL_ELBC 1 /* Enable eLBC Support */ | |
36 | #define CONFIG_MP | |
37 | ||
38 | #define CONFIG_PCI 1 /* Enable PCI/PCIE */ | |
39 | #if defined(CONFIG_PCI) | |
40 | #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ | |
41 | #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ | |
42 | #define CONFIG_PCIE3 1 /* PCIE controller 3 (slot 3) */ | |
43 | ||
44 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ | |
842033e6 | 45 | #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ |
9839709e IS |
46 | #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ |
47 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ | |
48 | #endif /* #if defined(CONFIG_PCI) */ | |
49 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ | |
50 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ | |
51 | #define CONFIG_ENV_OVERWRITE | |
52 | ||
53 | #if defined(CONFIG_PCI) | |
54 | #define CONFIG_E1000 1 /* E1000 pci Ethernet card */ | |
55 | #endif | |
56 | ||
57 | #ifndef __ASSEMBLY__ | |
58 | extern unsigned long get_board_ddr_clk(unsigned long dummy); | |
59 | extern unsigned long get_board_sys_clk(unsigned long dummy); | |
60 | #endif | |
61 | ||
62 | /* | |
63 | * For P2020COME DDRCLK and SYSCLK are from the same oscillator | |
64 | * For DA phase the SYSCLK is 66MHz | |
65 | * For EA phase the SYSCLK is 100MHz | |
66 | */ | |
67 | #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) | |
68 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) | |
69 | ||
70 | #define CONFIG_HWCONFIG | |
71 | ||
72 | /* | |
73 | * These can be toggled for performance analysis, otherwise use default. | |
74 | */ | |
75 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
76 | #define CONFIG_BTB /* toggle branch prediction */ | |
77 | ||
78 | #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ | |
79 | ||
80 | #define CONFIG_ENABLE_36BIT_PHYS 1 | |
81 | ||
82 | #ifdef CONFIG_PHYS_64BIT | |
83 | #define CONFIG_ADDR_MAP 1 | |
84 | #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ | |
85 | #endif | |
86 | ||
87 | #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ | |
88 | #define CONFIG_SYS_MEMTEST_END 0x1fffffff | |
89 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ | |
90 | ||
9839709e IS |
91 | /* |
92 | * Config the L2 Cache as L2 SRAM | |
93 | */ | |
94 | #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 | |
95 | #ifdef CONFIG_PHYS_64BIT | |
96 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull | |
97 | #else | |
98 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR | |
99 | #endif | |
100 | #define CONFIG_SYS_L2_SIZE (512 << 10) | |
101 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR \ | |
102 | + CONFIG_SYS_L2_SIZE) | |
103 | ||
104 | #define CONFIG_SYS_CCSRBAR 0xffe00000 | |
105 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
106 | ||
107 | /* DDR Setup */ | |
108 | #define CONFIG_FSL_DDR3 | |
109 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ | |
110 | #define CONFIG_DDR_SPD | |
111 | ||
112 | #define CONFIG_DDR_ECC | |
113 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER | |
114 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef | |
115 | ||
116 | #define CONFIG_SYS_SDRAM_SIZE 2048ULL /* DDR size on P2020COME */ | |
117 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
118 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
119 | ||
120 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
121 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
122 | #define CONFIG_CHIP_SELECTS_PER_CTRL 2 | |
123 | ||
124 | #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d | |
125 | #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 | |
126 | #define CONFIG_SYS_DDR_SBE 0x00ff0000 | |
127 | ||
128 | #define CONFIG_SYS_SPD_BUS_NUM 1 | |
129 | #define SPD_EEPROM_ADDRESS 0x53 | |
130 | ||
131 | /* | |
132 | * Memory map | |
133 | * | |
134 | * 0x0000_0000 0x7fff_ffff DDR3 2G Cacheable | |
135 | * 0x8000_0000 0x9fff_ffff PCI Express 3 Mem 1G non-cacheable | |
136 | * 0xa000_0000 0xbfff_ffff PCI Express 2 Mem 1G non-cacheable | |
137 | * 0xc000_0000 0xdfff_ffff PCI Express 1 Mem 1G non-cacheable | |
138 | * 0xffc1_0000 0xffc1_ffff PCI Express 3 IO 64K non-cacheable | |
139 | * 0xffc2_0000 0xffc2_ffff PCI Express 2 IO 64K non-cacheable | |
140 | * 0xffc3_0000 0xffc3_ffff PCI Express 1 IO 64K non-cacheable | |
141 | * | |
142 | * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 | |
143 | * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable | |
144 | */ | |
145 | ||
146 | /* | |
147 | * Local Bus Definitions | |
148 | */ | |
149 | ||
150 | /* There is no NOR Flash on P2020COME */ | |
151 | #define CONFIG_SYS_NO_FLASH | |
152 | ||
153 | #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ | |
154 | #define CONFIG_HWCONFIG | |
155 | ||
156 | #define CONFIG_SYS_INIT_RAM_LOCK 1 | |
157 | #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ | |
158 | #ifdef CONFIG_PHYS_64BIT | |
159 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf | |
160 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR | |
161 | /* the assembler doesn't like typecast */ | |
162 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ | |
163 | ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ | |
164 | CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) | |
165 | #else | |
166 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR | |
167 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 | |
168 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS | |
169 | #endif | |
170 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 | |
171 | ||
172 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ | |
173 | - GENERATED_GBL_DATA_SIZE) | |
174 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
175 | ||
176 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) | |
177 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) | |
178 | ||
179 | /* Serial Port - controlled on board with jumper J8 | |
180 | * open - index 2 | |
181 | * shorted - index 1 | |
182 | */ | |
183 | #define CONFIG_CONS_INDEX 1 | |
184 | #define CONFIG_SYS_NS16550 | |
185 | #define CONFIG_SYS_NS16550_SERIAL | |
186 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
187 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
188 | ||
9839709e IS |
189 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ |
190 | ||
191 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
192 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} | |
193 | ||
194 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) | |
195 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
196 | ||
197 | /* Use the HUSH parser */ | |
198 | #define CONFIG_SYS_HUSH_PARSER | |
9839709e IS |
199 | |
200 | /* | |
201 | * Pass open firmware flat tree | |
202 | */ | |
203 | #define CONFIG_OF_LIBFDT 1 | |
204 | #define CONFIG_OF_BOARD_SETUP 1 | |
205 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 | |
206 | ||
207 | /* new uImage format support */ | |
208 | #define CONFIG_FIT 1 | |
209 | #define CONFIG_FIT_VERBOSE 1 | |
210 | ||
211 | /* I2C */ | |
212 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
213 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
214 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
215 | #define CONFIG_I2C_MULTI_BUS | |
216 | #define CONFIG_I2C_CMD_TREE | |
217 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address*/ | |
218 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
219 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } | |
220 | #define CONFIG_SYS_I2C_OFFSET 0x3000 | |
221 | #define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
222 | ||
223 | /* | |
224 | * I2C2 EEPROM | |
225 | */ | |
226 | #define CONFIG_ID_EEPROM | |
227 | #ifdef CONFIG_ID_EEPROM | |
228 | #define CONFIG_SYS_I2C_EEPROM_NXID | |
229 | #endif | |
230 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 | |
231 | #define CONFIG_SYS_I2C_EEPROM_ADDR2 0x18 | |
232 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
233 | #define CONFIG_SYS_EEPROM_BUS_NUM 0 | |
234 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ | |
235 | ||
236 | /* | |
237 | * eSPI - Enhanced SPI | |
238 | */ | |
239 | #define CONFIG_FSL_ESPI | |
240 | #define CONFIG_SPI_FLASH | |
241 | #define CONFIG_SPI_FLASH_STMICRO | |
242 | #define CONFIG_CMD_SF | |
243 | #define CONFIG_SF_DEFAULT_SPEED 10000000 | |
244 | #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 | |
245 | ||
246 | /* | |
247 | * General PCI | |
248 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
249 | */ | |
250 | #if defined(CONFIG_PCI) | |
251 | ||
252 | /* controller 3, Slot 3, tgtid 3, Base address 8000 */ | |
253 | #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 | |
254 | #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 | |
255 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 | |
256 | #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ | |
257 | #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc10000 | |
258 | #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 | |
259 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc10000 | |
260 | #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ | |
261 | ||
262 | /* controller 2, Slot 2, tgtid 2, Base address 9000 */ | |
263 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 | |
264 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 | |
265 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 | |
266 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ | |
267 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000 | |
268 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 | |
269 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000 | |
270 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ | |
271 | ||
272 | /* controller 1, Slot 1, tgtid 1, Base address a000 */ | |
273 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 | |
274 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 | |
275 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 | |
276 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ | |
277 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc30000 | |
278 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
279 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc30000 | |
280 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ | |
281 | ||
282 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
283 | ||
284 | #undef CONFIG_EEPRO100 | |
285 | #undef CONFIG_TULIP | |
286 | #undef CONFIG_RTL8139 | |
287 | ||
288 | #ifdef CONFIG_RTL8139 | |
289 | /* This macro is used by RTL8139 but not defined in PPC architecture */ | |
290 | #define KSEG1ADDR(x) (x) | |
291 | #define _IO_BASE 0x00000000 | |
292 | #endif | |
293 | ||
9839709e IS |
294 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
295 | #define CONFIG_DOS_PARTITION | |
296 | ||
297 | #endif /* CONFIG_PCI */ | |
298 | ||
299 | #if defined(CONFIG_TSEC_ENET) | |
300 | #define CONFIG_MII 1 /* MII PHY management */ | |
301 | #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ | |
302 | #define CONFIG_TSEC1 1 | |
303 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
304 | #define CONFIG_TSEC2 1 | |
305 | #define CONFIG_TSEC2_NAME "eTSEC2" | |
306 | #define CONFIG_TSEC3 1 | |
307 | #define CONFIG_TSEC3_NAME "eTSEC3" | |
308 | ||
309 | #define TSEC1_PHY_ADDR 0 | |
310 | #define TSEC2_PHY_ADDR 2 | |
311 | #define TSEC3_PHY_ADDR 1 | |
312 | ||
313 | #undef CONFIG_VSC7385_ENET | |
314 | ||
315 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
316 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
317 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
318 | ||
319 | #define TSEC1_PHYIDX 0 | |
320 | #define TSEC2_PHYIDX 0 | |
321 | #define TSEC3_PHYIDX 0 | |
322 | ||
323 | #define CONFIG_ETHPRIME "eTSEC1" | |
324 | ||
325 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ | |
326 | ||
327 | #endif /* CONFIG_TSEC_ENET */ | |
328 | ||
329 | /* | |
330 | * Environment | |
331 | */ | |
332 | #if defined(CONFIG_RAMBOOT_SDCARD) | |
333 | #define CONFIG_ENV_IS_IN_MMC 1 | |
4394d0c2 | 334 | #define CONFIG_FSL_FIXED_MMC_LOCATION |
9839709e IS |
335 | #define CONFIG_ENV_SIZE 0x2000 |
336 | #define CONFIG_SYS_MMC_ENV_DEV 0 | |
337 | #elif defined(CONFIG_RAMBOOT_SPIFLASH) | |
338 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
339 | #define CONFIG_ENV_SPI_BUS 0 | |
340 | #define CONFIG_ENV_SPI_CS 0 | |
341 | #define CONFIG_ENV_SPI_MAX_HZ 10000000 | |
342 | #define CONFIG_ENV_SPI_MODE 0 | |
343 | #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ | |
344 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
345 | #define CONFIG_ENV_SIZE 0x2000 | |
346 | #endif | |
347 | ||
348 | #define CONFIG_LOADS_ECHO 1 | |
349 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 | |
350 | ||
351 | /* | |
352 | * Command line configuration. | |
353 | */ | |
354 | #include <config_cmd_default.h> | |
355 | ||
356 | #define CONFIG_CMD_ELF | |
357 | #define CONFIG_CMD_I2C | |
358 | #define CONFIG_CMD_IRQ | |
359 | #define CONFIG_CMD_MII | |
360 | #define CONFIG_CMD_PING | |
361 | #define CONFIG_CMD_SETEXPR | |
362 | #define CONFIG_CMD_REGINFO | |
363 | ||
364 | #if defined(CONFIG_PCI) | |
365 | #define CONFIG_CMD_NET | |
366 | #define CONFIG_CMD_PCI | |
367 | #endif | |
368 | ||
369 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
370 | ||
371 | #define CONFIG_MMC 1 | |
372 | ||
373 | #ifdef CONFIG_MMC | |
374 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ | |
375 | #define CONFIG_CMD_MMC | |
376 | #define CONFIG_DOS_PARTITION | |
377 | #define CONFIG_FSL_ESDHC | |
378 | #define CONFIG_GENERIC_MMC | |
379 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR | |
380 | #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT | |
381 | #endif /* CONFIG_MMC */ | |
382 | ||
3d7506fa | 383 | #define CONFIG_HAS_FSL_DR_USB |
384 | #ifdef CONFIG_HAS_FSL_DR_USB | |
9839709e IS |
385 | #define CONFIG_USB_EHCI |
386 | ||
387 | #ifdef CONFIG_USB_EHCI | |
388 | #define CONFIG_CMD_USB | |
389 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
390 | #define CONFIG_USB_EHCI_FSL | |
391 | #define CONFIG_USB_STORAGE | |
3d7506fa | 392 | #endif |
9839709e IS |
393 | #endif |
394 | ||
395 | #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) | |
396 | #define CONFIG_CMD_EXT2 | |
397 | #define CONFIG_CMD_FAT | |
398 | #define CONFIG_DOS_PARTITION | |
399 | #endif | |
400 | ||
401 | /* Misc Extra Settings */ | |
9839709e IS |
402 | #define CONFIG_CMD_DHCP 1 |
403 | ||
404 | #define CONFIG_CMD_DATE 1 | |
405 | #define CONFIG_RTC_M41T62 1 | |
406 | #define CONFIG_SYS_RTC_BUS_NUM 1 | |
407 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 | |
408 | ||
409 | /* | |
410 | * Miscellaneous configurable options | |
411 | */ | |
412 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
413 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ | |
414 | #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ | |
415 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
416 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
417 | #if defined(CONFIG_CMD_KGDB) | |
418 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
419 | #else | |
420 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
421 | #endif | |
422 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
423 | /* Print Buffer Size */ | |
424 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
425 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ | |
426 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */ | |
427 | ||
428 | /* | |
429 | * For booting Linux, the board info and command line data | |
430 | * have to be in the first 64 MB of memory, since this is | |
431 | * the maximum mapped by the Linux kernel during initialization. | |
432 | */ | |
433 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) | |
434 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) | |
435 | ||
436 | #if defined(CONFIG_CMD_KGDB) | |
437 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
438 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
439 | #endif | |
440 | ||
441 | /* | |
442 | * Environment Configuration | |
443 | */ | |
444 | ||
445 | /* The mac addresses for all ethernet interface */ | |
446 | #if defined(CONFIG_TSEC_ENET) | |
447 | #define CONFIG_HAS_ETH0 | |
448 | #define CONFIG_HAS_ETH1 | |
449 | #define CONFIG_HAS_ETH2 | |
450 | #define CONFIG_HAS_ETH3 | |
451 | #endif | |
452 | ||
453 | #define CONFIG_HOSTNAME unknown | |
454 | #define CONFIG_ROOTPATH "/opt/nfsroot" | |
455 | #define CONFIG_BOOTFILE "uImage" | |
456 | #define CONFIG_UBOOTPATH u-boot.bin | |
457 | ||
458 | /* default location for tftp and bootm */ | |
459 | #define CONFIG_LOADADDR 1000000 | |
460 | ||
461 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ | |
462 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ | |
463 | ||
464 | #define CONFIG_BAUDRATE 115200 | |
465 | ||
466 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
467 | "hwconfig=fsl_ddr:ecc=on\0" \ | |
468 | "bootcmd=run sdboot\0" \ | |
469 | "sdboot=setenv bootargs root=/dev/mmcblk0p2 rw " \ | |
470 | "rootdelay=$rootdelaysecond console=$consoledev,$baudrate "\ | |
471 | "$othbootargs; mmcinfo; " \ | |
472 | "ext2load mmc 0:2 $loadaddr /boot/$bootfile; " \ | |
473 | "ext2load mmc 0:2 $fdtaddr /boot/$fdtfile; " \ | |
474 | "bootm $loadaddr - $fdtaddr\0" \ | |
475 | "sdfatboot=setenv bootargs root=/dev/ram rw " \ | |
476 | "rootdelay=$rootdelaysecond console=$consoledev,$baudrate "\ | |
477 | "$othbootargs; mmcinfo; " \ | |
478 | "fatload mmc 0:1 $loadaddr $bootfile; " \ | |
479 | "fatload mmc 0:1 $fdtaddr $fdtfile; " \ | |
480 | "fatload mmc 0:1 $ramdiskaddr $ramdiskfile; " \ | |
481 | "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ | |
482 | "usbboot=setenv bootargs root=/dev/sda1 rw " \ | |
483 | "rootdelay=$rootdelaysecond console=$consoledev,$baudrate "\ | |
484 | "$othbootargs; " \ | |
485 | "usb start; " \ | |
486 | "ext2load usb 0:1 $loadaddr /boot/$bootfile; " \ | |
487 | "ext2load usb 0:1 $fdtaddr /boot/$fdtfile; " \ | |
488 | "bootm $loadaddr - $fdtaddr\0" \ | |
489 | "usbfatboot=setenv bootargs root=/dev/ram rw " \ | |
490 | "console=$consoledev,$baudrate $othbootargs; " \ | |
491 | "usb start; " \ | |
492 | "fatload usb 0:2 $loadaddr $bootfile; " \ | |
493 | "fatload usb 0:2 $fdtaddr $fdtfile; " \ | |
494 | "fatload usb 0:2 $ramdiskaddr $ramdiskfile; " \ | |
495 | "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ | |
496 | "usbext2boot=setenv bootargs root=/dev/ram rw " \ | |
497 | "console=$consoledev,$baudrate $othbootargs; " \ | |
498 | "usb start; " \ | |
499 | "ext2load usb 0:4 $loadaddr $bootfile; " \ | |
500 | "ext2load usb 0:4 $fdtaddr $fdtfile; " \ | |
501 | "ext2load usb 0:4 $ramdiskaddr $ramdiskfile; " \ | |
502 | "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ | |
503 | "upgradespi=sf probe 0; " \ | |
504 | "setenv startaddr 0; " \ | |
505 | "setenv erasesize a0000; " \ | |
506 | "tftp 1000000 $tftppath/$uboot_spi; " \ | |
507 | "sf erase $startaddr $erasesize; " \ | |
508 | "sf write 1000000 $startaddr $filesize; " \ | |
509 | "sf erase 100000 120000\0" \ | |
510 | "clearspienv=sf probe 0;sf erase 100000 20000\0" \ | |
511 | "othbootargs=ramdisk_size=700000 cache-sram-size=0x10000\0" \ | |
512 | "netdev=eth0\0" \ | |
513 | "rootdelaysecond=15\0" \ | |
514 | "uboot_nor=u-boot-nor.bin\0" \ | |
515 | "uboot_spi=u-boot-p2020.spi\0" \ | |
516 | "uboot_sd=u-boot-p2020.bin\0" \ | |
517 | "consoledev=ttyS0\0" \ | |
518 | "ramdiskaddr=2000000\0" \ | |
519 | "ramdiskfile=rootfs-dev.ext2.img\0" \ | |
520 | "fdtaddr=c00000\0" \ | |
521 | "fdtfile=uImage-2.6.32-p2020.dtb\0" \ | |
522 | "tftppath=p2020\0" | |
523 | ||
524 | #define CONFIG_HDBOOT \ | |
525 | "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ | |
526 | "console=$consoledev,$baudrate $othbootargs;" \ | |
527 | "usb start;" \ | |
528 | "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ | |
529 | "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ | |
530 | "bootm $loadaddr - $fdtaddr" | |
531 | ||
532 | #define CONFIG_NFSBOOTCOMMAND \ | |
533 | "setenv bootargs root=/dev/nfs rw " \ | |
534 | "nfsroot=$serverip:$rootpath " \ | |
535 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\ | |
536 | "console=$consoledev,$baudrate $othbootargs;" \ | |
537 | "tftp $loadaddr $tftppath/$bootfile;" \ | |
538 | "tftp $fdtaddr $tftppath/$fdtfile;" \ | |
539 | "bootm $loadaddr - $fdtaddr" | |
540 | ||
6b62b9a3 | 541 | |
9839709e IS |
542 | #define CONFIG_RAMBOOTCOMMAND \ |
543 | "setenv bootargs root=/dev/ram rw " \ | |
544 | "console=$consoledev,$baudrate $othbootargs;" \ | |
545 | "tftp $ramdiskaddr $tftppath/$ramdiskfile;" \ | |
546 | "tftp $loadaddr $tftppath/$bootfile;" \ | |
547 | "tftp $fdtaddr $tftppath/$fdtfile;" \ | |
548 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
549 | ||
550 | #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT | |
551 | ||
552 | #endif /* __CONFIG_H */ |