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feb7838f | 1 | /* |
ebf9d526 | 2 | * Copyright 2007-2010 Freescale Semiconductor, Inc. |
feb7838f SS |
3 | * |
4 | * See file CREDITS for list of people who contributed to this | |
5 | * project. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
20 | * MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | /* | |
24 | * p2020ds board configuration file | |
25 | * | |
26 | */ | |
27 | #ifndef __CONFIG_H | |
28 | #define __CONFIG_H | |
29 | ||
ebf9d526 KG |
30 | #include "../board/freescale/common/ics307_clk.h" |
31 | ||
d24f2d32 | 32 | #ifdef CONFIG_36BIT |
a0f9e0e0 KG |
33 | #define CONFIG_PHYS_64BIT |
34 | #endif | |
35 | ||
feb7838f SS |
36 | /* High Level Configuration Options */ |
37 | #define CONFIG_BOOKE 1 /* BOOKE */ | |
38 | #define CONFIG_E500 1 /* BOOKE e500 family */ | |
39 | #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ | |
40 | #define CONFIG_P2020 1 | |
41 | #define CONFIG_P2020DS 1 | |
42 | #define CONFIG_MP 1 /* support multiple processors */ | |
feb7838f | 43 | |
2ae18241 WD |
44 | #ifndef CONFIG_SYS_TEXT_BASE |
45 | #define CONFIG_SYS_TEXT_BASE 0xeff80000 | |
46 | #endif | |
47 | ||
feb7838f SS |
48 | #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ |
49 | #define CONFIG_PCI 1 /* Enable PCI/PCIE */ | |
50 | #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ | |
51 | #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ | |
52 | #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ | |
53 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ | |
54 | #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ | |
55 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ | |
56 | ||
57 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ | |
29c35182 | 58 | #define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/ |
feb7838f SS |
59 | |
60 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ | |
61 | #define CONFIG_ENV_OVERWRITE | |
62 | ||
ebf9d526 KG |
63 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ |
64 | #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */ | |
feb7838f | 65 | #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ |
feb7838f SS |
66 | |
67 | /* | |
68 | * These can be toggled for performance analysis, otherwise use default. | |
69 | */ | |
70 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
71 | #define CONFIG_BTB /* toggle branch predition */ | |
72 | ||
73 | #define CONFIG_ENABLE_36BIT_PHYS 1 | |
74 | ||
75 | #ifdef CONFIG_PHYS_64BIT | |
76 | #define CONFIG_ADDR_MAP 1 | |
77 | #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ | |
78 | #endif | |
79 | ||
84bc0030 YS |
80 | #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ |
81 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ | |
82 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
feb7838f SS |
83 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ |
84 | ||
85 | /* | |
86 | * Base addresses -- Note these are effective addresses where the | |
87 | * actual resources get mapped (not physical addresses) | |
88 | */ | |
89 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ | |
90 | #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ | |
91 | #ifdef CONFIG_PHYS_64BIT | |
92 | #define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */ | |
93 | #else | |
94 | #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ | |
95 | #endif | |
96 | #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ | |
97 | ||
feb7838f | 98 | /* DDR Setup */ |
feb7838f | 99 | #define CONFIG_VERY_BIG_RAM |
d24f2d32 | 100 | #ifdef CONFIG_DDR2 |
394c46ca YS |
101 | #define CONFIG_FSL_DDR2 |
102 | #else | |
feb7838f | 103 | #define CONFIG_FSL_DDR3 1 |
394c46ca | 104 | #endif |
feb7838f SS |
105 | #undef CONFIG_FSL_DDR_INTERACTIVE |
106 | ||
8e5e9b94 WD |
107 | /* ECC will be enabled based on perf_mode environment variable */ |
108 | /* #define CONFIG_DDR_ECC */ | |
109 | ||
feb7838f SS |
110 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER |
111 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
112 | ||
113 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
114 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
115 | ||
116 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
117 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
118 | #define CONFIG_CHIP_SELECTS_PER_CTRL 2 | |
119 | ||
120 | /* I2C addresses of SPD EEPROMs */ | |
394c46ca | 121 | #define CONFIG_DDR_SPD |
feb7838f SS |
122 | #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD EEPROM located on I2C bus 0 */ |
123 | #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ | |
124 | ||
125 | /* These are used when DDR doesn't use SPD. */ | |
feb7838f SS |
126 | #define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1GB */ |
127 | ||
128 | /* Default settings for "stable" mode */ | |
129 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F | |
130 | #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 | |
131 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 | |
132 | #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000 | |
133 | #define CONFIG_SYS_DDR_TIMING_3 0x00020000 | |
134 | #define CONFIG_SYS_DDR_TIMING_0 0x00330804 | |
135 | #define CONFIG_SYS_DDR_TIMING_1 0x6f6b4846 | |
136 | #define CONFIG_SYS_DDR_TIMING_2 0x0fa890d4 | |
137 | #define CONFIG_SYS_DDR_MODE_1 0x00421422 | |
138 | #define CONFIG_SYS_DDR_MODE_2 0x00000000 | |
139 | #define CONFIG_SYS_DDR_MODE_CTRL 0x00000000 | |
140 | #define CONFIG_SYS_DDR_INTERVAL 0x61800100 | |
141 | #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef | |
142 | #define CONFIG_SYS_DDR_CLK_CTRL 0x02000000 | |
143 | #define CONFIG_SYS_DDR_TIMING_4 0x00220001 | |
144 | #define CONFIG_SYS_DDR_TIMING_5 0x03402400 | |
145 | #define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 | |
146 | #define CONFIG_SYS_DDR_WRLVL_CNTL 0x8655A608 | |
147 | #define CONFIG_SYS_DDR_CONTROL 0xE7000000 /* Type = DDR3: ECC enabled, No Interleaving */ | |
148 | #define CONFIG_SYS_DDR_CONTROL2 0x24400011 | |
149 | #define CONFIG_SYS_DDR_CDR1 0x00040000 | |
150 | #define CONFIG_SYS_DDR_CDR2 0x00000000 | |
151 | ||
152 | #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d | |
153 | #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 | |
154 | #define CONFIG_SYS_DDR_SBE 0x00010000 | |
155 | ||
156 | /* Settings that differ for "performance" mode */ | |
157 | #define CONFIG_SYS_DDR_CS0_BNDS_PERF 0x0000007F /* Interleaving Enabled */ | |
158 | #define CONFIG_SYS_DDR_CS1_BNDS_PERF 0x00000000 /* Interleaving Enabled */ | |
159 | #define CONFIG_SYS_DDR_CS1_CONFIG_PERF 0x80014202 | |
160 | #define CONFIG_SYS_DDR_TIMING_1_PERF 0x5d5b4543 | |
161 | #define CONFIG_SYS_DDR_TIMING_2_PERF 0x0fa890ce | |
162 | #define CONFIG_SYS_DDR_CONTROL_PERF 0xC7004000 /* Type = DDR3: ECC disabled, cs0-cs1 interleaving */ | |
163 | ||
164 | /* | |
165 | * The following set of values were tested for DDR2 | |
166 | * with a DDR3 to DDR2 interposer | |
167 | * | |
168 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 | |
169 | #define CONFIG_SYS_DDR_TIMING_0 0x00260802 | |
170 | #define CONFIG_SYS_DDR_TIMING_1 0x3935d322 | |
171 | #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 | |
172 | #define CONFIG_SYS_DDR_MODE_1 0x00480432 | |
173 | #define CONFIG_SYS_DDR_MODE_2 0x00000000 | |
174 | #define CONFIG_SYS_DDR_INTERVAL 0x06180100 | |
175 | #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef | |
176 | #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 | |
177 | #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 | |
178 | #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 | |
179 | #define CONFIG_SYS_DDR_CONTROL 0xC3008000 | |
180 | #define CONFIG_SYS_DDR_CONTROL2 0x04400010 | |
181 | * | |
182 | */ | |
183 | ||
184 | #undef CONFIG_CLOCKS_IN_MHZ | |
185 | ||
186 | /* | |
187 | * Memory map | |
188 | * | |
189 | * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable | |
190 | * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable | |
191 | * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable | |
192 | * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable | |
193 | * | |
194 | * Localbus cacheable (TBD) | |
195 | * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable | |
196 | * | |
197 | * Localbus non-cacheable | |
198 | * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable | |
199 | * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable | |
200 | * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable | |
201 | * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 | |
202 | * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 | |
203 | * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable | |
204 | */ | |
205 | ||
206 | /* | |
207 | * Local Bus Definitions | |
208 | */ | |
209 | #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ | |
210 | #ifdef CONFIG_PHYS_64BIT | |
211 | #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull | |
212 | #else | |
213 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE | |
214 | #endif | |
215 | ||
216 | #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V) | |
217 | #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 | |
218 | ||
219 | #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) | |
220 | #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 | |
221 | ||
222 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} | |
223 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
224 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
225 | ||
226 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ | |
227 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
228 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
229 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
230 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
231 | ||
14d0a02a | 232 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
feb7838f SS |
233 | |
234 | #define CONFIG_FLASH_CFI_DRIVER | |
235 | #define CONFIG_SYS_FLASH_CFI | |
236 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
237 | #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 | |
238 | ||
239 | #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ | |
240 | ||
394c46ca | 241 | #define CONFIG_HWCONFIG /* enable hwconfig */ |
5a469608 TT |
242 | #define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ |
243 | ||
244 | #ifdef CONFIG_FSL_NGPIXIS | |
feb7838f SS |
245 | #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ |
246 | #ifdef CONFIG_PHYS_64BIT | |
247 | #define PIXIS_BASE_PHYS 0xfffdf0000ull | |
248 | #else | |
249 | #define PIXIS_BASE_PHYS PIXIS_BASE | |
250 | #endif | |
251 | ||
252 | #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) | |
253 | #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ | |
254 | ||
5a469608 TT |
255 | #define PIXIS_LBMAP_SWITCH 7 |
256 | #define PIXIS_LBMAP_MASK 0xf0 | |
257 | #define PIXIS_LBMAP_SHIFT 4 | |
258 | #define PIXIS_LBMAP_ALTBANK 0x20 | |
259 | #endif | |
feb7838f SS |
260 | |
261 | #define CONFIG_SYS_INIT_RAM_LOCK 1 | |
262 | #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ | |
d51cc7a0 YS |
263 | #ifdef CONFIG_PHYS_64BIT |
264 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf | |
265 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR | |
266 | /* The assembler doesn't like typecast */ | |
267 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ | |
268 | ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ | |
269 | CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) | |
270 | #else | |
271 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ | |
272 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 | |
273 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS | |
274 | #endif | |
feb7838f SS |
275 | #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ |
276 | ||
277 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ | |
278 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
279 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
280 | ||
281 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ | |
282 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ | |
283 | ||
284 | #define CONFIG_SYS_NAND_BASE 0xffa00000 | |
285 | #ifdef CONFIG_PHYS_64BIT | |
286 | #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull | |
287 | #else | |
288 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE | |
289 | #endif | |
290 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ | |
291 | CONFIG_SYS_NAND_BASE + 0x40000, \ | |
292 | CONFIG_SYS_NAND_BASE + 0x80000,\ | |
293 | CONFIG_SYS_NAND_BASE + 0xC0000} | |
294 | #define CONFIG_SYS_MAX_NAND_DEVICE 4 | |
295 | #define CONFIG_MTD_NAND_VERIFY_WRITE | |
296 | #define CONFIG_CMD_NAND 1 | |
297 | #define CONFIG_NAND_FSL_ELBC 1 | |
298 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) | |
299 | ||
300 | /* NAND flash config */ | |
301 | #define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | |
302 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | |
303 | | BR_PS_8 /* Port Size = 8bit */ \ | |
304 | | BR_MS_FCM /* MSEL = FCM */ \ | |
305 | | BR_V) /* valid */ | |
306 | #define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ | |
307 | | OR_FCM_PGS /* Large Page*/ \ | |
308 | | OR_FCM_CSCT \ | |
309 | | OR_FCM_CST \ | |
310 | | OR_FCM_CHT \ | |
311 | | OR_FCM_SCY_1 \ | |
312 | | OR_FCM_TRLX \ | |
313 | | OR_FCM_EHTR) | |
314 | ||
315 | #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ | |
316 | #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ | |
317 | #define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ | |
318 | #define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ | |
319 | ||
320 | #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\ | |
321 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | |
322 | | BR_PS_8 /* Port Size = 8bit */ \ | |
323 | | BR_MS_FCM /* MSEL = FCM */ \ | |
324 | | BR_V) /* valid */ | |
325 | #define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ | |
326 | #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\ | |
327 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | |
328 | | BR_PS_8 /* Port Size = 8bit */ \ | |
329 | | BR_MS_FCM /* MSEL = FCM */ \ | |
330 | | BR_V) /* valid */ | |
331 | #define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ | |
332 | ||
333 | #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\ | |
334 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | |
335 | | BR_PS_8 /* Port Size = 8bit */ \ | |
336 | | BR_MS_FCM /* MSEL = FCM */ \ | |
337 | | BR_V) /* valid */ | |
338 | #define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ | |
339 | ||
340 | /* Serial Port - controlled on board with jumper J8 | |
341 | * open - index 2 | |
342 | * shorted - index 1 | |
343 | */ | |
344 | #define CONFIG_CONS_INDEX 1 | |
feb7838f SS |
345 | #define CONFIG_SYS_NS16550 |
346 | #define CONFIG_SYS_NS16550_SERIAL | |
347 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
348 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
349 | ||
350 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
351 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} | |
352 | ||
353 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) | |
354 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
355 | ||
356 | /* Use the HUSH parser */ | |
357 | #define CONFIG_SYS_HUSH_PARSER | |
358 | #ifdef CONFIG_SYS_HUSH_PARSER | |
359 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
360 | #endif | |
361 | ||
362 | /* | |
363 | * Pass open firmware flat tree | |
364 | */ | |
365 | #define CONFIG_OF_LIBFDT 1 | |
366 | #define CONFIG_OF_BOARD_SETUP 1 | |
367 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 | |
368 | ||
feb7838f SS |
369 | /* I2C */ |
370 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
371 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
372 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
373 | #define CONFIG_I2C_MULTI_BUS | |
feb7838f SS |
374 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
375 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 | |
376 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
377 | #define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}/* Don't probe these addrs */ | |
378 | #define CONFIG_SYS_I2C_OFFSET 0x3000 | |
379 | #define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
380 | ||
381 | /* | |
382 | * I2C2 EEPROM | |
383 | */ | |
384 | #define CONFIG_ID_EEPROM | |
385 | #ifdef CONFIG_ID_EEPROM | |
386 | #define CONFIG_SYS_I2C_EEPROM_NXID | |
387 | #endif | |
388 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 | |
389 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
390 | #define CONFIG_SYS_EEPROM_BUS_NUM 0 | |
391 | ||
392 | /* | |
393 | * General PCI | |
394 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
395 | */ | |
396 | ||
397 | /* controller 3, Slot 1, tgtid 3, Base address b000 */ | |
398 | #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 | |
399 | #ifdef CONFIG_PHYS_64BIT | |
156984a3 | 400 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 |
feb7838f SS |
401 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull |
402 | #else | |
403 | #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 | |
404 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 | |
405 | #endif | |
406 | #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ | |
407 | #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 | |
408 | #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 | |
409 | #ifdef CONFIG_PHYS_64BIT | |
410 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull | |
411 | #else | |
412 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 | |
413 | #endif | |
414 | #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ | |
415 | ||
416 | /* controller 2, direct to uli, tgtid 2, Base address 9000 */ | |
417 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 | |
418 | #ifdef CONFIG_PHYS_64BIT | |
156984a3 | 419 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 |
feb7838f SS |
420 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull |
421 | #else | |
422 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 | |
423 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 | |
424 | #endif | |
425 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ | |
426 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 | |
427 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 | |
428 | #ifdef CONFIG_PHYS_64BIT | |
429 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull | |
430 | #else | |
431 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 | |
432 | #endif | |
433 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ | |
434 | ||
435 | /* controller 1, Slot 2, tgtid 1, Base address a000 */ | |
436 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 | |
437 | #ifdef CONFIG_PHYS_64BIT | |
156984a3 | 438 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 |
feb7838f SS |
439 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull |
440 | #else | |
441 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 | |
442 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 | |
443 | #endif | |
444 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ | |
445 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 | |
446 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
447 | #ifdef CONFIG_PHYS_64BIT | |
448 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull | |
449 | #else | |
450 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 | |
451 | #endif | |
452 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ | |
453 | ||
454 | #if defined(CONFIG_PCI) | |
455 | ||
456 | /*PCIE video card used*/ | |
457 | #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT | |
458 | ||
459 | /* video */ | |
460 | #define CONFIG_VIDEO | |
461 | ||
462 | #if defined(CONFIG_VIDEO) | |
463 | #define CONFIG_BIOSEMU | |
464 | #define CONFIG_CFB_CONSOLE | |
465 | #define CONFIG_VIDEO_SW_CURSOR | |
466 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
467 | #define CONFIG_ATI_RADEON_FB | |
468 | #define CONFIG_VIDEO_LOGO | |
469 | /*#define CONFIG_CONSOLE_CURSOR*/ | |
470 | #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET | |
471 | #endif | |
472 | ||
473 | #define CONFIG_NET_MULTI | |
474 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
475 | ||
476 | #undef CONFIG_EEPRO100 | |
477 | #undef CONFIG_TULIP | |
478 | #define CONFIG_RTL8139 | |
479 | ||
feb7838f SS |
480 | #ifndef CONFIG_PCI_PNP |
481 | #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS | |
482 | #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS | |
483 | #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ | |
484 | #endif | |
485 | ||
486 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
487 | #define CONFIG_DOS_PARTITION | |
488 | #define CONFIG_SCSI_AHCI | |
489 | ||
490 | #ifdef CONFIG_SCSI_AHCI | |
491 | #define CONFIG_SATA_ULI5288 | |
492 | #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 | |
493 | #define CONFIG_SYS_SCSI_MAX_LUN 1 | |
494 | #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) | |
495 | #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE | |
496 | #endif /* SCSI */ | |
497 | ||
498 | #endif /* CONFIG_PCI */ | |
499 | ||
500 | ||
501 | #if defined(CONFIG_TSEC_ENET) | |
502 | ||
503 | #ifndef CONFIG_NET_MULTI | |
504 | #define CONFIG_NET_MULTI 1 | |
505 | #endif | |
506 | ||
507 | #define CONFIG_MII 1 /* MII PHY management */ | |
508 | #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ | |
509 | #define CONFIG_TSEC1 1 | |
510 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
511 | #define CONFIG_TSEC2 1 | |
512 | #define CONFIG_TSEC2_NAME "eTSEC2" | |
513 | #define CONFIG_TSEC3 1 | |
514 | #define CONFIG_TSEC3_NAME "eTSEC3" | |
515 | ||
516 | #define CONFIG_PIXIS_SGMII_CMD | |
517 | #define CONFIG_FSL_SGMII_RISER 1 | |
518 | #define SGMII_RISER_PHY_OFFSET 0x1b | |
519 | ||
520 | #ifdef CONFIG_FSL_SGMII_RISER | |
521 | #define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */ | |
522 | #endif | |
523 | ||
524 | #define TSEC1_PHY_ADDR 0 | |
525 | #define TSEC2_PHY_ADDR 1 | |
526 | #define TSEC3_PHY_ADDR 2 | |
527 | ||
528 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
529 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
530 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
531 | ||
532 | #define TSEC1_PHYIDX 0 | |
533 | #define TSEC2_PHYIDX 0 | |
534 | #define TSEC3_PHYIDX 0 | |
535 | ||
536 | #define CONFIG_ETHPRIME "eTSEC1" | |
537 | ||
538 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ | |
539 | #endif /* CONFIG_TSEC_ENET */ | |
540 | ||
541 | /* | |
542 | * Environment | |
543 | */ | |
544 | #define CONFIG_ENV_IS_IN_FLASH 1 | |
545 | #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 | |
546 | #define CONFIG_ENV_ADDR 0xfff80000 | |
547 | #else | |
548 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) | |
549 | #endif | |
550 | #define CONFIG_ENV_SIZE 0x2000 | |
551 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ | |
552 | ||
553 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
554 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
555 | ||
556 | /* | |
557 | * Command line configuration. | |
558 | */ | |
559 | #include <config_cmd_default.h> | |
560 | ||
561 | #define CONFIG_CMD_IRQ | |
562 | #define CONFIG_CMD_PING | |
563 | #define CONFIG_CMD_I2C | |
564 | #define CONFIG_CMD_MII | |
565 | #define CONFIG_CMD_ELF | |
566 | #define CONFIG_CMD_IRQ | |
567 | #define CONFIG_CMD_SETEXPR | |
199e262e | 568 | #define CONFIG_CMD_REGINFO |
feb7838f SS |
569 | |
570 | #if defined(CONFIG_PCI) | |
571 | #define CONFIG_CMD_PCI | |
feb7838f SS |
572 | #define CONFIG_CMD_NET |
573 | #define CONFIG_CMD_SCSI | |
574 | #define CONFIG_CMD_EXT2 | |
575 | #endif | |
576 | ||
0ead6f2e RZ |
577 | /* |
578 | * USB | |
579 | */ | |
580 | #define CONFIG_CMD_USB | |
581 | #define CONFIG_USB_STORAGE | |
582 | #define CONFIG_USB_EHCI | |
583 | #define CONFIG_USB_EHCI_FSL | |
584 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
585 | ||
feb7838f SS |
586 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
587 | ||
588 | /* | |
589 | * Miscellaneous configurable options | |
590 | */ | |
591 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
5be58f5f KP |
592 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
593 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
feb7838f SS |
594 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
595 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
596 | #if defined(CONFIG_CMD_KGDB) | |
597 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
598 | #else | |
599 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
600 | #endif | |
601 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
602 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
603 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
604 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ | |
605 | ||
606 | /* | |
607 | * For booting Linux, the board info and command line data | |
89188a62 | 608 | * have to be in the first 16 MB of memory, since this is |
feb7838f SS |
609 | * the maximum mapped by the Linux kernel during initialization. |
610 | */ | |
89188a62 | 611 | #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ |
feb7838f | 612 | |
feb7838f SS |
613 | #if defined(CONFIG_CMD_KGDB) |
614 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
615 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
616 | #endif | |
617 | ||
618 | /* | |
619 | * Environment Configuration | |
620 | */ | |
621 | ||
622 | /* The mac addresses for all ethernet interface */ | |
623 | #if defined(CONFIG_TSEC_ENET) | |
624 | #define CONFIG_HAS_ETH0 | |
625 | #define CONFIG_ETHADDR 00:E0:0C:02:00:FD | |
626 | #define CONFIG_HAS_ETH1 | |
627 | #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD | |
628 | #define CONFIG_HAS_ETH2 | |
629 | #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD | |
630 | #define CONFIG_HAS_ETH3 | |
631 | #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD | |
632 | #endif | |
633 | ||
634 | #define CONFIG_IPADDR 192.168.1.254 | |
635 | ||
636 | #define CONFIG_HOSTNAME unknown | |
637 | #define CONFIG_ROOTPATH /opt/nfsroot | |
638 | #define CONFIG_BOOTFILE uImage | |
639 | #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ | |
640 | ||
641 | #define CONFIG_SERVERIP 192.168.1.1 | |
642 | #define CONFIG_GATEWAYIP 192.168.1.1 | |
643 | #define CONFIG_NETMASK 255.255.255.0 | |
644 | ||
645 | /* default location for tftp and bootm */ | |
646 | #define CONFIG_LOADADDR 1000000 | |
647 | ||
648 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ | |
649 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ | |
650 | ||
651 | #define CONFIG_BAUDRATE 115200 | |
652 | ||
653 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
654 | "perf_mode=stable\0" \ | |
655 | "memctl_intlv_ctl=2\0" \ | |
656 | "netdev=eth0\0" \ | |
657 | "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ | |
658 | "tftpflash=tftpboot $loadaddr $uboot; " \ | |
14d0a02a WD |
659 | "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ |
660 | "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ | |
661 | "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \ | |
662 | "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ | |
663 | "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ | |
feb7838f SS |
664 | "consoledev=ttyS0\0" \ |
665 | "ramdiskaddr=2000000\0" \ | |
666 | "ramdiskfile=p2020ds/ramdisk.uboot\0" \ | |
667 | "fdtaddr=c00000\0" \ | |
668 | "fdtfile=p2020ds/p2020ds.dtb\0" \ | |
669 | "bdev=sda3\0" | |
670 | ||
671 | #define CONFIG_HDBOOT \ | |
672 | "setenv bootargs root=/dev/$bdev rw " \ | |
673 | "console=$consoledev,$baudrate $othbootargs;" \ | |
674 | "tftp $loadaddr $bootfile;" \ | |
675 | "tftp $fdtaddr $fdtfile;" \ | |
676 | "bootm $loadaddr - $fdtaddr" | |
677 | ||
678 | #define CONFIG_NFSBOOTCOMMAND \ | |
679 | "setenv bootargs root=/dev/nfs rw " \ | |
680 | "nfsroot=$serverip:$rootpath " \ | |
681 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
682 | "console=$consoledev,$baudrate $othbootargs;" \ | |
683 | "tftp $loadaddr $bootfile;" \ | |
684 | "tftp $fdtaddr $fdtfile;" \ | |
685 | "bootm $loadaddr - $fdtaddr" | |
686 | ||
687 | #define CONFIG_RAMBOOTCOMMAND \ | |
688 | "setenv bootargs root=/dev/ram rw " \ | |
689 | "console=$consoledev,$baudrate $othbootargs;" \ | |
690 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
691 | "tftp $loadaddr $bootfile;" \ | |
692 | "tftp $fdtaddr $fdtfile;" \ | |
693 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
694 | ||
695 | #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT | |
696 | ||
697 | #endif /* __CONFIG_H */ |