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83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
4f1d1b7d | 2 | /* |
3d7506fa | 3 | * Copyright 2011-2012 Freescale Semiconductor, Inc. |
2f3bb4ab | 4 | * Copyright 2020 NXP |
4f1d1b7d MH |
5 | */ |
6 | ||
7 | /* | |
8 | * P2041 RDB board configuration file | |
3e978f5d | 9 | * Also supports P2040 RDB |
4f1d1b7d MH |
10 | */ |
11 | #ifndef __CONFIG_H | |
12 | #define __CONFIG_H | |
13 | ||
4f1d1b7d MH |
14 | #ifdef CONFIG_RAMBOOT_PBL |
15 | #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE | |
16 | #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc | |
e4536f8e MY |
17 | #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg |
18 | #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p2041rdb.cfg | |
4f1d1b7d MH |
19 | #endif |
20 | ||
461632bd | 21 | #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE |
ff65f126 | 22 | /* Set 1M boot space */ |
461632bd LG |
23 | #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) |
24 | #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ | |
25 | (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) | |
ff65f126 | 26 | #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc |
ff65f126 LG |
27 | #endif |
28 | ||
4f1d1b7d | 29 | /* High Level Configuration Options */ |
4f1d1b7d | 30 | #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ |
4f1d1b7d | 31 | |
4f1d1b7d MH |
32 | #ifndef CONFIG_RESET_VECTOR_ADDRESS |
33 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc | |
34 | #endif | |
35 | ||
36 | #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ | |
51370d56 | 37 | #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS |
b38eaec5 RD |
38 | #define CONFIG_PCIE1 /* PCIE controller 1 */ |
39 | #define CONFIG_PCIE2 /* PCIE controller 2 */ | |
40 | #define CONFIG_PCIE3 /* PCIE controller 3 */ | |
4f1d1b7d MH |
41 | #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ |
42 | ||
43 | #define CONFIG_SYS_SRIO | |
44 | #define CONFIG_SRIO1 /* SRIO port 1 */ | |
45 | #define CONFIG_SRIO2 /* SRIO port 2 */ | |
c8b28152 | 46 | #define CONFIG_SRIO_PCIE_BOOT_MASTER |
4d28db8a | 47 | #define CONFIG_SYS_DPAA_RMAN /* RMan */ |
4f1d1b7d | 48 | |
4f1d1b7d MH |
49 | #define CONFIG_ENV_OVERWRITE |
50 | ||
4f1d1b7d | 51 | #if defined(CONFIG_SPIFLASH) |
4f1d1b7d | 52 | #elif defined(CONFIG_SDCARD) |
4394d0c2 | 53 | #define CONFIG_FSL_FIXED_MMC_LOCATION |
4f1d1b7d | 54 | #define CONFIG_SYS_MMC_ENV_DEV 0 |
4f1d1b7d MH |
55 | #endif |
56 | ||
44d50f0b SX |
57 | #ifndef __ASSEMBLY__ |
58 | unsigned long get_board_sys_clk(unsigned long dummy); | |
59 | #endif | |
60 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) | |
4f1d1b7d MH |
61 | |
62 | /* | |
63 | * These can be toggled for performance analysis, otherwise use default. | |
64 | */ | |
65 | #define CONFIG_SYS_CACHE_STASHING | |
cd420e0b MH |
66 | #define CONFIG_BACKSIDE_L2_CACHE |
67 | #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E | |
4f1d1b7d MH |
68 | #define CONFIG_BTB /* toggle branch predition */ |
69 | ||
70 | #define CONFIG_ENABLE_36BIT_PHYS | |
71 | ||
72 | #ifdef CONFIG_PHYS_64BIT | |
73 | #define CONFIG_ADDR_MAP | |
74 | #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ | |
75 | #endif | |
76 | ||
77 | #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ | |
4f1d1b7d MH |
78 | |
79 | /* | |
80 | * Config the L3 Cache as L3 SRAM | |
81 | */ | |
82 | #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE | |
83 | #ifdef CONFIG_PHYS_64BIT | |
84 | #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \ | |
85 | CONFIG_RAMBOOT_TEXT_BASE) | |
86 | #else | |
87 | #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR | |
88 | #endif | |
89 | #define CONFIG_SYS_L3_SIZE (1024 << 10) | |
90 | #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) | |
91 | ||
4f1d1b7d MH |
92 | #ifdef CONFIG_PHYS_64BIT |
93 | #define CONFIG_SYS_DCSRBAR 0xf0000000 | |
94 | #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull | |
95 | #endif | |
96 | ||
97 | /* EEPROM */ | |
98 | #define CONFIG_ID_EEPROM | |
99 | #define CONFIG_SYS_I2C_EEPROM_NXID | |
100 | #define CONFIG_SYS_EEPROM_BUS_NUM 0 | |
101 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 | |
102 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
103 | ||
104 | /* | |
105 | * DDR Setup | |
106 | */ | |
107 | #define CONFIG_VERY_BIG_RAM | |
108 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
109 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
110 | ||
111 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
112 | #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) | |
113 | ||
114 | #define CONFIG_DDR_SPD | |
4f1d1b7d MH |
115 | |
116 | #define CONFIG_SYS_SPD_BUS_NUM 0 | |
117 | #define SPD_EEPROM_ADDRESS 0x52 | |
118 | #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ | |
119 | ||
120 | /* | |
121 | * Local Bus Definitions | |
122 | */ | |
123 | ||
124 | /* Set the local bus clock 1/8 of platform clock */ | |
125 | #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 | |
126 | ||
ca1b0b89 YS |
127 | /* |
128 | * This board doesn't have a promjet connector. | |
129 | * However, it uses commone corenet board LAW and TLB. | |
130 | * It is necessary to use the same start address with proper offset. | |
131 | */ | |
132 | #define CONFIG_SYS_FLASH_BASE 0xe0000000 | |
4f1d1b7d | 133 | #ifdef CONFIG_PHYS_64BIT |
ca1b0b89 | 134 | #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull |
4f1d1b7d MH |
135 | #else |
136 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE | |
137 | #endif | |
138 | ||
c9b2feaf | 139 | #define CONFIG_SYS_FLASH_BR_PRELIM \ |
ca1b0b89 YS |
140 | (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \ |
141 | BR_PS_16 | BR_V) | |
c9b2feaf SX |
142 | #define CONFIG_SYS_FLASH_OR_PRELIM \ |
143 | ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ | |
144 | | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) | |
4f1d1b7d MH |
145 | |
146 | #define CONFIG_FSL_CPLD | |
147 | #define CPLD_BASE 0xffdf0000 /* CPLD registers */ | |
148 | #ifdef CONFIG_PHYS_64BIT | |
149 | #define CPLD_BASE_PHYS 0xfffdf0000ull | |
150 | #else | |
151 | #define CPLD_BASE_PHYS CPLD_BASE | |
152 | #endif | |
153 | ||
154 | #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V) | |
155 | #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ | |
156 | ||
157 | #define PIXIS_LBMAP_SWITCH 7 | |
158 | #define PIXIS_LBMAP_MASK 0xf0 | |
159 | #define PIXIS_LBMAP_SHIFT 4 | |
160 | #define PIXIS_LBMAP_ALTBANK 0x40 | |
161 | ||
162 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
163 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
164 | ||
165 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
166 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
167 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Erase Timeout (ms) */ | |
168 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (ms) */ | |
169 | ||
170 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE | |
171 | ||
172 | #if defined(CONFIG_RAMBOOT_PBL) | |
173 | #define CONFIG_SYS_RAMBOOT | |
174 | #endif | |
175 | ||
c9b2feaf SX |
176 | #define CONFIG_NAND_FSL_ELBC |
177 | /* Nand Flash */ | |
178 | #ifdef CONFIG_NAND_FSL_ELBC | |
179 | #define CONFIG_SYS_NAND_BASE 0xffa00000 | |
180 | #ifdef CONFIG_PHYS_64BIT | |
181 | #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull | |
182 | #else | |
183 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE | |
184 | #endif | |
185 | ||
186 | #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} | |
187 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
c9b2feaf SX |
188 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) |
189 | ||
190 | /* NAND flash config */ | |
191 | #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | |
192 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | |
193 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
194 | | BR_MS_FCM /* MSEL = FCM */ \ | |
195 | | BR_V) /* valid */ | |
196 | #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ | |
197 | | OR_FCM_PGS /* Large Page*/ \ | |
198 | | OR_FCM_CSCT \ | |
199 | | OR_FCM_CST \ | |
200 | | OR_FCM_CHT \ | |
201 | | OR_FCM_SCY_1 \ | |
202 | | OR_FCM_TRLX \ | |
203 | | OR_FCM_EHTR) | |
204 | ||
88718be3 | 205 | #ifdef CONFIG_MTD_RAW_NAND |
c9b2feaf SX |
206 | #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ |
207 | #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ | |
208 | #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ | |
209 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ | |
210 | #else | |
211 | #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ | |
212 | #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ | |
213 | #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ | |
214 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ | |
215 | #endif | |
216 | #else | |
217 | #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ | |
218 | #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ | |
219 | #endif /* CONFIG_NAND_FSL_ELBC */ | |
220 | ||
4f1d1b7d MH |
221 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
222 | #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 | |
ca1b0b89 | 223 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} |
4f1d1b7d | 224 | |
4f1d1b7d MH |
225 | #define CONFIG_HWCONFIG |
226 | ||
227 | /* define to use L1 as initial stack */ | |
228 | #define CONFIG_L1_INIT_RAM | |
229 | #define CONFIG_SYS_INIT_RAM_LOCK | |
230 | #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ | |
231 | #ifdef CONFIG_PHYS_64BIT | |
232 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf | |
233 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR | |
234 | /* The assembler doesn't like typecast */ | |
235 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ | |
236 | ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ | |
237 | CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) | |
238 | #else | |
239 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR | |
240 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 | |
241 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS | |
242 | #endif | |
243 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 | |
244 | ||
245 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ | |
246 | GENERATED_GBL_DATA_SIZE) | |
247 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
248 | ||
9307cbab | 249 | #define CONFIG_SYS_MONITOR_LEN (768 * 1024) |
4f1d1b7d MH |
250 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) |
251 | ||
252 | /* Serial Port - controlled on board with jumper J8 | |
253 | * open - index 2 | |
254 | * shorted - index 1 | |
255 | */ | |
4f1d1b7d MH |
256 | #define CONFIG_SYS_NS16550_SERIAL |
257 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
258 | #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) | |
259 | ||
260 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
261 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} | |
262 | ||
263 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) | |
264 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) | |
265 | #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) | |
266 | #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) | |
267 | ||
4f1d1b7d | 268 | /* I2C */ |
2f3bb4ab | 269 | #ifndef CONFIG_DM_I2C |
00f792e0 | 270 | #define CONFIG_SYS_I2C |
00f792e0 HS |
271 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 |
272 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
2bd1aab0 | 273 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 |
00f792e0 HS |
274 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 |
275 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
2bd1aab0 | 276 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 |
2f3bb4ab BL |
277 | #else |
278 | #define CONFIG_I2C_SET_DEFAULT_BUS_NUM | |
279 | #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 | |
280 | #endif | |
281 | #define CONFIG_SYS_I2C_FSL | |
282 | ||
4f1d1b7d MH |
283 | |
284 | /* | |
285 | * RapidIO | |
286 | */ | |
287 | #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 | |
288 | #ifdef CONFIG_PHYS_64BIT | |
289 | #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull | |
290 | #else | |
291 | #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 | |
292 | #endif | |
293 | #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ | |
294 | ||
295 | #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 | |
296 | #ifdef CONFIG_PHYS_64BIT | |
297 | #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull | |
298 | #else | |
299 | #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 | |
300 | #endif | |
301 | #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ | |
302 | ||
ff65f126 LG |
303 | /* |
304 | * for slave u-boot IMAGE instored in master memory space, | |
305 | * PHYS must be aligned based on the SIZE | |
306 | */ | |
e4911815 LG |
307 | #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull |
308 | #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull | |
309 | #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ | |
310 | #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull | |
ff65f126 LG |
311 | /* |
312 | * for slave UCODE and ENV instored in master memory space, | |
313 | * PHYS must be aligned based on the SIZE | |
314 | */ | |
e4911815 | 315 | #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull |
b5f7c873 LG |
316 | #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull |
317 | #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ | |
ff65f126 LG |
318 | |
319 | /* slave core release by master*/ | |
b5f7c873 LG |
320 | #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 |
321 | #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ | |
ff65f126 LG |
322 | |
323 | /* | |
461632bd | 324 | * SRIO_PCIE_BOOT - SLAVE |
ff65f126 | 325 | */ |
461632bd LG |
326 | #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE |
327 | #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 | |
328 | #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ | |
329 | (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) | |
ff65f126 LG |
330 | #endif |
331 | ||
4f1d1b7d MH |
332 | /* |
333 | * eSPI - Enhanced SPI | |
334 | */ | |
4f1d1b7d MH |
335 | |
336 | /* | |
337 | * General PCI | |
338 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
339 | */ | |
340 | ||
341 | /* controller 1, direct to uli, tgtid 3, Base address 20000 */ | |
342 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 | |
4f1d1b7d | 343 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull |
4f1d1b7d | 344 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 |
4f1d1b7d | 345 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull |
4f1d1b7d MH |
346 | |
347 | /* controller 2, Slot 2, tgtid 2, Base address 201000 */ | |
348 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 | |
4f1d1b7d | 349 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull |
4f1d1b7d | 350 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 |
4f1d1b7d | 351 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull |
4f1d1b7d MH |
352 | |
353 | /* controller 3, Slot 1, tgtid 1, Base address 202000 */ | |
354 | #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 | |
4f1d1b7d | 355 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull |
4f1d1b7d | 356 | #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 |
4f1d1b7d | 357 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull |
4f1d1b7d MH |
358 | |
359 | /* Qman/Bman */ | |
4f1d1b7d MH |
360 | #define CONFIG_SYS_BMAN_NUM_PORTALS 10 |
361 | #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 | |
362 | #ifdef CONFIG_PHYS_64BIT | |
363 | #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull | |
364 | #else | |
365 | #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE | |
366 | #endif | |
367 | #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 | |
3fa66db4 JL |
368 | #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 |
369 | #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 | |
370 | #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE | |
371 | #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) | |
372 | #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ | |
373 | CONFIG_SYS_BMAN_CENA_SIZE) | |
374 | #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) | |
375 | #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 | |
4f1d1b7d MH |
376 | #define CONFIG_SYS_QMAN_NUM_PORTALS 10 |
377 | #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 | |
378 | #ifdef CONFIG_PHYS_64BIT | |
379 | #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull | |
380 | #else | |
381 | #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE | |
382 | #endif | |
383 | #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 | |
3fa66db4 JL |
384 | #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 |
385 | #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 | |
386 | #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE | |
387 | #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) | |
388 | #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ | |
389 | CONFIG_SYS_QMAN_CENA_SIZE) | |
390 | #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) | |
391 | #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 | |
4f1d1b7d MH |
392 | |
393 | #define CONFIG_SYS_DPAA_FMAN | |
394 | #define CONFIG_SYS_DPAA_PME | |
395 | /* Default address of microcode for the Linux Fman driver */ | |
4f1d1b7d MH |
396 | #if defined(CONFIG_SPIFLASH) |
397 | /* | |
398 | * env is stored at 0x100000, sector size is 0x10000, ucode is stored after | |
399 | * env, so we got 0x110000. | |
400 | */ | |
dcf1d774 | 401 | #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 |
4f1d1b7d MH |
402 | #elif defined(CONFIG_SDCARD) |
403 | /* | |
404 | * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is | |
e222b1f3 PK |
405 | * about 825KB (1650 blocks), Env is stored after the image, and the env size is |
406 | * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. | |
4f1d1b7d | 407 | */ |
dcf1d774 | 408 | #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) |
88718be3 | 409 | #elif defined(CONFIG_MTD_RAW_NAND) |
dcf1d774 | 410 | #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) |
461632bd | 411 | #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) |
ff65f126 LG |
412 | /* |
413 | * Slave has no ucode locally, it can fetch this from remote. When implementing | |
414 | * in two corenet boards, slave's ucode could be stored in master's memory | |
415 | * space, the address can be mapped from slave TLB->slave LAW-> | |
461632bd LG |
416 | * slave SRIO or PCIE outbound window->master inbound window-> |
417 | * master LAW->the ucode address in master's memory space. | |
ff65f126 | 418 | */ |
dcf1d774 | 419 | #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 |
4f1d1b7d | 420 | #else |
dcf1d774 | 421 | #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 |
4f1d1b7d | 422 | #endif |
f2717b47 TT |
423 | #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 |
424 | #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) | |
4f1d1b7d | 425 | |
4f1d1b7d | 426 | #ifdef CONFIG_PCI |
e617bb8d HZ |
427 | #if !defined(CONFIG_DM_PCI) |
428 | #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ | |
842033e6 | 429 | #define CONFIG_PCI_INDIRECT_BRIDGE |
e617bb8d HZ |
430 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 |
431 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ | |
432 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
433 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ | |
434 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 | |
435 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ | |
436 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 | |
437 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ | |
438 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 | |
439 | #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ | |
440 | #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 | |
441 | #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ | |
442 | #endif | |
4f1d1b7d MH |
443 | |
444 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
4f1d1b7d MH |
445 | #endif /* CONFIG_PCI */ |
446 | ||
aa7f281c | 447 | /* SATA */ |
9760b274 ZRR |
448 | #define CONFIG_FSL_SATA_V2 |
449 | ||
450 | #ifdef CONFIG_FSL_SATA_V2 | |
aa7f281c MH |
451 | #define CONFIG_SYS_SATA_MAX_DEVICE 2 |
452 | #define CONFIG_SATA1 | |
453 | #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR | |
454 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA | |
455 | #define CONFIG_SATA2 | |
456 | #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR | |
457 | #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA | |
458 | ||
459 | #define CONFIG_LBA48 | |
aa7f281c MH |
460 | #endif |
461 | ||
4f1d1b7d MH |
462 | #ifdef CONFIG_FMAN_ENET |
463 | #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2 | |
464 | #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3 | |
465 | #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4 | |
466 | #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1 | |
467 | #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0 | |
468 | ||
469 | #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c | |
470 | #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d | |
471 | #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e | |
472 | #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f | |
473 | ||
0787ecc0 MH |
474 | #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0 |
475 | ||
4f1d1b7d | 476 | #define CONFIG_SYS_TBIPA_VALUE 8 |
4f1d1b7d | 477 | #define CONFIG_ETHPRIME "FM1@DTSEC1" |
4f1d1b7d MH |
478 | #endif |
479 | ||
480 | /* | |
481 | * Environment | |
482 | */ | |
483 | #define CONFIG_LOADS_ECHO /* echo on for serial download */ | |
484 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ | |
485 | ||
486 | /* | |
487 | * Command line configuration. | |
488 | */ | |
4f1d1b7d | 489 | |
4f1d1b7d MH |
490 | /* |
491 | * USB | |
492 | */ | |
3d7506fa | 493 | #define CONFIG_HAS_FSL_DR_USB |
494 | #define CONFIG_HAS_FSL_MPH_USB | |
495 | ||
496 | #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) | |
4f1d1b7d MH |
497 | #define CONFIG_USB_EHCI_FSL |
498 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
3d7506fa | 499 | #endif |
500 | ||
4f1d1b7d | 501 | #ifdef CONFIG_MMC |
4f1d1b7d MH |
502 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR |
503 | #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT | |
4f1d1b7d | 504 | #endif |
737537ef | 505 | |
4f1d1b7d MH |
506 | /* |
507 | * Miscellaneous configurable options | |
508 | */ | |
4f1d1b7d | 509 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
4f1d1b7d MH |
510 | |
511 | /* | |
512 | * For booting Linux, the board info and command line data | |
513 | * have to be in the first 64 MB of memory, since this is | |
514 | * the maximum mapped by the Linux kernel during initialization. | |
515 | */ | |
516 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */ | |
517 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
518 | ||
519 | #ifdef CONFIG_CMD_KGDB | |
520 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
4f1d1b7d MH |
521 | #endif |
522 | ||
523 | /* | |
524 | * Environment Configuration | |
525 | */ | |
8b3637c6 | 526 | #define CONFIG_ROOTPATH "/opt/nfsroot" |
b3f44c21 | 527 | #define CONFIG_BOOTFILE "uImage" |
4f1d1b7d MH |
528 | #define CONFIG_UBOOTPATH u-boot.bin |
529 | ||
530 | /* default location for tftp and bootm */ | |
531 | #define CONFIG_LOADADDR 1000000 | |
532 | ||
4f1d1b7d MH |
533 | #define __USB_PHY_TYPE utmi |
534 | ||
535 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
536 | "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ | |
537 | "bank_intlv=cs0_cs1\0" \ | |
538 | "netdev=eth0\0" \ | |
5368c55d MV |
539 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ |
540 | "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ | |
4f1d1b7d MH |
541 | "tftpflash=tftpboot $loadaddr $uboot && " \ |
542 | "protect off $ubootaddr +$filesize && " \ | |
543 | "erase $ubootaddr +$filesize && " \ | |
544 | "cp.b $loadaddr $ubootaddr $filesize && " \ | |
545 | "protect on $ubootaddr +$filesize && " \ | |
546 | "cmp.b $loadaddr $ubootaddr $filesize\0" \ | |
547 | "consoledev=ttyS0\0" \ | |
5368c55d | 548 | "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ |
4f1d1b7d MH |
549 | "usb_dr_mode=host\0" \ |
550 | "ramdiskaddr=2000000\0" \ | |
551 | "ramdiskfile=p2041rdb/ramdisk.uboot\0" \ | |
b24a4f62 | 552 | "fdtaddr=1e00000\0" \ |
4f1d1b7d | 553 | "fdtfile=p2041rdb/p2041rdb.dtb\0" \ |
3246584d | 554 | "bdev=sda3\0" |
4f1d1b7d MH |
555 | |
556 | #define CONFIG_HDBOOT \ | |
557 | "setenv bootargs root=/dev/$bdev rw " \ | |
558 | "console=$consoledev,$baudrate $othbootargs;" \ | |
559 | "tftp $loadaddr $bootfile;" \ | |
560 | "tftp $fdtaddr $fdtfile;" \ | |
561 | "bootm $loadaddr - $fdtaddr" | |
562 | ||
563 | #define CONFIG_NFSBOOTCOMMAND \ | |
564 | "setenv bootargs root=/dev/nfs rw " \ | |
565 | "nfsroot=$serverip:$rootpath " \ | |
566 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
567 | "console=$consoledev,$baudrate $othbootargs;" \ | |
568 | "tftp $loadaddr $bootfile;" \ | |
569 | "tftp $fdtaddr $fdtfile;" \ | |
570 | "bootm $loadaddr - $fdtaddr" | |
571 | ||
572 | #define CONFIG_RAMBOOTCOMMAND \ | |
573 | "setenv bootargs root=/dev/ram rw " \ | |
574 | "console=$consoledev,$baudrate $othbootargs;" \ | |
575 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
576 | "tftp $loadaddr $bootfile;" \ | |
577 | "tftp $fdtaddr $fdtfile;" \ | |
578 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
579 | ||
580 | #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT | |
581 | ||
4f1d1b7d | 582 | #include <asm/fsl_secure_boot.h> |
4f1d1b7d MH |
583 | |
584 | #endif /* __CONFIG_H */ |