[people/ms/u-boot.git] / include / configs / P3G4.h

/*
 * (C) Copyright 2001
 * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#ifndef __ASSEMBLY__
#include <galileo/core.h>
#endif

#include "../board/evb64260/local.h"

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_P3G4		1	/* this is a P3G4  board	*/
#define CONFIG_SYS_GT_6426x        GT_64260 /* with a 64260 system controller */

#define CONFIG_BAUDRATE		115200	/* console baudrate = 115200	*/

#undef	CONFIG_ECC			/* enable ECC support */
/* #define CONFIG_EVB64260_750CX  1 */      /* Support the EVB-64260-750CX Board */

/* which initialization functions to call for this board */
#define CONFIG_MISC_INIT_R	1
#define CONFIG_BOARD_EARLY_INIT_F 1

#define CONFIG_SYS_BOARD_NAME		"P3G4"

#undef CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "

/*
 * The following defines let you select what serial you want to use
 * for your console driver.
 *
 * to use the MPSC, #define CONFIG_MPSC.  If you have wired up another
 * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
 */
#define	CONFIG_MPSC
#define CONFIG_MPSC_PORT	0

#define CONFIG_NET_MULTI        /* attempt all available adapters */

/* define this if you want to enable GT MAC filtering */
#define CONFIG_GT_USE_MAC_HASH_TABLE

#undef CONFIG_ETHER_PORT_MII	/* use RMII */

#if 0
#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
#else
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
#endif
#define CONFIG_ZERO_BOOTDELAY_CHECK

#define CONFIG_PREBOOT	"echo;"	\
	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"hostname=p3g4\0"						\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
	"flash_nfs=run nfsargs addip addtty;"				\
		"bootm ${kernel_addr}\0"				\
	"flash_self=run ramargs addip addtty;"				\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
	        "bootm\0"						\
	"rootpath=/opt/eldk/ppc_74xx\0"					\
	"bootfile=/tftpboot/p3g4/uImage\0"				\
	"kernel_addr=ff000000\0"					\
	"ramdisk_addr=ff010000\0"					\
	"load=tftp 100000 /tftpboot/p3g4/u-boot.bin\0"			\
	"update=protect off fff00000 fff3ffff;era fff00000 fff3ffff;"	\
		"cp.b 100000 fff00000 ${filesize};"			\
		"setenv filesize;saveenv\0"				\
	"upd=run load update\0"						\
	""
#define CONFIG_BOOTCOMMAND	"run flash_self"

#define CONFIG_LOADS_ECHO	0	/* echo off for serial download	*/
#define	CONFIG_SYS_LOADS_BAUD_CHANGE		/* allow baudrate changes	*/

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
#undef	CONFIG_ALTIVEC                  /* undef to disable             */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE


#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PCI
#define CONFIG_CMD_ELF
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_UNIVERSE
#define CONFIG_CMD_BSP


/*
 * Miscellaneous configurable options
 */
#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB)
#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x00400000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x00C00000	/* 4 ... 12 MB in DRAM	*/

#define	CONFIG_SYS_LOAD_ADDR		0x00300000	/* default load address	*/

#define	CONFIG_SYS_HZ			1000		/* decr freq: 1ms ticks	*/
#define CONFIG_SYS_BUS_CLK		133000000	/* 133 MHz		*/

#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }


/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area
 */
#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
#define	CONFIG_SYS_INIT_RAM_END	0x1000
#define	CONFIG_SYS_GBL_DATA_SIZE	128  /* size in bytes reserved for init data */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_RAM_LOCK


/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define	CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH_BASE		0xff000000
#define CONFIG_SYS_RESET_ADDRESS	0xfff00100
#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
#define	CONFIG_SYS_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc */

/* areas to map different things with the GT in physical space */
#define CONFIG_SYS_DRAM_BANKS		1
#define CONFIG_SYS_DFL_GT_REGS		0x14000000	/* boot time GT_REGS */

/* What to put in the bats. */
#define CONFIG_SYS_MISC_REGION_BASE	0xf0000000

/* Peripheral Device section */
#define CONFIG_SYS_GT_REGS		0xf8000000
#define CONFIG_SYS_DEV_BASE		0xff000000

#define CONFIG_SYS_DEV0_SPACE		CONFIG_SYS_DEV_BASE
#define CONFIG_SYS_DEV1_SPACE		(CONFIG_SYS_DEV0_SPACE + CONFIG_SYS_DEV0_SIZE)
#define CONFIG_SYS_DEV2_SPACE		(CONFIG_SYS_DEV1_SPACE + CONFIG_SYS_DEV1_SIZE)
#define CONFIG_SYS_DEV3_SPACE		(CONFIG_SYS_DEV2_SPACE + CONFIG_SYS_DEV2_SIZE)

#define CONFIG_SYS_DEV0_SIZE		 _8M /* Flash bank */
#define CONFIG_SYS_DEV1_SIZE		 0   /* unused */
#define CONFIG_SYS_DEV2_SIZE		 0   /* unused */
#define CONFIG_SYS_DEV3_SIZE		 0   /* unused */

#define CONFIG_SYS_16BIT_BOOT_PAR	0xc01b5e7c
#define CONFIG_SYS_DEV0_PAR		CONFIG_SYS_16BIT_BOOT_PAR

#if 0 /* Wrong?? NTL */
#define CONFIG_SYS_MPP_CONTROL_0	0x53541717	/* InitAct EOT[4] DBurst TCEn[1] */
						/* DMAAck[1:0] GNT0[1:0] */
#else
#define CONFIG_SYS_MPP_CONTROL_0	0x53547777	/* InitAct EOT[4] DBurst TCEn[1] */
						/* REQ0[1:0] GNT0[1:0] */
#endif
#define CONFIG_SYS_MPP_CONTROL_1	0x44009911	/* TCEn[4] TCTcnt[4] GPP[13:12] */
						/* DMAReq[4] DMAAck[4] WDNMI WDE */
#if 0 /* Wrong?? NTL */
#define CONFIG_SYS_MPP_CONTROL_2	0x40091818	/* TCTcnt[0] GPP[22:21] BClkIn */
						/* DMAAck[1:0] GNT1[1:0] */
#else
#define CONFIG_SYS_MPP_CONTROL_2	0x40098888	/* TCTcnt[0] */
						/* GPP[22] (RS232IntB or PCI1Int) */
						/* GPP[21] (RS323IntA) */
						/* BClkIn */
						/* REQ1[1:0] GNT1[1:0] */
#endif

#if 0 /* Wrong?? NTL */
# define CONFIG_SYS_MPP_CONTROL_3	0x00090066	/* GPP[31:29] BClkOut0 */
						/* GPP[27:26] Int[1:0] */
#else
# define CONFIG_SYS_MPP_CONTROL_3	0x22090066      /* MREQ MGNT */
						/* GPP[29]    (PCI1Int) */
						/* BClkOut0 */
						/* GPP[27]    (PCI0Int) */
						/* GPP[26]    (RtcInt or PCI1Int) */
						/* CPUInt[25:24] */
#endif

#define CONFIG_SYS_SERIAL_PORT_MUX	0x00001102	/* 11=MPSC1/MPSC0 02=ETH 0 and 2 RMII */

#if 0 /* Wrong?? - NTL */
# define CONFIG_SYS_GPP_LEVEL_CONTROL	0x000002c6
#else
# define CONFIG_SYS_GPP_LEVEL_CONTROL	0x2c600000	/* 0010 1100 0110 0000 */
						/* gpp[29] */
						/* gpp[27:26] */
						/* gpp[22:21] */

# define CONFIG_SYS_SDRAM_CONFIG	0xd8e18200	/* 0x448 */
				/* idmas use buffer 1,1
				   comm use buffer 0
				   pci use buffer 1,1
				   cpu use buffer 0
				   normal load (see also ifdef HVL)
				   standard SDRAM (see also ifdef REG)
				   non staggered refresh */
				/* 31:26  25 23  20 19 18 16 */
				/* 110110 00 111 0  0  00 1 */
				/* refresh_count=0x200
				   phisical interleaving disable
				   virtual interleaving enable */
				/* 15 14 13:0 */
				/* 1  0  0x200 */
#endif

#if 0
#define CONFIG_SYS_DUART_IO		CONFIG_SYS_DEV2_SPACE
#define CONFIG_SYS_DUART_CHAN		1		/* channel to use for console */
#endif
#undef CONFIG_SYS_INIT_CHAN1
#undef CONFIG_SYS_INIT_CHAN2
#if 0
#define SRAM_BASE		CONFIG_SYS_DEV0_SPACE
#define SRAM_SIZE		0x00100000		/* 1 MB of sram */
#endif


/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */

#define PCI_HOST_ADAPTER 0              /* configure ar pci adapter     */
#define PCI_HOST_FORCE  1               /* configure as pci host        */
#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */

#define CONFIG_PCI                      /* include pci support          */
#define CONFIG_PCI_HOST PCI_HOST_FORCE  /* select pci host function     */
#define CONFIG_PCI_PNP                  /* do pci plug-and-play         */

/* PCI MEMORY MAP section */
#define CONFIG_SYS_PCI0_MEM_BASE	0x80000000
#define CONFIG_SYS_PCI0_MEM_SIZE	_128M
#define CONFIG_SYS_PCI0_0_MEM_SPACE	(CONFIG_SYS_PCI0_MEM_BASE)

#define CONFIG_SYS_PCI1_MEM_BASE	0x88000000
#define CONFIG_SYS_PCI1_MEM_SIZE	_128M
#define CONFIG_SYS_PCI1_0_MEM_SPACE	(CONFIG_SYS_PCI1_MEM_BASE)

/* PCI I/O MAP section */
#define CONFIG_SYS_PCI0_IO_BASE	0xfa000000
#define CONFIG_SYS_PCI0_IO_SIZE	_16M
#define CONFIG_SYS_PCI0_IO_SPACE	(CONFIG_SYS_PCI0_IO_BASE)
#define CONFIG_SYS_PCI0_IO_SPACE_PCI	0x00000000

#define CONFIG_SYS_PCI1_IO_BASE	0xfb000000
#define CONFIG_SYS_PCI1_IO_SIZE	_16M
#define CONFIG_SYS_PCI1_IO_SPACE	(CONFIG_SYS_PCI1_IO_BASE)
#define CONFIG_SYS_PCI1_IO_SPACE_PCI	0x00000000

/*----------------------------------------------------------------------
 * Initial BAT mappings
 */

/* NOTES:
 * 1) GUARDED and WRITE_THRU not allowed in IBATS
 * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
 */

/* SDRAM */
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U

/* init ram */
#define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U

/* PCI0, PCI1 in one BAT */
#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS
#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)

/* GT regs, bootrom, all the devices, PCI I/O */
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U

/* I2C speed and slave address (for compatability) defaults */
#define CONFIG_SYS_I2C_SPEED	400000
#define CONFIG_SYS_I2C_SLAVE	0x7F

/* I2C addresses for the two DIMM SPD chips */
#ifndef CONFIG_EVB64260_750CX
#define DIMM0_I2C_ADDR	0x56
#define DIMM1_I2C_ADDR	0x54
#else /* CONFIG_EVB64260_750CX - only has 1 DIMM */
#define DIMM0_I2C_ADDR  0x54
#define DIMM1_I2C_ADDR	0x54
#endif

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define	CONFIG_SYS_BOOTMAPSZ		(8<<20)	/* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks	*/
#define CONFIG_SYS_MAX_FLASH_SECT	67	/* max number of sectors on one chip */

#define CONFIG_SYS_EXTRA_FLASH_DEVICE	BOOT_DEVICE
#define CONFIG_SYS_EXTRA_FLASH_WIDTH	2	/* 16 bit */
#define CONFIG_SYS_BOOT_FLASH_WIDTH	2	/* 16 bit */

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
#define CONFIG_SYS_FLASH_CFI		1

#define	CONFIG_ENV_IS_IN_FLASH	1
#define	CONFIG_ENV_SIZE		0x1000	/* Total Size of Environment Sector */
#define CONFIG_ENV_SECT_SIZE	0x20000
#define CONFIG_ENV_ADDR		0xFFFE0000

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	32	/* For all MPC74xx CPUs		 */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif

/*-----------------------------------------------------------------------
 * L2CR setup -- make sure this is right for your board!
 * look in include/74xx_7xx.h for the defines used here
 */

#define CONFIG_SYS_L2

#define L2_INIT		(L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
			 L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)

#define L2_ENABLE	(L2_INIT | L2CR_L2E)

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM	0x02		/* Software reboot		    */

#define CONFIG_SYS_BOARD_ASM_INIT      1


#endif	/* __CONFIG_H */
Commit	Line	Data
12f34241 WD	1	/*
	2	* (C) Copyright 2001
	3	* Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* board/config.h - configuration options, board specific
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
12f34241 WD	31	#ifndef __ASSEMBLY__
	32	#include <galileo/core.h>
	33	#endif
	34
	35	#include "../board/evb64260/local.h"
	36
	37	/*
	38	* High Level Configuration Options
	39	* (easy to change)
	40	*/
	41
	42	#define CONFIG_P3G4 1 /* this is a P3G4 board */
6d0f6bcf	43	#define CONFIG_SYS_GT_6426x GT_64260 /* with a 64260 system controller */
12f34241	44
53677ef1	45	#define CONFIG_BAUDRATE 115200 /* console baudrate = 115200 */
12f34241 WD	46
	47	#undef CONFIG_ECC /* enable ECC support */
	48	/* #define CONFIG_EVB64260_750CX 1 / / Support the EVB-64260-750CX Board */
	49
	50	/* which initialization functions to call for this board */
	51	#define CONFIG_MISC_INIT_R 1
c837dcb1	52	#define CONFIG_BOARD_EARLY_INIT_F 1
12f34241	53
6d0f6bcf	54	#define CONFIG_SYS_BOARD_NAME "P3G4"
12f34241	55
6d0f6bcf JCPV	56	#undef CONFIG_SYS_HUSH_PARSER
6d0f6bcf JCPV	57	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
12f34241 WD	58
	59	/*
	60	* The following defines let you select what serial you want to use
	61	* for your console driver.
	62	*
	63	* to use the MPSC, #define CONFIG_MPSC. If you have wired up another
	64	* mpsc channel, change CONFIG_MPSC_PORT to the desired value.
	65	*/
	66	#define CONFIG_MPSC
dcb2f95a	67	#define CONFIG_MPSC_PORT 0
12f34241 WD	68
	69	#define CONFIG_NET_MULTI /* attempt all available adapters */
	70
	71	/* define this if you want to enable GT MAC filtering */
	72	#define CONFIG_GT_USE_MAC_HASH_TABLE
	73
	74	#undef CONFIG_ETHER_PORT_MII /* use RMII */
	75
dcb2f95a	76	#if 0
12f34241 WD	77	#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
	78	#else
	79	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	80	#endif
	81	#define CONFIG_ZERO_BOOTDELAY_CHECK
	82
dcb2f95a	83	#define CONFIG_PREBOOT "echo;" \
32bf3d14	84	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
dcb2f95a SR	85	"echo"
dcb2f95a SR	86
12f34241	87	#undef CONFIG_BOOTARGS
dcb2f95a SR	88
	89	#define CONFIG_EXTRA_ENV_SETTINGS \
	90	"netdev=eth0\0" \
	91	"hostname=p3g4\0" \
	92	"nfsargs=setenv bootargs root=/dev/nfs rw " \
fe126d8b	93	"nfsroot=${serverip}:${rootpath}\0" \
dcb2f95a	94	"ramargs=setenv bootargs root=/dev/ram rw\0" \
fe126d8b WD	95	"addip=setenv bootargs ${bootargs} " \
	96	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	97	":${hostname}:${netdev}:off panic=1\0" \
	98	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
dcb2f95a	99	"flash_nfs=run nfsargs addip addtty;" \
fe126d8b	100	"bootm ${kernel_addr}\0" \
dcb2f95a	101	"flash_self=run ramargs addip addtty;" \
fe126d8b WD	102	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
fe126d8b WD	103	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
dcb2f95a SR	104	"bootm\0" \
	105	"rootpath=/opt/eldk/ppc_74xx\0" \
	106	"bootfile=/tftpboot/p3g4/uImage\0" \
	107	"kernel_addr=ff000000\0" \
	108	"ramdisk_addr=ff010000\0" \
	109	"load=tftp 100000 /tftpboot/p3g4/u-boot.bin\0" \
	110	"update=protect off fff00000 fff3ffff;era fff00000 fff3ffff;" \
fe126d8b	111	"cp.b 100000 fff00000 ${filesize};" \
dcb2f95a	112	"setenv filesize;saveenv\0" \
d8ab58b2	113	"upd=run load update\0" \
dcb2f95a SR	114	""
dcb2f95a SR	115	#define CONFIG_BOOTCOMMAND "run flash_self"
12f34241 WD	116
12f34241 WD	117	#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
6d0f6bcf	118	#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */
12f34241 WD	119
	120	#undef CONFIG_WATCHDOG /* watchdog disabled */
	121	#undef CONFIG_ALTIVEC /* undef to disable */
	122
18225e8d JL	123	/*
	124	* BOOTP options
	125	*/
	126	#define CONFIG_BOOTP_SUBNETMASK
	127	#define CONFIG_BOOTP_GATEWAY
	128	#define CONFIG_BOOTP_HOSTNAME
	129	#define CONFIG_BOOTP_BOOTPATH
	130	#define CONFIG_BOOTP_BOOTFILESIZE
	131
12f34241	132
149dded2	133	#define CONFIG_TIMESTAMP /* Print image info with timestamp */
12f34241	134
acf02697 JL	135
	136	/*
	137	* Command line configuration.
	138	*/
	139	#include <config_cmd_default.h>
	140
	141	#define CONFIG_CMD_ASKENV
	142	#define CONFIG_CMD_DHCP
	143	#define CONFIG_CMD_PCI
	144	#define CONFIG_CMD_ELF
	145	#define CONFIG_CMD_MII
	146	#define CONFIG_CMD_PING
	147	#define CONFIG_CMD_UNIVERSE
	148	#define CONFIG_CMD_BSP
	149
12f34241 WD	150
	151	/*
	152	* Miscellaneous configurable options
	153	*/
6d0f6bcf JCPV	154	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	155	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
acf02697	156	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	157	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
12f34241	158	#else
6d0f6bcf	159	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
12f34241	160	#endif
6d0f6bcf JCPV	161	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	162	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	163	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
12f34241	164
6d0f6bcf JCPV	165	#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
6d0f6bcf JCPV	166	#define CONFIG_SYS_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */
12f34241	167
6d0f6bcf	168	#define CONFIG_SYS_LOAD_ADDR 0x00300000 /* default load address */
12f34241	169
6d0f6bcf	170	#define CONFIG_SYS_HZ 1000 /* decr freq: 1ms ticks */
ee80fa7b	171	#define CONFIG_SYS_BUS_CLK 133000000 /* 133 MHz */
12f34241	172
6d0f6bcf	173	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
12f34241 WD	174
	175
	176	/*
	177	* Low Level Configuration Settings
	178	* (address mappings, register initial values, etc.)
	179	* You should know what you are doing if you make changes here.
	180	*/
	181
	182	/*-----------------------------------------------------------------------
	183	* Definitions for initial stack pointer and data area
	184	*/
6d0f6bcf JCPV	185	#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
	186	#define CONFIG_SYS_INIT_RAM_END 0x1000
	187	#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */
	188	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
	189	#define CONFIG_SYS_INIT_RAM_LOCK
12f34241 WD	190
	191
	192	/*-----------------------------------------------------------------------
	193	* Start addresses for the final memory configuration
	194	* (Set up by the startup code)
6d0f6bcf	195	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
12f34241	196	*/
6d0f6bcf JCPV	197	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	198	#define CONFIG_SYS_FLASH_BASE 0xff000000
	199	#define CONFIG_SYS_RESET_ADDRESS 0xfff00100
	200	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	201	#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
	202	#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */
12f34241 WD	203
12f34241 WD	204	/* areas to map different things with the GT in physical space */
6d0f6bcf JCPV	205	#define CONFIG_SYS_DRAM_BANKS 1
6d0f6bcf JCPV	206	#define CONFIG_SYS_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */
12f34241 WD	207
12f34241 WD	208	/* What to put in the bats. */
6d0f6bcf	209	#define CONFIG_SYS_MISC_REGION_BASE 0xf0000000
12f34241 WD	210
12f34241 WD	211	/* Peripheral Device section */
6d0f6bcf JCPV	212	#define CONFIG_SYS_GT_REGS 0xf8000000
6d0f6bcf JCPV	213	#define CONFIG_SYS_DEV_BASE 0xff000000
12f34241	214
6d0f6bcf JCPV	215	#define CONFIG_SYS_DEV0_SPACE CONFIG_SYS_DEV_BASE
	216	#define CONFIG_SYS_DEV1_SPACE (CONFIG_SYS_DEV0_SPACE + CONFIG_SYS_DEV0_SIZE)
	217	#define CONFIG_SYS_DEV2_SPACE (CONFIG_SYS_DEV1_SPACE + CONFIG_SYS_DEV1_SIZE)
	218	#define CONFIG_SYS_DEV3_SPACE (CONFIG_SYS_DEV2_SPACE + CONFIG_SYS_DEV2_SIZE)
12f34241	219
6d0f6bcf JCPV	220	#define CONFIG_SYS_DEV0_SIZE _8M /* Flash bank */
	221	#define CONFIG_SYS_DEV1_SIZE 0 /* unused */
	222	#define CONFIG_SYS_DEV2_SIZE 0 /* unused */
	223	#define CONFIG_SYS_DEV3_SIZE 0 /* unused */
12f34241	224
6d0f6bcf JCPV	225	#define CONFIG_SYS_16BIT_BOOT_PAR 0xc01b5e7c
6d0f6bcf JCPV	226	#define CONFIG_SYS_DEV0_PAR CONFIG_SYS_16BIT_BOOT_PAR
12f34241 WD	227
12f34241 WD	228	#if 0 /* Wrong?? NTL */
6d0f6bcf	229	#define CONFIG_SYS_MPP_CONTROL_0 0x53541717 /* InitAct EOT[4] DBurst TCEn[1] */
12f34241 WD	230	/* DMAAck[1:0] GNT0[1:0] */
12f34241 WD	231	#else
6d0f6bcf	232	#define CONFIG_SYS_MPP_CONTROL_0 0x53547777 /* InitAct EOT[4] DBurst TCEn[1] */
12f34241 WD	233	/* REQ0[1:0] GNT0[1:0] */
12f34241 WD	234	#endif
6d0f6bcf	235	#define CONFIG_SYS_MPP_CONTROL_1 0x44009911 /* TCEn[4] TCTcnt[4] GPP[13:12] */
12f34241 WD	236	/* DMAReq[4] DMAAck[4] WDNMI WDE */
12f34241 WD	237	#if 0 /* Wrong?? NTL */
6d0f6bcf	238	#define CONFIG_SYS_MPP_CONTROL_2 0x40091818 /* TCTcnt[0] GPP[22:21] BClkIn */
12f34241 WD	239	/* DMAAck[1:0] GNT1[1:0] */
12f34241 WD	240	#else
6d0f6bcf	241	#define CONFIG_SYS_MPP_CONTROL_2 0x40098888 /* TCTcnt[0] */
12f34241 WD	242	/* GPP[22] (RS232IntB or PCI1Int) */
	243	/* GPP[21] (RS323IntA) */
	244	/* BClkIn */
	245	/* REQ1[1:0] GNT1[1:0] */
	246	#endif
	247
	248	#if 0 /* Wrong?? NTL */
6d0f6bcf	249	# define CONFIG_SYS_MPP_CONTROL_3 0x00090066 /* GPP[31:29] BClkOut0 */
12f34241 WD	250	/* GPP[27:26] Int[1:0] */
12f34241 WD	251	#else
6d0f6bcf	252	# define CONFIG_SYS_MPP_CONTROL_3 0x22090066 /* MREQ MGNT */
12f34241 WD	253	/* GPP[29] (PCI1Int) */
	254	/* BClkOut0 */
	255	/* GPP[27] (PCI0Int) */
	256	/* GPP[26] (RtcInt or PCI1Int) */
	257	/* CPUInt[25:24] */
	258	#endif
	259
6d0f6bcf	260	#define CONFIG_SYS_SERIAL_PORT_MUX 0x00001102 /* 11=MPSC1/MPSC0 02=ETH 0 and 2 RMII */
12f34241 WD	261
12f34241 WD	262	#if 0 /* Wrong?? - NTL */
6d0f6bcf	263	# define CONFIG_SYS_GPP_LEVEL_CONTROL 0x000002c6
12f34241	264	#else
6d0f6bcf	265	# define CONFIG_SYS_GPP_LEVEL_CONTROL 0x2c600000 /* 0010 1100 0110 0000 */
12f34241 WD	266	/* gpp[29] */
	267	/* gpp[27:26] */
	268	/* gpp[22:21] */
	269
6d0f6bcf	270	# define CONFIG_SYS_SDRAM_CONFIG 0xd8e18200 /* 0x448 */
12f34241 WD	271	/* idmas use buffer 1,1
	272	comm use buffer 0
	273	pci use buffer 1,1
	274	cpu use buffer 0
	275	normal load (see also ifdef HVL)
	276	standard SDRAM (see also ifdef REG)
	277	non staggered refresh */
	278	/* 31:26 25 23 20 19 18 16 */
	279	/* 110110 00 111 0 0 00 1 */
	280	/* refresh_count=0x200
	281	phisical interleaving disable
	282	virtual interleaving enable */
	283	/* 15 14 13:0 */
	284	/* 1 0 0x200 */
	285	#endif
	286
	287	#if 0
6d0f6bcf JCPV	288	#define CONFIG_SYS_DUART_IO CONFIG_SYS_DEV2_SPACE
6d0f6bcf JCPV	289	#define CONFIG_SYS_DUART_CHAN 1 /* channel to use for console */
12f34241	290	#endif
6d0f6bcf JCPV	291	#undef CONFIG_SYS_INIT_CHAN1
6d0f6bcf JCPV	292	#undef CONFIG_SYS_INIT_CHAN2
12f34241	293	#if 0
6d0f6bcf	294	#define SRAM_BASE CONFIG_SYS_DEV0_SPACE
12f34241 WD	295	#define SRAM_SIZE 0x00100000 /* 1 MB of sram */
	296	#endif
	297
	298
	299	/*-----------------------------------------------------------------------
	300	* PCI stuff
	301	*-----------------------------------------------------------------------
	302	*/
	303
	304	#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
	305	#define PCI_HOST_FORCE 1 /* configure as pci host */
	306	#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
	307
	308	#define CONFIG_PCI /* include pci support */
	309	#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
	310	#define CONFIG_PCI_PNP /* do pci plug-and-play */
	311
	312	/* PCI MEMORY MAP section */
6d0f6bcf JCPV	313	#define CONFIG_SYS_PCI0_MEM_BASE 0x80000000
	314	#define CONFIG_SYS_PCI0_MEM_SIZE _128M
	315	#define CONFIG_SYS_PCI0_0_MEM_SPACE (CONFIG_SYS_PCI0_MEM_BASE)
dcb2f95a	316
6d0f6bcf JCPV	317	#define CONFIG_SYS_PCI1_MEM_BASE 0x88000000
	318	#define CONFIG_SYS_PCI1_MEM_SIZE _128M
	319	#define CONFIG_SYS_PCI1_0_MEM_SPACE (CONFIG_SYS_PCI1_MEM_BASE)
12f34241	320
12f34241	321	/* PCI I/O MAP section */
6d0f6bcf JCPV	322	#define CONFIG_SYS_PCI0_IO_BASE 0xfa000000
	323	#define CONFIG_SYS_PCI0_IO_SIZE _16M
	324	#define CONFIG_SYS_PCI0_IO_SPACE (CONFIG_SYS_PCI0_IO_BASE)
	325	#define CONFIG_SYS_PCI0_IO_SPACE_PCI 0x00000000
dcb2f95a	326
6d0f6bcf JCPV	327	#define CONFIG_SYS_PCI1_IO_BASE 0xfb000000
	328	#define CONFIG_SYS_PCI1_IO_SIZE _16M
	329	#define CONFIG_SYS_PCI1_IO_SPACE (CONFIG_SYS_PCI1_IO_BASE)
	330	#define CONFIG_SYS_PCI1_IO_SPACE_PCI 0x00000000
12f34241 WD	331
	332	/*----------------------------------------------------------------------
	333	* Initial BAT mappings
	334	*/
	335
	336	/* NOTES:
	337	* 1) GUARDED and WRITE_THRU not allowed in IBATS
	338	* 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
	339	*/
	340
	341	/* SDRAM */
6d0f6bcf JCPV	342	#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \| BATL_PP_RW \| BATL_CACHEINHIBIT)
	343	#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	344	#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE \| BATL_PP_RW \| BATL_CACHEINHIBIT \| BATL_GUARDEDSTORAGE)
	345	#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
12f34241 WD	346
12f34241 WD	347	/* init ram */
6d0f6bcf JCPV	348	#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR \| BATL_PP_RW \| BATL_MEMCOHERENCE)
	349	#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR \| BATU_BL_128K \| BATU_VS \| BATU_VP)
	350	#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
	351	#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
12f34241 WD	352
12f34241 WD	353	/* PCI0, PCI1 in one BAT */
6d0f6bcf JCPV	354	#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS
	355	#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
	356	#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE \| BATL_CACHEINHIBIT \| BATL_PP_RW \| BATL_GUARDEDSTORAGE)
	357	#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE \| BATU_BL_256M \| BATU_VS \| BATU_VP)
12f34241 WD	358
12f34241 WD	359	/* GT regs, bootrom, all the devices, PCI I/O */
6d0f6bcf JCPV	360	#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE \| BATL_CACHEINHIBIT \| BATL_PP_RW)
	361	#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE \| BATU_VS \| BATU_VP \| BATU_BL_256M)
	362	#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE \| BATL_CACHEINHIBIT \| BATL_PP_RW \| BATL_GUARDEDSTORAGE)
	363	#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
12f34241 WD	364
12f34241 WD	365	/* I2C speed and slave address (for compatability) defaults */
6d0f6bcf JCPV	366	#define CONFIG_SYS_I2C_SPEED 400000
6d0f6bcf JCPV	367	#define CONFIG_SYS_I2C_SLAVE 0x7F
12f34241 WD	368
	369	/* I2C addresses for the two DIMM SPD chips */
	370	#ifndef CONFIG_EVB64260_750CX
	371	#define DIMM0_I2C_ADDR 0x56
	372	#define DIMM1_I2C_ADDR 0x54
	373	#else /* CONFIG_EVB64260_750CX - only has 1 DIMM */
	374	#define DIMM0_I2C_ADDR 0x54
	375	#define DIMM1_I2C_ADDR 0x54
	376	#endif
	377
	378	/*
	379	* For booting Linux, the board info and command line data
	380	* have to be in the first 8 MB of memory, since this is
	381	* the maximum mapped by the Linux kernel during initialization.
	382	*/
6d0f6bcf	383	#define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */
12f34241 WD	384
	385	/*-----------------------------------------------------------------------
	386	* FLASH organization
	387	*/
6d0f6bcf JCPV	388	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
6d0f6bcf JCPV	389	#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
12f34241	390
6d0f6bcf JCPV	391	#define CONFIG_SYS_EXTRA_FLASH_DEVICE BOOT_DEVICE
	392	#define CONFIG_SYS_EXTRA_FLASH_WIDTH 2 /* 16 bit */
	393	#define CONFIG_SYS_BOOT_FLASH_WIDTH 2 /* 16 bit */
12f34241	394
6d0f6bcf JCPV	395	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
	396	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
	397	#define CONFIG_SYS_FLASH_CFI 1
12f34241	398
5a1aceb0	399	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	400	#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
	401	#define CONFIG_ENV_SECT_SIZE 0x20000
	402	#define CONFIG_ENV_ADDR 0xFFFE0000
12f34241 WD	403
	404	/*-----------------------------------------------------------------------
	405	* Cache Configuration
	406	*/
6d0f6bcf	407	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
acf02697	408	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	409	#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
12f34241 WD	410	#endif
	411
	412	/*-----------------------------------------------------------------------
	413	* L2CR setup -- make sure this is right for your board!
	414	* look in include/74xx_7xx.h for the defines used here
	415	*/
	416
6d0f6bcf	417	#define CONFIG_SYS_L2
12f34241	418
53677ef1 WD	419	#define L2_INIT (L2CR_L2SIZ_2M \| L2CR_L2CLK_3 \| L2CR_L2RAM_BURST \| \
53677ef1 WD	420	L2CR_L2OH_5 \| L2CR_L2CTL \| L2CR_L2WT)
12f34241 WD	421
	422	#define L2_ENABLE (L2_INIT \| L2CR_L2E)
	423
	424	/*
	425	* Internal Definitions
	426	*
	427	* Boot Flags
	428	*/
	429	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	430	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	431
6d0f6bcf	432	#define CONFIG_SYS_BOARD_ASM_INIT 1
12f34241 WD	433
	434
	435	#endif /* __CONFIG_H */