[people/ms/u-boot.git] / include / configs / P3G4.h

/*
 * (C) Copyright 2001
 * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#ifndef __ASSEMBLY__
#include <galileo/core.h>
#endif

#include "../board/evb64260/local.h"

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_P3G4		1	/* this is a P3G4  board	*/
#define CONFIG_SYS_GT_6426x        GT_64260 /* with a 64260 system controller */

#define	CONFIG_SYS_TEXT_BASE	0xfff00000

#define CONFIG_BAUDRATE		115200	/* console baudrate = 115200	*/

#undef	CONFIG_ECC			/* enable ECC support */
/* #define CONFIG_EVB64260_750CX  1 */      /* Support the EVB-64260-750CX Board */

/* which initialization functions to call for this board */
#define CONFIG_MISC_INIT_R	1
#define CONFIG_BOARD_EARLY_INIT_F 1

#define CONFIG_SYS_BOARD_NAME		"P3G4"

#undef CONFIG_SYS_HUSH_PARSER

/*
 * The following defines let you select what serial you want to use
 * for your console driver.
 *
 * to use the MPSC, #define CONFIG_MPSC.  If you have wired up another
 * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
 */
#define	CONFIG_MPSC
#define CONFIG_MPSC_PORT	0


/* define this if you want to enable GT MAC filtering */
#define CONFIG_GT_USE_MAC_HASH_TABLE

#undef CONFIG_ETHER_PORT_MII	/* use RMII */

#if 0
#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
#else
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
#endif
#define CONFIG_ZERO_BOOTDELAY_CHECK

#define CONFIG_PREBOOT	"echo;"	\
	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"hostname=p3g4\0"						\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
	"flash_nfs=run nfsargs addip addtty;"				\
		"bootm ${kernel_addr}\0"				\
	"flash_self=run ramargs addip addtty;"				\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
		"bootm\0"						\
	"rootpath=/opt/eldk/ppc_74xx\0"					\
	"bootfile=/tftpboot/p3g4/uImage\0"				\
	"kernel_addr=ff000000\0"					\
	"ramdisk_addr=ff010000\0"					\
	"load=tftp 100000 /tftpboot/p3g4/u-boot.bin\0"			\
	"update=protect off fff00000 fff3ffff;era fff00000 fff3ffff;"	\
		"cp.b 100000 fff00000 ${filesize};"			\
		"setenv filesize;saveenv\0"				\
	"upd=run load update\0"						\
	""
#define CONFIG_BOOTCOMMAND	"run flash_self"

#define CONFIG_LOADS_ECHO	0	/* echo off for serial download	*/
#define	CONFIG_SYS_LOADS_BAUD_CHANGE		/* allow baudrate changes	*/

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
#undef	CONFIG_ALTIVEC                  /* undef to disable             */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE


#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PCI
#define CONFIG_CMD_ELF
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_UNIVERSE
#define CONFIG_CMD_BSP


/*
 * Miscellaneous configurable options
 */
#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#if defined(CONFIG_CMD_KGDB)
#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x00400000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x00C00000	/* 4 ... 12 MB in DRAM	*/

#define	CONFIG_SYS_LOAD_ADDR		0x00300000	/* default load address	*/
#define CONFIG_SYS_BUS_CLK		133000000	/* 133 MHz		*/

#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }


/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area
 */
#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
#define	CONFIG_SYS_INIT_RAM_SIZE	0x1000
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_RAM_LOCK


/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define	CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH_BASE		0xff000000
#define CONFIG_SYS_RESET_ADDRESS	0xfff00100
#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
#define	CONFIG_SYS_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc */

/* areas to map different things with the GT in physical space */
#define CONFIG_SYS_DRAM_BANKS		1
#define CONFIG_SYS_DFL_GT_REGS		0x14000000	/* boot time GT_REGS */

/* What to put in the bats. */
#define CONFIG_SYS_MISC_REGION_BASE	0xf0000000

/* Peripheral Device section */
#define CONFIG_SYS_GT_REGS		0xf8000000
#define CONFIG_SYS_DEV_BASE		0xff000000

#define CONFIG_SYS_DEV0_SPACE		CONFIG_SYS_DEV_BASE
#define CONFIG_SYS_DEV1_SPACE		(CONFIG_SYS_DEV0_SPACE + CONFIG_SYS_DEV0_SIZE)
#define CONFIG_SYS_DEV2_SPACE		(CONFIG_SYS_DEV1_SPACE + CONFIG_SYS_DEV1_SIZE)
#define CONFIG_SYS_DEV3_SPACE		(CONFIG_SYS_DEV2_SPACE + CONFIG_SYS_DEV2_SIZE)

#define CONFIG_SYS_DEV0_SIZE		 _8M /* Flash bank */
#define CONFIG_SYS_DEV1_SIZE		 0   /* unused */
#define CONFIG_SYS_DEV2_SIZE		 0   /* unused */
#define CONFIG_SYS_DEV3_SIZE		 0   /* unused */

#define CONFIG_SYS_16BIT_BOOT_PAR	0xc01b5e7c
#define CONFIG_SYS_DEV0_PAR		CONFIG_SYS_16BIT_BOOT_PAR

#if 0 /* Wrong?? NTL */
#define CONFIG_SYS_MPP_CONTROL_0	0x53541717	/* InitAct EOT[4] DBurst TCEn[1] */
						/* DMAAck[1:0] GNT0[1:0] */
#else
#define CONFIG_SYS_MPP_CONTROL_0	0x53547777	/* InitAct EOT[4] DBurst TCEn[1] */
						/* REQ0[1:0] GNT0[1:0] */
#endif
#define CONFIG_SYS_MPP_CONTROL_1	0x44009911	/* TCEn[4] TCTcnt[4] GPP[13:12] */
						/* DMAReq[4] DMAAck[4] WDNMI WDE */
#if 0 /* Wrong?? NTL */
#define CONFIG_SYS_MPP_CONTROL_2	0x40091818	/* TCTcnt[0] GPP[22:21] BClkIn */
						/* DMAAck[1:0] GNT1[1:0] */
#else
#define CONFIG_SYS_MPP_CONTROL_2	0x40098888	/* TCTcnt[0] */
						/* GPP[22] (RS232IntB or PCI1Int) */
						/* GPP[21] (RS323IntA) */
						/* BClkIn */
						/* REQ1[1:0] GNT1[1:0] */
#endif

#if 0 /* Wrong?? NTL */
# define CONFIG_SYS_MPP_CONTROL_3	0x00090066	/* GPP[31:29] BClkOut0 */
						/* GPP[27:26] Int[1:0] */
#else
# define CONFIG_SYS_MPP_CONTROL_3	0x22090066      /* MREQ MGNT */
						/* GPP[29]    (PCI1Int) */
						/* BClkOut0 */
						/* GPP[27]    (PCI0Int) */
						/* GPP[26]    (RtcInt or PCI1Int) */
						/* CPUInt[25:24] */
#endif

#define CONFIG_SYS_SERIAL_PORT_MUX	0x00001102	/* 11=MPSC1/MPSC0 02=ETH 0 and 2 RMII */

#if 0 /* Wrong?? - NTL */
# define CONFIG_SYS_GPP_LEVEL_CONTROL	0x000002c6
#else
# define CONFIG_SYS_GPP_LEVEL_CONTROL	0x2c600000	/* 0010 1100 0110 0000 */
						/* gpp[29] */
						/* gpp[27:26] */
						/* gpp[22:21] */

# define CONFIG_SYS_SDRAM_CONFIG	0xd8e18200	/* 0x448 */
				/* idmas use buffer 1,1
				   comm use buffer 0
				   pci use buffer 1,1
				   cpu use buffer 0
				   normal load (see also ifdef HVL)
				   standard SDRAM (see also ifdef REG)
				   non staggered refresh */
				/* 31:26  25 23  20 19 18 16 */
				/* 110110 00 111 0  0  00 1 */
				/* refresh_count=0x200
				   phisical interleaving disable
				   virtual interleaving enable */
				/* 15 14 13:0 */
				/* 1  0  0x200 */
#endif

#if 0
#define CONFIG_SYS_DUART_IO		CONFIG_SYS_DEV2_SPACE
#define CONFIG_SYS_DUART_CHAN		1		/* channel to use for console */
#endif
#undef CONFIG_SYS_INIT_CHAN1
#undef CONFIG_SYS_INIT_CHAN2
#if 0
#define SRAM_BASE		CONFIG_SYS_DEV0_SPACE
#define SRAM_SIZE		0x00100000		/* 1 MB of sram */
#endif


/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */

#define PCI_HOST_ADAPTER 0              /* configure ar pci adapter     */
#define PCI_HOST_FORCE  1               /* configure as pci host        */
#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */

#define CONFIG_PCI                      /* include pci support          */
#define CONFIG_PCI_HOST PCI_HOST_FORCE  /* select pci host function     */
#define CONFIG_PCI_PNP                  /* do pci plug-and-play         */

/* PCI MEMORY MAP section */
#define CONFIG_SYS_PCI0_MEM_BASE	0x80000000
#define CONFIG_SYS_PCI0_MEM_SIZE	_128M
#define CONFIG_SYS_PCI0_0_MEM_SPACE	(CONFIG_SYS_PCI0_MEM_BASE)

#define CONFIG_SYS_PCI1_MEM_BASE	0x88000000
#define CONFIG_SYS_PCI1_MEM_SIZE	_128M
#define CONFIG_SYS_PCI1_0_MEM_SPACE	(CONFIG_SYS_PCI1_MEM_BASE)

/* PCI I/O MAP section */
#define CONFIG_SYS_PCI0_IO_BASE	0xfa000000
#define CONFIG_SYS_PCI0_IO_SIZE	_16M
#define CONFIG_SYS_PCI0_IO_SPACE	(CONFIG_SYS_PCI0_IO_BASE)
#define CONFIG_SYS_PCI0_IO_SPACE_PCI	0x00000000

#define CONFIG_SYS_PCI1_IO_BASE	0xfb000000
#define CONFIG_SYS_PCI1_IO_SIZE	_16M
#define CONFIG_SYS_PCI1_IO_SPACE	(CONFIG_SYS_PCI1_IO_BASE)
#define CONFIG_SYS_PCI1_IO_SPACE_PCI	0x00000000

/*----------------------------------------------------------------------
 * Initial BAT mappings
 */

/* NOTES:
 * 1) GUARDED and WRITE_THRU not allowed in IBATS
 * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
 */

/* SDRAM */
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U

/* init ram */
#define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U

/* PCI0, PCI1 in one BAT */
#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS
#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)

/* GT regs, bootrom, all the devices, PCI I/O */
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U

/* I2C speed and slave address (for compatability) defaults */
#define CONFIG_SYS_I2C_SPEED	400000
#define CONFIG_SYS_I2C_SLAVE	0x7F

/* I2C addresses for the two DIMM SPD chips */
#ifndef CONFIG_EVB64260_750CX
#define DIMM0_I2C_ADDR	0x56
#define DIMM1_I2C_ADDR	0x54
#else /* CONFIG_EVB64260_750CX - only has 1 DIMM */
#define DIMM0_I2C_ADDR  0x54
#define DIMM1_I2C_ADDR	0x54
#endif

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define	CONFIG_SYS_BOOTMAPSZ		(8<<20)	/* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks	*/
#define CONFIG_SYS_MAX_FLASH_SECT	67	/* max number of sectors on one chip */

#define CONFIG_SYS_EXTRA_FLASH_DEVICE	BOOT_DEVICE
#define CONFIG_SYS_EXTRA_FLASH_WIDTH	2	/* 16 bit */
#define CONFIG_SYS_BOOT_FLASH_WIDTH	2	/* 16 bit */

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
#define CONFIG_SYS_FLASH_CFI		1

#define	CONFIG_ENV_IS_IN_FLASH	1
#define	CONFIG_ENV_SIZE		0x1000	/* Total Size of Environment Sector */
#define CONFIG_ENV_SECT_SIZE	0x20000
#define CONFIG_ENV_ADDR		0xFFFE0000

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	32	/* For all MPC74xx CPUs		 */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif

/*-----------------------------------------------------------------------
 * L2CR setup -- make sure this is right for your board!
 * look in include/74xx_7xx.h for the defines used here
 */

#define CONFIG_SYS_L2

#define L2_INIT		(L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
			 L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)

#define L2_ENABLE	(L2_INIT | L2CR_L2E)

#define CONFIG_SYS_BOARD_ASM_INIT      1


#endif	/* __CONFIG_H */
Commit	Line	Data
12f34241 WD	1	/*
	2	* (C) Copyright 2001
	3	* Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
12f34241 WD	6	*/
	7
	8	/*
	9	* board/config.h - configuration options, board specific
	10	*/
	11
	12	#ifndef __CONFIG_H
	13	#define __CONFIG_H
	14
12f34241 WD	15	#ifndef __ASSEMBLY__
	16	#include <galileo/core.h>
	17	#endif
	18
	19	#include "../board/evb64260/local.h"
	20
	21	/*
	22	* High Level Configuration Options
	23	* (easy to change)
	24	*/
	25
	26	#define CONFIG_P3G4 1 /* this is a P3G4 board */
6d0f6bcf	27	#define CONFIG_SYS_GT_6426x GT_64260 /* with a 64260 system controller */
12f34241	28
2ae18241 WD	29	#define CONFIG_SYS_TEXT_BASE 0xfff00000
2ae18241 WD	30
53677ef1	31	#define CONFIG_BAUDRATE 115200 /* console baudrate = 115200 */
12f34241 WD	32
	33	#undef CONFIG_ECC /* enable ECC support */
	34	/* #define CONFIG_EVB64260_750CX 1 / / Support the EVB-64260-750CX Board */
	35
	36	/* which initialization functions to call for this board */
	37	#define CONFIG_MISC_INIT_R 1
c837dcb1	38	#define CONFIG_BOARD_EARLY_INIT_F 1
12f34241	39
6d0f6bcf	40	#define CONFIG_SYS_BOARD_NAME "P3G4"
12f34241	41
6d0f6bcf	42	#undef CONFIG_SYS_HUSH_PARSER
12f34241 WD	43
	44	/*
	45	* The following defines let you select what serial you want to use
	46	* for your console driver.
	47	*
	48	* to use the MPSC, #define CONFIG_MPSC. If you have wired up another
	49	* mpsc channel, change CONFIG_MPSC_PORT to the desired value.
	50	*/
	51	#define CONFIG_MPSC
dcb2f95a	52	#define CONFIG_MPSC_PORT 0
12f34241	53
12f34241 WD	54
	55	/* define this if you want to enable GT MAC filtering */
	56	#define CONFIG_GT_USE_MAC_HASH_TABLE
	57
	58	#undef CONFIG_ETHER_PORT_MII /* use RMII */
	59
dcb2f95a	60	#if 0
12f34241 WD	61	#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
	62	#else
	63	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	64	#endif
	65	#define CONFIG_ZERO_BOOTDELAY_CHECK
	66
dcb2f95a	67	#define CONFIG_PREBOOT "echo;" \
32bf3d14	68	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
dcb2f95a SR	69	"echo"
dcb2f95a SR	70
12f34241	71	#undef CONFIG_BOOTARGS
dcb2f95a SR	72
	73	#define CONFIG_EXTRA_ENV_SETTINGS \
	74	"netdev=eth0\0" \
	75	"hostname=p3g4\0" \
	76	"nfsargs=setenv bootargs root=/dev/nfs rw " \
fe126d8b	77	"nfsroot=${serverip}:${rootpath}\0" \
dcb2f95a	78	"ramargs=setenv bootargs root=/dev/ram rw\0" \
fe126d8b WD	79	"addip=setenv bootargs ${bootargs} " \
	80	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	81	":${hostname}:${netdev}:off panic=1\0" \
	82	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
dcb2f95a	83	"flash_nfs=run nfsargs addip addtty;" \
fe126d8b	84	"bootm ${kernel_addr}\0" \
dcb2f95a	85	"flash_self=run ramargs addip addtty;" \
fe126d8b WD	86	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
fe126d8b WD	87	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
93e14596	88	"bootm\0" \
dcb2f95a SR	89	"rootpath=/opt/eldk/ppc_74xx\0" \
	90	"bootfile=/tftpboot/p3g4/uImage\0" \
	91	"kernel_addr=ff000000\0" \
	92	"ramdisk_addr=ff010000\0" \
	93	"load=tftp 100000 /tftpboot/p3g4/u-boot.bin\0" \
	94	"update=protect off fff00000 fff3ffff;era fff00000 fff3ffff;" \
fe126d8b	95	"cp.b 100000 fff00000 ${filesize};" \
dcb2f95a	96	"setenv filesize;saveenv\0" \
d8ab58b2	97	"upd=run load update\0" \
dcb2f95a SR	98	""
dcb2f95a SR	99	#define CONFIG_BOOTCOMMAND "run flash_self"
12f34241 WD	100
12f34241 WD	101	#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
6d0f6bcf	102	#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */
12f34241 WD	103
	104	#undef CONFIG_WATCHDOG /* watchdog disabled */
	105	#undef CONFIG_ALTIVEC /* undef to disable */
	106
18225e8d JL	107	/*
	108	* BOOTP options
	109	*/
	110	#define CONFIG_BOOTP_SUBNETMASK
	111	#define CONFIG_BOOTP_GATEWAY
	112	#define CONFIG_BOOTP_HOSTNAME
	113	#define CONFIG_BOOTP_BOOTPATH
	114	#define CONFIG_BOOTP_BOOTFILESIZE
	115
12f34241	116
149dded2	117	#define CONFIG_TIMESTAMP /* Print image info with timestamp */
12f34241	118
acf02697 JL	119
	120	/*
	121	* Command line configuration.
	122	*/
	123	#include <config_cmd_default.h>
	124
	125	#define CONFIG_CMD_ASKENV
	126	#define CONFIG_CMD_DHCP
	127	#define CONFIG_CMD_PCI
	128	#define CONFIG_CMD_ELF
	129	#define CONFIG_CMD_MII
	130	#define CONFIG_CMD_PING
	131	#define CONFIG_CMD_UNIVERSE
	132	#define CONFIG_CMD_BSP
	133
12f34241 WD	134
	135	/*
	136	* Miscellaneous configurable options
	137	*/
6d0f6bcf	138	#define CONFIG_SYS_LONGHELP /* undef to save memory */
acf02697	139	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	140	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
12f34241	141	#else
6d0f6bcf	142	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
12f34241	143	#endif
6d0f6bcf JCPV	144	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	145	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	146	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
12f34241	147
6d0f6bcf JCPV	148	#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
6d0f6bcf JCPV	149	#define CONFIG_SYS_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */
12f34241	150
6d0f6bcf	151	#define CONFIG_SYS_LOAD_ADDR 0x00300000 /* default load address */
ee80fa7b	152	#define CONFIG_SYS_BUS_CLK 133000000 /* 133 MHz */
12f34241	153
6d0f6bcf	154	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
12f34241 WD	155
	156
	157	/*
	158	* Low Level Configuration Settings
	159	* (address mappings, register initial values, etc.)
	160	* You should know what you are doing if you make changes here.
	161	*/
	162
	163	/*-----------------------------------------------------------------------
	164	* Definitions for initial stack pointer and data area
	165	*/
6d0f6bcf	166	#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
553f0982	167	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
25ddd1fb	168	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	169	#define CONFIG_SYS_INIT_RAM_LOCK
12f34241 WD	170
	171
	172	/*-----------------------------------------------------------------------
	173	* Start addresses for the final memory configuration
	174	* (Set up by the startup code)
6d0f6bcf	175	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
12f34241	176	*/
6d0f6bcf JCPV	177	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	178	#define CONFIG_SYS_FLASH_BASE 0xff000000
	179	#define CONFIG_SYS_RESET_ADDRESS 0xfff00100
	180	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
14d0a02a	181	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
6d0f6bcf	182	#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */
12f34241 WD	183
12f34241 WD	184	/* areas to map different things with the GT in physical space */
6d0f6bcf JCPV	185	#define CONFIG_SYS_DRAM_BANKS 1
6d0f6bcf JCPV	186	#define CONFIG_SYS_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */
12f34241 WD	187
12f34241 WD	188	/* What to put in the bats. */
6d0f6bcf	189	#define CONFIG_SYS_MISC_REGION_BASE 0xf0000000
12f34241 WD	190
12f34241 WD	191	/* Peripheral Device section */
6d0f6bcf JCPV	192	#define CONFIG_SYS_GT_REGS 0xf8000000
6d0f6bcf JCPV	193	#define CONFIG_SYS_DEV_BASE 0xff000000
12f34241	194
6d0f6bcf JCPV	195	#define CONFIG_SYS_DEV0_SPACE CONFIG_SYS_DEV_BASE
	196	#define CONFIG_SYS_DEV1_SPACE (CONFIG_SYS_DEV0_SPACE + CONFIG_SYS_DEV0_SIZE)
	197	#define CONFIG_SYS_DEV2_SPACE (CONFIG_SYS_DEV1_SPACE + CONFIG_SYS_DEV1_SIZE)
	198	#define CONFIG_SYS_DEV3_SPACE (CONFIG_SYS_DEV2_SPACE + CONFIG_SYS_DEV2_SIZE)
12f34241	199
6d0f6bcf JCPV	200	#define CONFIG_SYS_DEV0_SIZE _8M /* Flash bank */
	201	#define CONFIG_SYS_DEV1_SIZE 0 /* unused */
	202	#define CONFIG_SYS_DEV2_SIZE 0 /* unused */
	203	#define CONFIG_SYS_DEV3_SIZE 0 /* unused */
12f34241	204
6d0f6bcf JCPV	205	#define CONFIG_SYS_16BIT_BOOT_PAR 0xc01b5e7c
6d0f6bcf JCPV	206	#define CONFIG_SYS_DEV0_PAR CONFIG_SYS_16BIT_BOOT_PAR
12f34241 WD	207
12f34241 WD	208	#if 0 /* Wrong?? NTL */
6d0f6bcf	209	#define CONFIG_SYS_MPP_CONTROL_0 0x53541717 /* InitAct EOT[4] DBurst TCEn[1] */
12f34241 WD	210	/* DMAAck[1:0] GNT0[1:0] */
12f34241 WD	211	#else
6d0f6bcf	212	#define CONFIG_SYS_MPP_CONTROL_0 0x53547777 /* InitAct EOT[4] DBurst TCEn[1] */
12f34241 WD	213	/* REQ0[1:0] GNT0[1:0] */
12f34241 WD	214	#endif
6d0f6bcf	215	#define CONFIG_SYS_MPP_CONTROL_1 0x44009911 /* TCEn[4] TCTcnt[4] GPP[13:12] */
12f34241 WD	216	/* DMAReq[4] DMAAck[4] WDNMI WDE */
12f34241 WD	217	#if 0 /* Wrong?? NTL */
6d0f6bcf	218	#define CONFIG_SYS_MPP_CONTROL_2 0x40091818 /* TCTcnt[0] GPP[22:21] BClkIn */
12f34241 WD	219	/* DMAAck[1:0] GNT1[1:0] */
12f34241 WD	220	#else
6d0f6bcf	221	#define CONFIG_SYS_MPP_CONTROL_2 0x40098888 /* TCTcnt[0] */
12f34241 WD	222	/* GPP[22] (RS232IntB or PCI1Int) */
	223	/* GPP[21] (RS323IntA) */
	224	/* BClkIn */
	225	/* REQ1[1:0] GNT1[1:0] */
	226	#endif
	227
	228	#if 0 /* Wrong?? NTL */
6d0f6bcf	229	# define CONFIG_SYS_MPP_CONTROL_3 0x00090066 /* GPP[31:29] BClkOut0 */
12f34241 WD	230	/* GPP[27:26] Int[1:0] */
12f34241 WD	231	#else
6d0f6bcf	232	# define CONFIG_SYS_MPP_CONTROL_3 0x22090066 /* MREQ MGNT */
12f34241 WD	233	/* GPP[29] (PCI1Int) */
	234	/* BClkOut0 */
	235	/* GPP[27] (PCI0Int) */
	236	/* GPP[26] (RtcInt or PCI1Int) */
	237	/* CPUInt[25:24] */
	238	#endif
	239
6d0f6bcf	240	#define CONFIG_SYS_SERIAL_PORT_MUX 0x00001102 /* 11=MPSC1/MPSC0 02=ETH 0 and 2 RMII */
12f34241 WD	241
12f34241 WD	242	#if 0 /* Wrong?? - NTL */
6d0f6bcf	243	# define CONFIG_SYS_GPP_LEVEL_CONTROL 0x000002c6
12f34241	244	#else
6d0f6bcf	245	# define CONFIG_SYS_GPP_LEVEL_CONTROL 0x2c600000 /* 0010 1100 0110 0000 */
12f34241 WD	246	/* gpp[29] */
	247	/* gpp[27:26] */
	248	/* gpp[22:21] */
	249
6d0f6bcf	250	# define CONFIG_SYS_SDRAM_CONFIG 0xd8e18200 /* 0x448 */
12f34241 WD	251	/* idmas use buffer 1,1
	252	comm use buffer 0
	253	pci use buffer 1,1
	254	cpu use buffer 0
	255	normal load (see also ifdef HVL)
	256	standard SDRAM (see also ifdef REG)
	257	non staggered refresh */
	258	/* 31:26 25 23 20 19 18 16 */
	259	/* 110110 00 111 0 0 00 1 */
	260	/* refresh_count=0x200
	261	phisical interleaving disable
	262	virtual interleaving enable */
	263	/* 15 14 13:0 */
	264	/* 1 0 0x200 */
	265	#endif
	266
	267	#if 0
6d0f6bcf JCPV	268	#define CONFIG_SYS_DUART_IO CONFIG_SYS_DEV2_SPACE
6d0f6bcf JCPV	269	#define CONFIG_SYS_DUART_CHAN 1 /* channel to use for console */
12f34241	270	#endif
6d0f6bcf JCPV	271	#undef CONFIG_SYS_INIT_CHAN1
6d0f6bcf JCPV	272	#undef CONFIG_SYS_INIT_CHAN2
12f34241	273	#if 0
6d0f6bcf	274	#define SRAM_BASE CONFIG_SYS_DEV0_SPACE
12f34241 WD	275	#define SRAM_SIZE 0x00100000 /* 1 MB of sram */
	276	#endif
	277
	278
	279	/*-----------------------------------------------------------------------
	280	* PCI stuff
	281	*-----------------------------------------------------------------------
	282	*/
	283
	284	#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
	285	#define PCI_HOST_FORCE 1 /* configure as pci host */
	286	#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
	287
	288	#define CONFIG_PCI /* include pci support */
	289	#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
	290	#define CONFIG_PCI_PNP /* do pci plug-and-play */
	291
	292	/* PCI MEMORY MAP section */
6d0f6bcf JCPV	293	#define CONFIG_SYS_PCI0_MEM_BASE 0x80000000
	294	#define CONFIG_SYS_PCI0_MEM_SIZE _128M
	295	#define CONFIG_SYS_PCI0_0_MEM_SPACE (CONFIG_SYS_PCI0_MEM_BASE)
dcb2f95a	296
6d0f6bcf JCPV	297	#define CONFIG_SYS_PCI1_MEM_BASE 0x88000000
	298	#define CONFIG_SYS_PCI1_MEM_SIZE _128M
	299	#define CONFIG_SYS_PCI1_0_MEM_SPACE (CONFIG_SYS_PCI1_MEM_BASE)
12f34241	300
12f34241	301	/* PCI I/O MAP section */
6d0f6bcf JCPV	302	#define CONFIG_SYS_PCI0_IO_BASE 0xfa000000
	303	#define CONFIG_SYS_PCI0_IO_SIZE _16M
	304	#define CONFIG_SYS_PCI0_IO_SPACE (CONFIG_SYS_PCI0_IO_BASE)
	305	#define CONFIG_SYS_PCI0_IO_SPACE_PCI 0x00000000
dcb2f95a	306
6d0f6bcf JCPV	307	#define CONFIG_SYS_PCI1_IO_BASE 0xfb000000
	308	#define CONFIG_SYS_PCI1_IO_SIZE _16M
	309	#define CONFIG_SYS_PCI1_IO_SPACE (CONFIG_SYS_PCI1_IO_BASE)
	310	#define CONFIG_SYS_PCI1_IO_SPACE_PCI 0x00000000
12f34241 WD	311
	312	/*----------------------------------------------------------------------
	313	* Initial BAT mappings
	314	*/
	315
	316	/* NOTES:
	317	* 1) GUARDED and WRITE_THRU not allowed in IBATS
	318	* 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
	319	*/
	320
	321	/* SDRAM */
6d0f6bcf JCPV	322	#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \| BATL_PP_RW \| BATL_CACHEINHIBIT)
	323	#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	324	#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE \| BATL_PP_RW \| BATL_CACHEINHIBIT \| BATL_GUARDEDSTORAGE)
	325	#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
12f34241 WD	326
12f34241 WD	327	/* init ram */
6d0f6bcf JCPV	328	#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR \| BATL_PP_RW \| BATL_MEMCOHERENCE)
	329	#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR \| BATU_BL_128K \| BATU_VS \| BATU_VP)
	330	#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
	331	#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
12f34241 WD	332
12f34241 WD	333	/* PCI0, PCI1 in one BAT */
6d0f6bcf JCPV	334	#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS
	335	#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
	336	#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE \| BATL_CACHEINHIBIT \| BATL_PP_RW \| BATL_GUARDEDSTORAGE)
	337	#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE \| BATU_BL_256M \| BATU_VS \| BATU_VP)
12f34241 WD	338
12f34241 WD	339	/* GT regs, bootrom, all the devices, PCI I/O */
6d0f6bcf JCPV	340	#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE \| BATL_CACHEINHIBIT \| BATL_PP_RW)
	341	#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE \| BATU_VS \| BATU_VP \| BATU_BL_256M)
	342	#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE \| BATL_CACHEINHIBIT \| BATL_PP_RW \| BATL_GUARDEDSTORAGE)
	343	#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
12f34241 WD	344
12f34241 WD	345	/* I2C speed and slave address (for compatability) defaults */
6d0f6bcf JCPV	346	#define CONFIG_SYS_I2C_SPEED 400000
6d0f6bcf JCPV	347	#define CONFIG_SYS_I2C_SLAVE 0x7F
12f34241 WD	348
	349	/* I2C addresses for the two DIMM SPD chips */
	350	#ifndef CONFIG_EVB64260_750CX
	351	#define DIMM0_I2C_ADDR 0x56
	352	#define DIMM1_I2C_ADDR 0x54
	353	#else /* CONFIG_EVB64260_750CX - only has 1 DIMM */
	354	#define DIMM0_I2C_ADDR 0x54
	355	#define DIMM1_I2C_ADDR 0x54
	356	#endif
	357
	358	/*
	359	* For booting Linux, the board info and command line data
	360	* have to be in the first 8 MB of memory, since this is
	361	* the maximum mapped by the Linux kernel during initialization.
	362	*/
6d0f6bcf	363	#define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */
12f34241 WD	364
	365	/*-----------------------------------------------------------------------
	366	* FLASH organization
	367	*/
6d0f6bcf JCPV	368	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
6d0f6bcf JCPV	369	#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
12f34241	370
6d0f6bcf JCPV	371	#define CONFIG_SYS_EXTRA_FLASH_DEVICE BOOT_DEVICE
	372	#define CONFIG_SYS_EXTRA_FLASH_WIDTH 2 /* 16 bit */
	373	#define CONFIG_SYS_BOOT_FLASH_WIDTH 2 /* 16 bit */
12f34241	374
6d0f6bcf JCPV	375	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
	376	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
	377	#define CONFIG_SYS_FLASH_CFI 1
12f34241	378
5a1aceb0	379	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	380	#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
	381	#define CONFIG_ENV_SECT_SIZE 0x20000
	382	#define CONFIG_ENV_ADDR 0xFFFE0000
12f34241 WD	383
	384	/*-----------------------------------------------------------------------
	385	* Cache Configuration
	386	*/
6d0f6bcf	387	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
acf02697	388	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	389	#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
12f34241 WD	390	#endif
	391
	392	/*-----------------------------------------------------------------------
	393	* L2CR setup -- make sure this is right for your board!
	394	* look in include/74xx_7xx.h for the defines used here
	395	*/
	396
6d0f6bcf	397	#define CONFIG_SYS_L2
12f34241	398
53677ef1 WD	399	#define L2_INIT (L2CR_L2SIZ_2M \| L2CR_L2CLK_3 \| L2CR_L2RAM_BURST \| \
53677ef1 WD	400	L2CR_L2OH_5 \| L2CR_L2CTL \| L2CR_L2WT)
12f34241 WD	401
	402	#define L2_ENABLE (L2_INIT \| L2CR_L2E)
	403
6d0f6bcf	404	#define CONFIG_SYS_BOARD_ASM_INIT 1
12f34241 WD	405
	406
	407	#endif /* __CONFIG_H */