]>
Commit | Line | Data |
---|---|---|
12f34241 WD |
1 | /* |
2 | * (C) Copyright 2001 | |
3 | * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * board/config.h - configuration options, board specific | |
26 | */ | |
27 | ||
28 | #ifndef __CONFIG_H | |
29 | #define __CONFIG_H | |
30 | ||
12f34241 WD |
31 | #ifndef __ASSEMBLY__ |
32 | #include <galileo/core.h> | |
33 | #endif | |
34 | ||
35 | #include "../board/evb64260/local.h" | |
36 | ||
37 | /* | |
38 | * High Level Configuration Options | |
39 | * (easy to change) | |
40 | */ | |
41 | ||
42 | #define CONFIG_P3G4 1 /* this is a P3G4 board */ | |
43 | #define CFG_GT_6426x GT_64260 /* with a 64260 system controller */ | |
44 | ||
45 | #define CONFIG_BAUDRATE 115200 /* console baudrate = 115200 */ | |
46 | ||
47 | #undef CONFIG_ECC /* enable ECC support */ | |
48 | /* #define CONFIG_EVB64260_750CX 1 */ /* Support the EVB-64260-750CX Board */ | |
49 | ||
50 | /* which initialization functions to call for this board */ | |
51 | #define CONFIG_MISC_INIT_R 1 | |
c837dcb1 | 52 | #define CONFIG_BOARD_EARLY_INIT_F 1 |
12f34241 WD |
53 | |
54 | #define CFG_BOARD_NAME "P3G4" | |
55 | ||
56 | #undef CFG_HUSH_PARSER | |
57 | #define CFG_PROMPT_HUSH_PS2 "> " | |
58 | ||
59 | /* | |
60 | * The following defines let you select what serial you want to use | |
61 | * for your console driver. | |
62 | * | |
63 | * to use the MPSC, #define CONFIG_MPSC. If you have wired up another | |
64 | * mpsc channel, change CONFIG_MPSC_PORT to the desired value. | |
65 | */ | |
66 | #define CONFIG_MPSC | |
dcb2f95a | 67 | #define CONFIG_MPSC_PORT 0 |
12f34241 WD |
68 | |
69 | #define CONFIG_NET_MULTI /* attempt all available adapters */ | |
70 | ||
71 | /* define this if you want to enable GT MAC filtering */ | |
72 | #define CONFIG_GT_USE_MAC_HASH_TABLE | |
73 | ||
74 | #undef CONFIG_ETHER_PORT_MII /* use RMII */ | |
75 | ||
dcb2f95a | 76 | #if 0 |
12f34241 WD |
77 | #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ |
78 | #else | |
79 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
80 | #endif | |
81 | #define CONFIG_ZERO_BOOTDELAY_CHECK | |
82 | ||
dcb2f95a | 83 | #define CONFIG_PREBOOT "echo;" \ |
32bf3d14 | 84 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
dcb2f95a SR |
85 | "echo" |
86 | ||
12f34241 | 87 | #undef CONFIG_BOOTARGS |
dcb2f95a SR |
88 | |
89 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
90 | "netdev=eth0\0" \ | |
91 | "hostname=p3g4\0" \ | |
92 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
fe126d8b | 93 | "nfsroot=${serverip}:${rootpath}\0" \ |
dcb2f95a | 94 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
fe126d8b WD |
95 | "addip=setenv bootargs ${bootargs} " \ |
96 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
97 | ":${hostname}:${netdev}:off panic=1\0" \ | |
98 | "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ | |
dcb2f95a | 99 | "flash_nfs=run nfsargs addip addtty;" \ |
fe126d8b | 100 | "bootm ${kernel_addr}\0" \ |
dcb2f95a | 101 | "flash_self=run ramargs addip addtty;" \ |
fe126d8b WD |
102 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
103 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ | |
dcb2f95a SR |
104 | "bootm\0" \ |
105 | "rootpath=/opt/eldk/ppc_74xx\0" \ | |
106 | "bootfile=/tftpboot/p3g4/uImage\0" \ | |
107 | "kernel_addr=ff000000\0" \ | |
108 | "ramdisk_addr=ff010000\0" \ | |
109 | "load=tftp 100000 /tftpboot/p3g4/u-boot.bin\0" \ | |
110 | "update=protect off fff00000 fff3ffff;era fff00000 fff3ffff;" \ | |
fe126d8b | 111 | "cp.b 100000 fff00000 ${filesize};" \ |
dcb2f95a | 112 | "setenv filesize;saveenv\0" \ |
d8ab58b2 | 113 | "upd=run load update\0" \ |
dcb2f95a SR |
114 | "" |
115 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
12f34241 WD |
116 | |
117 | #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ | |
118 | #define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */ | |
119 | ||
120 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
121 | #undef CONFIG_ALTIVEC /* undef to disable */ | |
122 | ||
18225e8d JL |
123 | /* |
124 | * BOOTP options | |
125 | */ | |
126 | #define CONFIG_BOOTP_SUBNETMASK | |
127 | #define CONFIG_BOOTP_GATEWAY | |
128 | #define CONFIG_BOOTP_HOSTNAME | |
129 | #define CONFIG_BOOTP_BOOTPATH | |
130 | #define CONFIG_BOOTP_BOOTFILESIZE | |
131 | ||
12f34241 | 132 | |
149dded2 | 133 | #define CONFIG_TIMESTAMP /* Print image info with timestamp */ |
12f34241 | 134 | |
acf02697 JL |
135 | |
136 | /* | |
137 | * Command line configuration. | |
138 | */ | |
139 | #include <config_cmd_default.h> | |
140 | ||
141 | #define CONFIG_CMD_ASKENV | |
142 | #define CONFIG_CMD_DHCP | |
143 | #define CONFIG_CMD_PCI | |
144 | #define CONFIG_CMD_ELF | |
145 | #define CONFIG_CMD_MII | |
146 | #define CONFIG_CMD_PING | |
147 | #define CONFIG_CMD_UNIVERSE | |
148 | #define CONFIG_CMD_BSP | |
149 | ||
12f34241 WD |
150 | |
151 | /* | |
152 | * Miscellaneous configurable options | |
153 | */ | |
154 | #define CFG_LONGHELP /* undef to save memory */ | |
155 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
acf02697 | 156 | #if defined(CONFIG_CMD_KGDB) |
12f34241 WD |
157 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
158 | #else | |
159 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
160 | #endif | |
161 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
162 | #define CFG_MAXARGS 16 /* max number of command args */ | |
163 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
164 | ||
165 | #define CFG_MEMTEST_START 0x00400000 /* memtest works on */ | |
166 | #define CFG_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */ | |
167 | ||
168 | #define CFG_LOAD_ADDR 0x00300000 /* default load address */ | |
169 | ||
170 | #define CFG_HZ 1000 /* decr freq: 1ms ticks */ | |
171 | #define CFG_BUS_HZ 133000000 /* 133 MHz */ | |
172 | #define CFG_BUS_CLK CFG_BUS_HZ | |
173 | ||
174 | #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } | |
175 | ||
176 | ||
177 | /* | |
178 | * Low Level Configuration Settings | |
179 | * (address mappings, register initial values, etc.) | |
180 | * You should know what you are doing if you make changes here. | |
181 | */ | |
182 | ||
183 | /*----------------------------------------------------------------------- | |
184 | * Definitions for initial stack pointer and data area | |
185 | */ | |
186 | #define CFG_INIT_RAM_ADDR 0x40000000 | |
187 | #define CFG_INIT_RAM_END 0x1000 | |
188 | #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */ | |
189 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
190 | #define CFG_INIT_RAM_LOCK | |
191 | ||
192 | ||
193 | /*----------------------------------------------------------------------- | |
194 | * Start addresses for the final memory configuration | |
195 | * (Set up by the startup code) | |
196 | * Please note that CFG_SDRAM_BASE _must_ start at 0 | |
197 | */ | |
198 | #define CFG_SDRAM_BASE 0x00000000 | |
2d5b561e | 199 | #define CFG_FLASH_BASE 0xff000000 |
12f34241 WD |
200 | #define CFG_RESET_ADDRESS 0xfff00100 |
201 | #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
202 | #define CFG_MONITOR_BASE TEXT_BASE | |
203 | #define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ | |
204 | ||
205 | /* areas to map different things with the GT in physical space */ | |
206 | #define CFG_DRAM_BANKS 1 | |
207 | #define CFG_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */ | |
208 | ||
209 | /* What to put in the bats. */ | |
210 | #define CFG_MISC_REGION_BASE 0xf0000000 | |
211 | ||
212 | /* Peripheral Device section */ | |
213 | #define CFG_GT_REGS 0xf8000000 | |
214 | #define CFG_DEV_BASE 0xff000000 | |
215 | ||
216 | #define CFG_DEV0_SPACE CFG_DEV_BASE | |
217 | #define CFG_DEV1_SPACE (CFG_DEV0_SPACE + CFG_DEV0_SIZE) | |
218 | #define CFG_DEV2_SPACE (CFG_DEV1_SPACE + CFG_DEV1_SIZE) | |
219 | #define CFG_DEV3_SPACE (CFG_DEV2_SPACE + CFG_DEV2_SIZE) | |
220 | ||
221 | #define CFG_DEV0_SIZE _8M /* Flash bank */ | |
222 | #define CFG_DEV1_SIZE 0 /* unused */ | |
223 | #define CFG_DEV2_SIZE 0 /* unused */ | |
224 | #define CFG_DEV3_SIZE 0 /* unused */ | |
225 | ||
226 | #define CFG_16BIT_BOOT_PAR 0xc01b5e7c | |
227 | #define CFG_DEV0_PAR CFG_16BIT_BOOT_PAR | |
228 | ||
229 | #if 0 /* Wrong?? NTL */ | |
230 | #define CFG_MPP_CONTROL_0 0x53541717 /* InitAct EOT[4] DBurst TCEn[1] */ | |
231 | /* DMAAck[1:0] GNT0[1:0] */ | |
232 | #else | |
233 | #define CFG_MPP_CONTROL_0 0x53547777 /* InitAct EOT[4] DBurst TCEn[1] */ | |
234 | /* REQ0[1:0] GNT0[1:0] */ | |
235 | #endif | |
236 | #define CFG_MPP_CONTROL_1 0x44009911 /* TCEn[4] TCTcnt[4] GPP[13:12] */ | |
237 | /* DMAReq[4] DMAAck[4] WDNMI WDE */ | |
238 | #if 0 /* Wrong?? NTL */ | |
239 | #define CFG_MPP_CONTROL_2 0x40091818 /* TCTcnt[0] GPP[22:21] BClkIn */ | |
240 | /* DMAAck[1:0] GNT1[1:0] */ | |
241 | #else | |
242 | #define CFG_MPP_CONTROL_2 0x40098888 /* TCTcnt[0] */ | |
243 | /* GPP[22] (RS232IntB or PCI1Int) */ | |
244 | /* GPP[21] (RS323IntA) */ | |
245 | /* BClkIn */ | |
246 | /* REQ1[1:0] GNT1[1:0] */ | |
247 | #endif | |
248 | ||
249 | #if 0 /* Wrong?? NTL */ | |
250 | # define CFG_MPP_CONTROL_3 0x00090066 /* GPP[31:29] BClkOut0 */ | |
251 | /* GPP[27:26] Int[1:0] */ | |
252 | #else | |
253 | # define CFG_MPP_CONTROL_3 0x22090066 /* MREQ MGNT */ | |
254 | /* GPP[29] (PCI1Int) */ | |
255 | /* BClkOut0 */ | |
256 | /* GPP[27] (PCI0Int) */ | |
257 | /* GPP[26] (RtcInt or PCI1Int) */ | |
258 | /* CPUInt[25:24] */ | |
259 | #endif | |
260 | ||
261 | #define CFG_SERIAL_PORT_MUX 0x00001102 /* 11=MPSC1/MPSC0 02=ETH 0 and 2 RMII */ | |
262 | ||
263 | #if 0 /* Wrong?? - NTL */ | |
264 | # define CFG_GPP_LEVEL_CONTROL 0x000002c6 | |
265 | #else | |
266 | # define CFG_GPP_LEVEL_CONTROL 0x2c600000 /* 0010 1100 0110 0000 */ | |
267 | /* gpp[29] */ | |
268 | /* gpp[27:26] */ | |
269 | /* gpp[22:21] */ | |
270 | ||
271 | # define CFG_SDRAM_CONFIG 0xd8e18200 /* 0x448 */ | |
272 | /* idmas use buffer 1,1 | |
273 | comm use buffer 0 | |
274 | pci use buffer 1,1 | |
275 | cpu use buffer 0 | |
276 | normal load (see also ifdef HVL) | |
277 | standard SDRAM (see also ifdef REG) | |
278 | non staggered refresh */ | |
279 | /* 31:26 25 23 20 19 18 16 */ | |
280 | /* 110110 00 111 0 0 00 1 */ | |
281 | /* refresh_count=0x200 | |
282 | phisical interleaving disable | |
283 | virtual interleaving enable */ | |
284 | /* 15 14 13:0 */ | |
285 | /* 1 0 0x200 */ | |
286 | #endif | |
287 | ||
288 | #if 0 | |
289 | #define CFG_DUART_IO CFG_DEV2_SPACE | |
290 | #define CFG_DUART_CHAN 1 /* channel to use for console */ | |
291 | #endif | |
292 | #undef CFG_INIT_CHAN1 | |
293 | #undef CFG_INIT_CHAN2 | |
294 | #if 0 | |
295 | #define SRAM_BASE CFG_DEV0_SPACE | |
296 | #define SRAM_SIZE 0x00100000 /* 1 MB of sram */ | |
297 | #endif | |
298 | ||
299 | ||
300 | /*----------------------------------------------------------------------- | |
301 | * PCI stuff | |
302 | *----------------------------------------------------------------------- | |
303 | */ | |
304 | ||
305 | #define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ | |
306 | #define PCI_HOST_FORCE 1 /* configure as pci host */ | |
307 | #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ | |
308 | ||
309 | #define CONFIG_PCI /* include pci support */ | |
310 | #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ | |
311 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
312 | ||
313 | /* PCI MEMORY MAP section */ | |
314 | #define CFG_PCI0_MEM_BASE 0x80000000 | |
315 | #define CFG_PCI0_MEM_SIZE _128M | |
dcb2f95a SR |
316 | #define CFG_PCI0_0_MEM_SPACE (CFG_PCI0_MEM_BASE) |
317 | ||
12f34241 WD |
318 | #define CFG_PCI1_MEM_BASE 0x88000000 |
319 | #define CFG_PCI1_MEM_SIZE _128M | |
12f34241 WD |
320 | #define CFG_PCI1_0_MEM_SPACE (CFG_PCI1_MEM_BASE) |
321 | ||
12f34241 WD |
322 | /* PCI I/O MAP section */ |
323 | #define CFG_PCI0_IO_BASE 0xfa000000 | |
324 | #define CFG_PCI0_IO_SIZE _16M | |
12f34241 WD |
325 | #define CFG_PCI0_IO_SPACE (CFG_PCI0_IO_BASE) |
326 | #define CFG_PCI0_IO_SPACE_PCI 0x00000000 | |
dcb2f95a SR |
327 | |
328 | #define CFG_PCI1_IO_BASE 0xfb000000 | |
329 | #define CFG_PCI1_IO_SIZE _16M | |
12f34241 WD |
330 | #define CFG_PCI1_IO_SPACE (CFG_PCI1_IO_BASE) |
331 | #define CFG_PCI1_IO_SPACE_PCI 0x00000000 | |
332 | ||
333 | /*---------------------------------------------------------------------- | |
334 | * Initial BAT mappings | |
335 | */ | |
336 | ||
337 | /* NOTES: | |
338 | * 1) GUARDED and WRITE_THRU not allowed in IBATS | |
339 | * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT | |
340 | */ | |
341 | ||
342 | /* SDRAM */ | |
343 | #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) | |
344 | #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
345 | #define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
346 | #define CFG_DBAT0U CFG_IBAT0U | |
347 | ||
348 | /* init ram */ | |
349 | #define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) | |
350 | #define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) | |
351 | #define CFG_DBAT1L CFG_IBAT1L | |
352 | #define CFG_DBAT1U CFG_IBAT1U | |
353 | ||
354 | /* PCI0, PCI1 in one BAT */ | |
355 | #define CFG_IBAT2L BATL_NO_ACCESS | |
356 | #define CFG_IBAT2U CFG_DBAT2U | |
357 | #define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) | |
358 | #define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
359 | ||
360 | /* GT regs, bootrom, all the devices, PCI I/O */ | |
361 | #define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW) | |
362 | #define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M) | |
363 | #define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) | |
364 | #define CFG_DBAT3U CFG_IBAT3U | |
365 | ||
366 | /* I2C speed and slave address (for compatability) defaults */ | |
367 | #define CFG_I2C_SPEED 400000 | |
368 | #define CFG_I2C_SLAVE 0x7F | |
369 | ||
370 | /* I2C addresses for the two DIMM SPD chips */ | |
371 | #ifndef CONFIG_EVB64260_750CX | |
372 | #define DIMM0_I2C_ADDR 0x56 | |
373 | #define DIMM1_I2C_ADDR 0x54 | |
374 | #else /* CONFIG_EVB64260_750CX - only has 1 DIMM */ | |
375 | #define DIMM0_I2C_ADDR 0x54 | |
376 | #define DIMM1_I2C_ADDR 0x54 | |
377 | #endif | |
378 | ||
379 | /* | |
380 | * For booting Linux, the board info and command line data | |
381 | * have to be in the first 8 MB of memory, since this is | |
382 | * the maximum mapped by the Linux kernel during initialization. | |
383 | */ | |
384 | #define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ | |
385 | ||
386 | /*----------------------------------------------------------------------- | |
387 | * FLASH organization | |
388 | */ | |
389 | #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ | |
390 | #define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ | |
391 | ||
2d5b561e | 392 | #define CFG_EXTRA_FLASH_DEVICE BOOT_DEVICE |
12f34241 WD |
393 | #define CFG_EXTRA_FLASH_WIDTH 2 /* 16 bit */ |
394 | #define CFG_BOOT_FLASH_WIDTH 2 /* 16 bit */ | |
395 | ||
396 | #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ | |
397 | #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
398 | #define CFG_FLASH_CFI 1 | |
399 | ||
400 | #define CFG_ENV_IS_IN_FLASH 1 | |
401 | #define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ | |
402 | #define CFG_ENV_SECT_SIZE 0x20000 | |
403 | #define CFG_ENV_ADDR 0xFFFE0000 | |
404 | ||
405 | /*----------------------------------------------------------------------- | |
406 | * Cache Configuration | |
407 | */ | |
408 | #define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ | |
acf02697 | 409 | #if defined(CONFIG_CMD_KGDB) |
12f34241 WD |
410 | #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
411 | #endif | |
412 | ||
413 | /*----------------------------------------------------------------------- | |
414 | * L2CR setup -- make sure this is right for your board! | |
415 | * look in include/74xx_7xx.h for the defines used here | |
416 | */ | |
417 | ||
418 | #define CFG_L2 | |
419 | ||
420 | #define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ | |
421 | L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) | |
422 | ||
423 | #define L2_ENABLE (L2_INIT | L2CR_L2E) | |
424 | ||
425 | /* | |
426 | * Internal Definitions | |
427 | * | |
428 | * Boot Flags | |
429 | */ | |
430 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
431 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
432 | ||
433 | #define CFG_BOARD_ASM_INIT 1 | |
434 | ||
435 | ||
436 | #endif /* __CONFIG_H */ |