[people/ms/u-boot.git] / include / configs / PCI405.h

/*
 * (C) Copyright 2007
 * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com
 *
 * (C) Copyright 2001-2004
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
#define CONFIG_PCI405		1	/* ...on a PCI405 board		*/

#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
#define CONFIG_MISC_INIT_R	1	/* call misc_init_r() on init	*/

#define CONFIG_SYS_CLK_FREQ	25000000 /* external frequency to pll	*/

#define CONFIG_BOARD_TYPES	1	/* support board types		*/

#define CONFIG_BAUDRATE		115200
#define CONFIG_BOOTDELAY	0	/* autoboot after 0 seconds	*/

#undef	CONFIG_BOOTARGS
#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"mem_linux=14336k\0"					        \
	"optargs=panic=0\0"					        \
	"ramargs=setenv bootargs mem=$mem_linux root=/dev/ram rw\0"	\
	"addcons=setenv bootargs $bootargs console=ttyS0,$baudrate $optargs\0" \
	""
#define	CONFIG_BOOTCOMMAND      "run ramargs;run addcons;loadpci"

#define CONFIG_PREBOOT                  /* enable preboot variable      */

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

#define CONFIG_MII		1	/* MII PHY management		*/
#define CONFIG_PHY_ADDR		0	/* PHY address			*/

#define CONFIG_RTC_M48T35A	1		/* ST Electronics M48 timekeeper */


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_PCI
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_ELF
#define CONFIG_CMD_DATE
#define CONFIG_CMD_I2C
#define CONFIG_CMD_BSP
#define CONFIG_CMD_EEPROM


#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/

#define CONFIG_PRAM		2048	/* reserve 2 MB "protected RAM" */

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory		*/
#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/

#define CFG_HUSH_PARSER			/* use "hush" command parser	*/
#ifdef	CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2	"> "
#endif

#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS	16		/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/

#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/

#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
#define CFG_BASE_BAUD	    691200

/* The following table includes the supported baudrates */
#define CFG_BAUDRATE_TABLE	\
	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
	 57600, 115200, 230400, 460800, 921600 }

#define CFG_LOAD_ADDR	0x100000	/* default load address */
#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */

#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */

#undef CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */

#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
#define PCI_HOST_FORCE	1		/* configure as pci host	*/
#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/

#define CONFIG_PCI			/* include pci support		*/
#define CONFIG_PCI_HOST PCI_HOST_ADAPTER /* select pci host function	*/
#undef	CONFIG_PCI_PNP			/* no pci plug-and-play		*/
					/* resource configuration	*/

#define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/

#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
#define CFG_PCI_SUBSYS_DEVICEID 0x0407	/* PCI Device ID: PCI-405	*/
#define CFG_PCI_CLASSCODE	0x0280	/* PCI Class Code: Network/Other*/
#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
#define CFG_PCI_PTM1MS	0xff000001	/* 16MB, enable hard-wired to 1 */
#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/

#if 0 /* test-only */
#define CFG_PCI_PTM2LA	0xffc00000	/* point to flash		*/
#define CFG_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
#else
#define CFG_PCI_PTM2LA	0xef600000	/* point to internal regs	*/
#define CFG_PCI_PTM2MS	0xffe00001	/* 2MB, enable			*/
#define CFG_PCI_PTM2PCI 0x00000000	/* Host: use this pci address	*/
#endif

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
#define CFG_SDRAM_BASE		0x00000000
#define CFG_FLASH_BASE		0xFFFD0000
#define CFG_MONITOR_BASE	CFG_FLASH_BASE
#define CFG_MONITOR_LEN		(192 * 1024)	/* Reserve 196 kB for Monitor	*/
#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
/*
 * The following defines are added for buggy IOP480 byte interface.
 * All other boards should use the standard values (CPCI405 etc.)
 */
#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/

#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */

#if 0 /* Use NVRAM for environment variables */
/*-----------------------------------------------------------------------
 * NVRAM organization
 */
#define CONFIG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
#define CONFIG_ENV_SIZE		0x0ff8		/* Size of Environment vars	*/
#define CONFIG_ENV_ADDR		\
	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-(CONFIG_ENV_SIZE+8))	/* Env	*/

#else /* Use EEPROM for environment variables */

#define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
#define CONFIG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
#define CONFIG_ENV_SIZE		0x400	/* 1024 bytes may be used for env vars*/
				   /* total size of a CAT24WC08 is 1024 bytes */
#endif

#define CFG_NVRAM_BASE_ADDR	0xf0200000		/* NVRAM base address	*/
#define CFG_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/

/*-----------------------------------------------------------------------
 * I2C EEPROM (CAT24WC16) for environment
 */
#define CONFIG_HARD_I2C			/* I2c with hardware support */
#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
#define CFG_I2C_SLAVE		0x7F

#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
/* mask of address bits that overflow into the "EEPROM chip address"	*/
#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
					/* 16 byte page write mode using*/
					/* last 4 bits of the address	*/
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
#define CFG_EEPROM_PAGE_WRITE_ENABLE

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */

#define FLASH_BASE0_PRELIM	0xFFE00000	/* FLASH bank #0	*/

/*-----------------------------------------------------------------------
 * External Bus Controller (EBC) Setup
 */

/* Memory Bank 0 (Flash Bank 0) initialization					*/
#define CFG_EBC_PB0AP		0x92015480
#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */

/* Memory Bank 1 (NVRAM/RTC) initialization					*/
#define CFG_EBC_PB1AP		0x01005280  /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1	*/
#define CFG_EBC_PB1CR		0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit	*/

/* Memory Bank 2 (CAN0, 1) initialization					*/
#define CFG_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
/*#define CFG_EBC_PB2AP		  0x038056C0  / * BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/

/* Memory Bank 3 (FPGA internal) initialization					*/
#define CFG_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
#define CFG_EBC_PB3CR		0xF041C000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=32bit */
#define CFG_FPGA_BASE_ADDR	0xF0400000

/*-----------------------------------------------------------------------
 * FPGA stuff
 */
/* FPGA internal regs */
#define CFG_FPGA_MODE		0x00
#define CFG_FPGA_STATUS		0x02
#define CFG_FPGA_TS		0x04
#define CFG_FPGA_TS_LOW		0x06
#define CFG_FPGA_TS_CAP0	0x10
#define CFG_FPGA_TS_CAP0_LOW	0x12
#define CFG_FPGA_TS_CAP1	0x14
#define CFG_FPGA_TS_CAP1_LOW	0x16
#define CFG_FPGA_TS_CAP2	0x18
#define CFG_FPGA_TS_CAP2_LOW	0x1a
#define CFG_FPGA_TS_CAP3	0x1c
#define CFG_FPGA_TS_CAP3_LOW	0x1e

/* FPGA Mode Reg */
#define CFG_FPGA_MODE_CF_RESET	0x0001
#define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100
#define CFG_FPGA_MODE_TS_IRQ_CLEAR  0x1000
#define CFG_FPGA_MODE_TS_CLEAR	0x2000

/* FPGA Status Reg */
#define CFG_FPGA_STATUS_DIP0	0x0001
#define CFG_FPGA_STATUS_DIP1	0x0002
#define CFG_FPGA_STATUS_DIP2	0x0004
#define CFG_FPGA_STATUS_FLASH	0x0008
#define CFG_FPGA_STATUS_TS_IRQ	0x1000

#define CFG_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
#define CFG_FPGA_MAX_SIZE	32*1024	    /* 32kByte is enough for XC2S15  */

/* FPGA program pin configuration */
#define CFG_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
#define CFG_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
#define CFG_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
#define CFG_FPGA_INIT		0x00400000  /* FPGA init pin (ppc input)     */
#define CFG_FPGA_DONE		0x00800000  /* FPGA done pin (ppc input)     */
/* new INIT and DONE pins since board revision 1.2 (for PPC405GPr support)   */
#define CFG_FPGA_INIT_V12	0x00008000  /* FPGA init pin (ppc input)     */
#define CFG_FPGA_DONE_V12	0x00010000  /* FPGA done pin (ppc input)     */

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in data cache)
 */
#if 0 /* test-only */
#define CFG_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */
#define CFG_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
#define CFG_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
#else
/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
#define CFG_TEMP_STACK_OCM	  1
/* On Chip Memory location */
#define CFG_OCM_DATA_ADDR	0xF8000000
#define CFG_OCM_DATA_SIZE	0x1000
#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/

#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
#endif

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

#endif	/* __CONFIG_H */
Commit	Line	Data
c609719b	1	/*
76d1466f MF	2	* (C) Copyright 2007
	3	* Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com
	4	*
a20b27a3	5	* (C) Copyright 2001-2004
76d1466f	6	* Stefan Roese, DENX Software Engineering, sr@denx.de.
c609719b WD	7	*
	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26
	27	/*
	28	* board/config.h - configuration options, board specific
	29	*/
	30
	31	#ifndef __CONFIG_H
	32	#define __CONFIG_H
	33
	34	/*
	35	* High Level Configuration Options
	36	* (easy to change)
	37	*/
c609719b	38	#define CONFIG_405GP 1 /* This is a PPC405 CPU */
c837dcb1 WD	39	#define CONFIG_4xx 1 /* ...member of PPC4xx family */
c837dcb1 WD	40	#define CONFIG_PCI405 1 /* ...on a PCI405 board */
c609719b	41
c837dcb1	42	#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
c609719b WD	43	#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() on init */
c609719b WD	44
c837dcb1	45	#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
c609719b	46
a20b27a3 SR	47	#define CONFIG_BOARD_TYPES 1 /* support board types */
a20b27a3 SR	48
d69b100e	49	#define CONFIG_BAUDRATE 115200
a20b27a3	50	#define CONFIG_BOOTDELAY 0 /* autoboot after 0 seconds */
c609719b WD	51
c609719b WD	52	#undef CONFIG_BOOTARGS
a20b27a3 SR	53	#define CONFIG_EXTRA_ENV_SETTINGS \
	54	"mem_linux=14336k\0" \
	55	"optargs=panic=0\0" \
	56	"ramargs=setenv bootargs mem=$mem_linux root=/dev/ram rw\0" \
76d1466f	57	"addcons=setenv bootargs $bootargs console=ttyS0,$baudrate $optargs\0" \
a20b27a3	58	""
76d1466f	59	#define CONFIG_BOOTCOMMAND "run ramargs;run addcons;loadpci"
a20b27a3 SR	60
a20b27a3 SR	61	#define CONFIG_PREBOOT /* enable preboot variable */
c609719b WD	62
	63	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	64	#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
	65
	66	#define CONFIG_MII 1 /* MII PHY management */
c837dcb1	67	#define CONFIG_PHY_ADDR 0 /* PHY address */
c609719b WD	68
	69	#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
	70
acf02697	71
a1aa0bb5 JL	72	/*
	73	* BOOTP options
	74	*/
	75	#define CONFIG_BOOTP_BOOTFILESIZE
	76	#define CONFIG_BOOTP_BOOTPATH
	77	#define CONFIG_BOOTP_GATEWAY
	78	#define CONFIG_BOOTP_HOSTNAME
	79
	80
acf02697 JL	81	/*
	82	* Command line configuration.
	83	*/
	84	#include <config_cmd_default.h>
	85
	86	#define CONFIG_CMD_PCI
	87	#define CONFIG_CMD_IRQ
	88	#define CONFIG_CMD_ELF
	89	#define CONFIG_CMD_DATE
	90	#define CONFIG_CMD_I2C
	91	#define CONFIG_CMD_BSP
	92	#define CONFIG_CMD_EEPROM
	93
c609719b	94
c837dcb1	95	#undef CONFIG_WATCHDOG /* watchdog disabled */
c609719b	96
c837dcb1	97	#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
c609719b	98
c837dcb1	99	#define CONFIG_PRAM 2048 /* reserve 2 MB "protected RAM" */
d69b100e	100
c609719b WD	101	/*
	102	* Miscellaneous configurable options
	103	*/
	104	#define CFG_LONGHELP /* undef to save memory */
	105	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	106
c837dcb1	107	#define CFG_HUSH_PARSER /* use "hush" command parser */
c609719b	108	#ifdef CFG_HUSH_PARSER
c837dcb1	109	#define CFG_PROMPT_HUSH_PS2 "> "
c609719b WD	110	#endif
c609719b WD	111
acf02697	112	#if defined(CONFIG_CMD_KGDB)
c837dcb1	113	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
c609719b	114	#else
c837dcb1	115	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
c609719b WD	116	#endif
	117	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	118	#define CFG_MAXARGS 16 /* max number of command args */
	119	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	120
c837dcb1	121	#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
c609719b	122
c837dcb1	123	#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
c609719b WD	124
	125	#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
	126	#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
	127
c837dcb1 WD	128	#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
	129	#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
	130	#define CFG_BASE_BAUD 691200
c609719b WD	131
c609719b WD	132	/* The following table includes the supported baudrates */
c837dcb1	133	#define CFG_BAUDRATE_TABLE \
8bde7f77 WD	134	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
8bde7f77 WD	135	57600, 115200, 230400, 460800, 921600 }
c609719b WD	136
	137	#define CFG_LOAD_ADDR 0x100000 /* default load address */
	138	#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
	139
c837dcb1	140	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
c609719b	141
d69b100e	142	#undef CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
c609719b	143
c837dcb1	144	#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
2853d29b	145
c609719b WD	146	/*-----------------------------------------------------------------------
	147	* PCI stuff
	148	*-----------------------------------------------------------------------
	149	*/
c837dcb1 WD	150	#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
	151	#define PCI_HOST_FORCE 1 /* configure as pci host */
	152	#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
c609719b	153
c837dcb1 WD	154	#define CONFIG_PCI /* include pci support */
	155	#define CONFIG_PCI_HOST PCI_HOST_ADAPTER /* select pci host function */
	156	#undef CONFIG_PCI_PNP /* no pci plug-and-play */
	157	/* resource configuration */
c609719b	158
c837dcb1	159	#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
c609719b	160
c837dcb1 WD	161	#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
	162	#define CFG_PCI_SUBSYS_DEVICEID 0x0407 /* PCI Device ID: PCI-405 */
	163	#define CFG_PCI_CLASSCODE 0x0280 /* PCI Class Code: Network/Other*/
	164	#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
	165	#define CFG_PCI_PTM1MS 0xff000001 /* 16MB, enable hard-wired to 1 */
	166	#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
c609719b WD	167
c609719b WD	168	#if 0 /* test-only */
c837dcb1 WD	169	#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
	170	#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
	171	#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
c609719b	172	#else
c837dcb1 WD	173	#define CFG_PCI_PTM2LA 0xef600000 /* point to internal regs */
	174	#define CFG_PCI_PTM2MS 0xffe00001 /* 2MB, enable */
	175	#define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
c609719b WD	176	#endif
	177
	178	/*-----------------------------------------------------------------------
	179	* Start addresses for the final memory configuration
	180	* (Set up by the startup code)
	181	* Please note that CFG_SDRAM_BASE _must_ start at 0
	182	*/
	183	#define CFG_SDRAM_BASE 0x00000000
	184	#define CFG_FLASH_BASE 0xFFFD0000
	185	#define CFG_MONITOR_BASE CFG_FLASH_BASE
	186	#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */
	187	#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
	188
	189	/*
	190	* For booting Linux, the board info and command line data
	191	* have to be in the first 8 MB of memory, since this is
	192	* the maximum mapped by the Linux kernel during initialization.
	193	*/
	194	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	195	/*-----------------------------------------------------------------------
	196	* FLASH organization
	197	*/
	198	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
	199	#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
	200
	201	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
	202	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
	203
c837dcb1 WD	204	#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
	205	#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
	206	#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
c609719b WD	207	/*
	208	* The following defines are added for buggy IOP480 byte interface.
	209	* All other boards should use the standard values (CPCI405 etc.)
	210	*/
c837dcb1 WD	211	#define CFG_FLASH_READ0 0x0000 /* 0 is standard */
	212	#define CFG_FLASH_READ1 0x0001 /* 1 is standard */
	213	#define CFG_FLASH_READ2 0x0002 /* 2 is standard */
c609719b	214
c837dcb1	215	#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
c609719b WD	216
	217	#if 0 /* Use NVRAM for environment variables */
	218	/*-----------------------------------------------------------------------
	219	* NVRAM organization
	220	*/
9314cee6	221	#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
0e8d1586 JCPV	222	#define CONFIG_ENV_SIZE 0x0ff8 /* Size of Environment vars */
	223	#define CONFIG_ENV_ADDR \
	224	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-(CONFIG_ENV_SIZE+8)) /* Env */
c609719b WD	225
	226	#else /* Use EEPROM for environment variables */
	227
bb1f8b4f	228	#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
0e8d1586 JCPV	229	#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
0e8d1586 JCPV	230	#define CONFIG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars*/
8bde7f77	231	/* total size of a CAT24WC08 is 1024 bytes */
c609719b WD	232	#endif
	233
	234	#define CFG_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */
	235	#define CFG_NVRAM_SIZE (321024) / NVRAM size */
	236
	237	/*-----------------------------------------------------------------------
	238	* I2C EEPROM (CAT24WC16) for environment
	239	*/
	240	#define CONFIG_HARD_I2C /* I2c with hardware support */
	241	#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
	242	#define CFG_I2C_SLAVE 0x7F
	243
	244	#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
c837dcb1 WD	245	#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
c837dcb1 WD	246	/* mask of address bits that overflow into the "EEPROM chip address" */
c609719b WD	247	#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
	248	#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
	249	/* 16 byte page write mode using*/
c837dcb1	250	/* last 4 bits of the address */
c609719b WD	251	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
	252	#define CFG_EEPROM_PAGE_WRITE_ENABLE
	253
c609719b WD	254	/*
	255	* Init Memory Controller:
	256	*
	257	* BR0/1 and OR0/1 (FLASH)
	258	*/
	259
	260	#define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */
	261
	262	/*-----------------------------------------------------------------------
	263	* External Bus Controller (EBC) Setup
	264	*/
	265
c837dcb1 WD	266	/* Memory Bank 0 (Flash Bank 0) initialization */
	267	#define CFG_EBC_PB0AP 0x92015480
	268	#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
c609719b	269
c837dcb1 WD	270	/* Memory Bank 1 (NVRAM/RTC) initialization */
	271	#define CFG_EBC_PB1AP 0x01005280 /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1 */
	272	#define CFG_EBC_PB1CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
c609719b	273
c837dcb1 WD	274	/* Memory Bank 2 (CAN0, 1) initialization */
	275	#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
	276	/#define CFG_EBC_PB2AP 0x038056C0 / BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
	277	#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
c609719b	278
c837dcb1 WD	279	/* Memory Bank 3 (FPGA internal) initialization */
	280	#define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
	281	#define CFG_EBC_PB3CR 0xF041C000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=32bit */
	282	#define CFG_FPGA_BASE_ADDR 0xF0400000
c609719b WD	283
	284	/*-----------------------------------------------------------------------
	285	* FPGA stuff
	286	*/
	287	/* FPGA internal regs */
c837dcb1 WD	288	#define CFG_FPGA_MODE 0x00
	289	#define CFG_FPGA_STATUS 0x02
	290	#define CFG_FPGA_TS 0x04
	291	#define CFG_FPGA_TS_LOW 0x06
	292	#define CFG_FPGA_TS_CAP0 0x10
	293	#define CFG_FPGA_TS_CAP0_LOW 0x12
	294	#define CFG_FPGA_TS_CAP1 0x14
	295	#define CFG_FPGA_TS_CAP1_LOW 0x16
	296	#define CFG_FPGA_TS_CAP2 0x18
	297	#define CFG_FPGA_TS_CAP2_LOW 0x1a
	298	#define CFG_FPGA_TS_CAP3 0x1c
	299	#define CFG_FPGA_TS_CAP3_LOW 0x1e
c609719b WD	300
c609719b WD	301	/* FPGA Mode Reg */
c837dcb1	302	#define CFG_FPGA_MODE_CF_RESET 0x0001
c609719b WD	303	#define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100
c609719b WD	304	#define CFG_FPGA_MODE_TS_IRQ_CLEAR 0x1000
c837dcb1	305	#define CFG_FPGA_MODE_TS_CLEAR 0x2000
c609719b WD	306
c609719b WD	307	/* FPGA Status Reg */
c837dcb1 WD	308	#define CFG_FPGA_STATUS_DIP0 0x0001
	309	#define CFG_FPGA_STATUS_DIP1 0x0002
	310	#define CFG_FPGA_STATUS_DIP2 0x0004
	311	#define CFG_FPGA_STATUS_FLASH 0x0008
	312	#define CFG_FPGA_STATUS_TS_IRQ 0x1000
c609719b	313
c837dcb1 WD	314	#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
c837dcb1 WD	315	#define CFG_FPGA_MAX_SIZE 321024 / 32kByte is enough for XC2S15 */
c609719b WD	316
c609719b WD	317	/* FPGA program pin configuration */
c837dcb1 WD	318	#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
	319	#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
	320	#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
	321	#define CFG_FPGA_INIT 0x00400000 /* FPGA init pin (ppc input) */
	322	#define CFG_FPGA_DONE 0x00800000 /* FPGA done pin (ppc input) */
a20b27a3 SR	323	/* new INIT and DONE pins since board revision 1.2 (for PPC405GPr support) */
	324	#define CFG_FPGA_INIT_V12 0x00008000 /* FPGA init pin (ppc input) */
	325	#define CFG_FPGA_DONE_V12 0x00010000 /* FPGA done pin (ppc input) */
c609719b WD	326
	327	/*-----------------------------------------------------------------------
	328	* Definitions for initial stack pointer and data area (in data cache)
	329	*/
a20b27a3	330	#if 0 /* test-only */
c837dcb1 WD	331	#define CFG_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
	332	#define CFG_INIT_RAM_ADDR 0x40000000 /* use data cache */
	333	#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
c609719b WD	334	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
c609719b WD	335	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
c837dcb1	336	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
a20b27a3 SR	337	#else
	338	/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
	339	#define CFG_TEMP_STACK_OCM 1
	340	/* On Chip Memory location */
	341	#define CFG_OCM_DATA_ADDR 0xF8000000
	342	#define CFG_OCM_DATA_SIZE 0x1000
	343	#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
	344	#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
	345
	346	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	347	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	348	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	349	#endif
c609719b	350
c609719b WD	351	/*
	352	* Internal Definitions
	353	*
	354	* Boot Flags
	355	*/
	356	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	357	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	358
	359	#endif /* __CONFIG_H */