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e2211743 | 1 | /* |
414eec35 | 2 | * (C) Copyright 2002-2005 |
e2211743 WD |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * | |
26 | * Configuration settings for the PCIPPC-2 board. | |
27 | * | |
28 | */ | |
29 | ||
30 | /* ------------------------------------------------------------------------- */ | |
31 | ||
32 | /* | |
33 | * board/config.h - configuration options, board specific | |
34 | */ | |
35 | ||
36 | #ifndef __CONFIG_H | |
37 | #define __CONFIG_H | |
38 | ||
39 | /* | |
40 | * High Level Configuration Options | |
41 | * (easy to change) | |
42 | */ | |
43 | ||
44 | #define CONFIG_PCIPPC2 1 /* this is a PCIPPC2 board */ | |
45 | ||
2ae18241 WD |
46 | #define CONFIG_SYS_TEXT_BASE 0xfff00000 |
47 | ||
c837dcb1 | 48 | #define CONFIG_BOARD_EARLY_INIT_F 1 |
e2211743 WD |
49 | #define CONFIG_MISC_INIT_R 1 |
50 | ||
51 | #define CONFIG_CONS_INDEX 1 | |
52 | #define CONFIG_BAUDRATE 9600 | |
e2211743 | 53 | |
e2211743 WD |
54 | #define CONFIG_PREBOOT "" |
55 | #define CONFIG_BOOTDELAY 5 | |
56 | ||
0aa27657 MV |
57 | #ifndef __ASSEMBLY__ |
58 | #include <galileo/core.h> | |
59 | #endif | |
60 | ||
18225e8d JL |
61 | /* |
62 | * BOOTP options | |
63 | */ | |
64 | #define CONFIG_BOOTP_SUBNETMASK | |
65 | #define CONFIG_BOOTP_GATEWAY | |
66 | #define CONFIG_BOOTP_HOSTNAME | |
67 | #define CONFIG_BOOTP_BOOTPATH | |
68 | #define CONFIG_BOOTP_BOOTFILESIZE | |
e2211743 WD |
69 | |
70 | #define CONFIG_MAC_PARTITION | |
71 | #define CONFIG_DOS_PARTITION | |
72 | ||
acf02697 JL |
73 | |
74 | /* | |
75 | * Command line configuration. | |
76 | */ | |
77 | #include <config_cmd_default.h> | |
78 | ||
79 | #define CONFIG_CMD_ASKENV | |
80 | #define CONFIG_CMD_BSP | |
81 | #define CONFIG_CMD_DATE | |
82 | #define CONFIG_CMD_DHCP | |
acf02697 JL |
83 | #define CONFIG_CMD_ELF |
84 | #define CONFIG_CMD_NFS | |
85 | #define CONFIG_CMD_PCI | |
86 | #define CONFIG_CMD_SNTP | |
e2211743 WD |
87 | |
88 | #define CONFIG_PCI 1 | |
89 | #define CONFIG_PCI_PNP 1 /* PCI plug-and-play */ | |
90 | ||
e2211743 WD |
91 | /* |
92 | * Miscellaneous configurable options | |
93 | */ | |
6d0f6bcf JCPV |
94 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
95 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
e2211743 | 96 | |
6d0f6bcf | 97 | #define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ |
6d0f6bcf | 98 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
e2211743 WD |
99 | |
100 | /* Print Buffer Size | |
101 | */ | |
6d0f6bcf | 102 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) |
e2211743 | 103 | |
6d0f6bcf JCPV |
104 | #define CONFIG_SYS_MAXARGS 64 /* max number of command args */ |
105 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
106 | #define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */ | |
e2211743 WD |
107 | |
108 | /*----------------------------------------------------------------------- | |
109 | * Start addresses for the final memory configuration | |
110 | * (Set up by the startup code) | |
6d0f6bcf | 111 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
e2211743 | 112 | */ |
6d0f6bcf JCPV |
113 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
114 | #define CONFIG_SYS_FLASH_BASE 0xFFF00000 | |
115 | #define CONFIG_SYS_FLASH_MAX_SIZE 0x00100000 | |
e2211743 WD |
116 | /* Maximum amount of RAM. |
117 | */ | |
6d0f6bcf | 118 | #define CONFIG_SYS_MAX_RAM_SIZE 0x20000000 /* 512Mb */ |
e2211743 | 119 | |
6d0f6bcf | 120 | #define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 |
e2211743 | 121 | |
14d0a02a | 122 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
e2211743 | 123 | |
6d0f6bcf JCPV |
124 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
125 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
e2211743 | 126 | |
6d0f6bcf JCPV |
127 | #if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_SDRAM_BASE && \ |
128 | CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_MAX_RAM_SIZE | |
129 | #define CONFIG_SYS_RAMBOOT | |
e2211743 | 130 | #else |
6d0f6bcf | 131 | #undef CONFIG_SYS_RAMBOOT |
e2211743 WD |
132 | #endif |
133 | ||
6d0f6bcf JCPV |
134 | #define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */ |
135 | #define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ | |
e2211743 WD |
136 | |
137 | /*----------------------------------------------------------------------- | |
138 | * Definitions for initial stack pointer and data area | |
139 | */ | |
140 | ||
6d0f6bcf | 141 | #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 |
553f0982 | 142 | #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 |
25ddd1fb | 143 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 144 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
e2211743 | 145 | |
6d0f6bcf | 146 | #define CONFIG_SYS_INIT_RAM_LOCK |
e2211743 WD |
147 | |
148 | /* | |
149 | * Temporary buffer for serial data until the real serial driver | |
150 | * is initialised (memtest will destroy this buffer) | |
151 | */ | |
6d0f6bcf JCPV |
152 | #define CONFIG_SYS_SCONSOLE_ADDR CONFIG_SYS_INIT_RAM_ADDR |
153 | #define CONFIG_SYS_SCONSOLE_SIZE 0x0002000 | |
e2211743 WD |
154 | |
155 | /* SDRAM 0 - 256MB | |
156 | */ | |
6d0f6bcf JCPV |
157 | #define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
158 | #define CONFIG_SYS_DBAT0U (CONFIG_SYS_SDRAM_BASE | \ | |
e2211743 WD |
159 | BATU_BL_256M | BATU_VS | BATU_VP) |
160 | /* SDRAM 1 - 256MB | |
161 | */ | |
6d0f6bcf | 162 | #define CONFIG_SYS_DBAT1L ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | \ |
e2211743 | 163 | BATL_PP_10 | BATL_MEMCOHERENCE) |
6d0f6bcf | 164 | #define CONFIG_SYS_DBAT1U ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | \ |
e2211743 WD |
165 | BATU_BL_256M | BATU_VS | BATU_VP) |
166 | ||
167 | /* Init RAM in the CPU DCache (no backing memory) | |
168 | */ | |
6d0f6bcf | 169 | #define CONFIG_SYS_DBAT2L (CONFIG_SYS_INIT_RAM_ADDR | \ |
e2211743 | 170 | BATL_PP_10 | BATL_MEMCOHERENCE) |
6d0f6bcf | 171 | #define CONFIG_SYS_DBAT2U (CONFIG_SYS_INIT_RAM_ADDR | \ |
e2211743 WD |
172 | BATU_BL_128K | BATU_VS | BATU_VP) |
173 | ||
174 | /* I/O and PCI memory at 0xf0000000 | |
175 | */ | |
6d0f6bcf JCPV |
176 | #define CONFIG_SYS_DBAT3L (0xf0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) |
177 | #define CONFIG_SYS_DBAT3U (0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP) | |
178 | ||
179 | #define CONFIG_SYS_IBAT0L CONFIG_SYS_DBAT0L | |
180 | #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U | |
181 | #define CONFIG_SYS_IBAT1L CONFIG_SYS_DBAT1L | |
182 | #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U | |
183 | #define CONFIG_SYS_IBAT2L CONFIG_SYS_DBAT2L | |
184 | #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U | |
185 | #define CONFIG_SYS_IBAT3L CONFIG_SYS_DBAT3L | |
186 | #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U | |
e2211743 WD |
187 | |
188 | /* | |
189 | * Low Level Configuration Settings | |
190 | * (address mappings, register initial values, etc.) | |
191 | * You should know what you are doing if you make changes here. | |
192 | * For the detail description refer to the PCIPPC2 user's manual. | |
193 | */ | |
6d0f6bcf | 194 | #define CONFIG_SYS_HZ 1000 |
ee80fa7b | 195 | #define CONFIG_SYS_BUS_CLK 100000000 /* bus speed - 100 mhz */ |
6d0f6bcf | 196 | #define CONFIG_SYS_CPU_CLK 300000000 |
e2211743 WD |
197 | |
198 | /* | |
199 | * For booting Linux, the board info and command line data | |
200 | * have to be in the first 8 MB of memory, since this is | |
201 | * the maximum mapped by the Linux kernel during initialization. | |
202 | */ | |
6d0f6bcf | 203 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
e2211743 WD |
204 | |
205 | /*----------------------------------------------------------------------- | |
206 | * FLASH organization | |
207 | */ | |
6d0f6bcf JCPV |
208 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */ |
209 | #define CONFIG_SYS_MAX_FLASH_SECT 16 /* Max number of sectors in one bank */ | |
e2211743 | 210 | |
6d0f6bcf JCPV |
211 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
212 | #define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ | |
e2211743 WD |
213 | |
214 | /* | |
215 | * Note: environment is not EMBEDDED in the U-Boot code. | |
216 | * It's stored in flash separately. | |
217 | */ | |
5a1aceb0 | 218 | #define CONFIG_ENV_IS_IN_FLASH 1 |
6d0f6bcf | 219 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x70000) |
0e8d1586 JCPV |
220 | #define CONFIG_ENV_SIZE 0x1000 /* Size of the Environment */ |
221 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* Size of the Environment Sector */ | |
e2211743 WD |
222 | |
223 | /*----------------------------------------------------------------------- | |
224 | * Cache Configuration | |
225 | */ | |
6d0f6bcf | 226 | #define CONFIG_SYS_CACHELINE_SIZE 32 |
acf02697 | 227 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 228 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
e2211743 WD |
229 | #endif |
230 | ||
231 | /* | |
232 | * L2 cache | |
233 | */ | |
6d0f6bcf | 234 | #undef CONFIG_SYS_L2 |
e2211743 | 235 | #define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ |
8bde7f77 | 236 | L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) |
e2211743 WD |
237 | #define L2_ENABLE (L2_INIT | L2CR_L2E) |
238 | ||
e2211743 WD |
239 | /*----------------------------------------------------------------------- |
240 | RTC m48t59 | |
241 | */ | |
242 | #define CONFIG_RTC_MK48T59 | |
243 | ||
244 | #define CONFIG_WATCHDOG | |
245 | ||
e2211743 WD |
246 | |
247 | #define CONFIG_EEPRO100 | |
6d0f6bcf | 248 | #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ |
e2211743 WD |
249 | #define CONFIG_TULIP |
250 | ||
251 | #endif /* __CONFIG_H */ |