[people/ms/u-boot.git] / include / configs / PCIPPC6.h

/*
 * (C) Copyright 2002-2005
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 *
 * Configuration settings for the PCIPPC-6 board.
 *
 */

/* ------------------------------------------------------------------------- */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_PCIPPC2		1	/* this is a PCIPPC2 board	*/

#define CONFIG_BOARD_EARLY_INIT_F 1
#define CONFIG_MISC_INIT_R	1

#define CONFIG_CONS_INDEX	1
#define CONFIG_BAUDRATE		9600
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

#define CONFIG_PREBOOT		""
#define CONFIG_BOOTDELAY	5

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE

#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_BSP
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ELF
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PCI
#define CONFIG_CMD_SCSI
#define CONFIG_CMD_SNTP


#define CONFIG_PCI		1
#define CONFIG_PCI_PNP		1	/* PCI plug-and-play */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/

#define CONFIG_SYS_HUSH_PARSER		1	/* use "hush" command parser	*/
#ifdef	CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
#endif
#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/

/* Print Buffer Size
 */
#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)

#define CONFIG_SYS_MAXARGS	64		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
#define CONFIG_SYS_LOAD_ADDR	0x00100000	/* Default load address		*/

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE	    0x00000000
#define CONFIG_SYS_FLASH_BASE	    0xFFF00000
#define CONFIG_SYS_FLASH_MAX_SIZE  0x00100000
/* Maximum amount of RAM.
 */
#define CONFIG_SYS_MAX_RAM_SIZE    0x20000000	/* 512Mb			*/

#define CONFIG_SYS_RESET_ADDRESS   0xFFF00100

#define CONFIG_SYS_MONITOR_BASE    TEXT_BASE

#define CONFIG_SYS_MONITOR_LEN	    (256 << 10) /* Reserve 256 kB for Monitor	*/
#define CONFIG_SYS_MALLOC_LEN	    (128 << 10) /* Reserve 128 kB for malloc()	*/

#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_SDRAM_BASE && \
    CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_MAX_RAM_SIZE
#define CONFIG_SYS_RAMBOOT
#else
#undef CONFIG_SYS_RAMBOOT
#endif

#define CONFIG_SYS_MEMTEST_START   0x00004000	/* memtest works on		*/
#define CONFIG_SYS_MEMTEST_END	    0x02000000	/* 0 ... 32 MB in DRAM		*/

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area
 */

/* Size in bytes reserved for initial data
 */
#define CONFIG_SYS_GBL_DATA_SIZE    128

#define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
#define CONFIG_SYS_INIT_RAM_END      0x8000
#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET    CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_INIT_RAM_LOCK

/*
 * Temporary buffer for serial data until the real serial driver
 * is initialised (memtest will destroy this buffer)
 */
#define CONFIG_SYS_SCONSOLE_ADDR     CONFIG_SYS_INIT_RAM_ADDR
#define CONFIG_SYS_SCONSOLE_SIZE     0x0002000

/* SDRAM 0 - 256MB
 */
#define CONFIG_SYS_DBAT0L	      (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_DBAT0U	      (CONFIG_SYS_SDRAM_BASE | \
			       BATU_BL_256M | BATU_VS | BATU_VP)
/* SDRAM 1 - 256MB
 */
#define CONFIG_SYS_DBAT1L	      ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | \
			       BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_DBAT1U	      ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | \
			       BATU_BL_256M | BATU_VS | BATU_VP)

/* Init RAM in the CPU DCache (no backing memory)
 */
#define CONFIG_SYS_DBAT2L	      (CONFIG_SYS_INIT_RAM_ADDR | \
			       BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_DBAT2U	      (CONFIG_SYS_INIT_RAM_ADDR | \
			       BATU_BL_128K | BATU_VS | BATU_VP)

/* I/O and PCI memory at 0xf0000000
 */
#define CONFIG_SYS_DBAT3L	      (0xf0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
#define CONFIG_SYS_DBAT3U	      (0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP)

#define CONFIG_SYS_IBAT0L	      CONFIG_SYS_DBAT0L
#define CONFIG_SYS_IBAT0U	      CONFIG_SYS_DBAT0U
#define CONFIG_SYS_IBAT1L	      CONFIG_SYS_DBAT1L
#define CONFIG_SYS_IBAT1U	      CONFIG_SYS_DBAT1U
#define CONFIG_SYS_IBAT2L	      CONFIG_SYS_DBAT2L
#define CONFIG_SYS_IBAT2U	      CONFIG_SYS_DBAT2U
#define CONFIG_SYS_IBAT3L	      CONFIG_SYS_DBAT3L
#define CONFIG_SYS_IBAT3U	      CONFIG_SYS_DBAT3U

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 * For the detail description refer to the PCIPPC2 user's manual.
 */
#define CONFIG_SYS_HZ		      1000
#define CONFIG_SYS_BUS_HZ	      100000000 /* bus speed - 100 mhz		*/
#define CONFIG_SYS_CPU_CLK	      300000000
#define CONFIG_SYS_BUS_CLK	      100000000

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	      (8 << 20) /* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* Max number of flash banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	16	/* Max number of sectors in one bank	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/

/*
 * Note: environment is not EMBEDDED in the U-Boot code.
 * It's stored in flash separately.
 */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x70000)
#define CONFIG_ENV_SIZE		0x1000	/* Size of the Environment		*/
#define CONFIG_ENV_SECT_SIZE	0x10000 /* Size of the Environment Sector	*/

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	32
#if defined(CONFIG_CMD_KGDB)
#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
#endif

/*
 * L2 cache
 */
#undef CONFIG_SYS_L2
#define L2_INIT	  (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
		   L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
#define L2_ENABLE (L2_INIT | L2CR_L2E)

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM		0x02	/* Software reboot			*/

/*-----------------------------------------------------------------------
  RTC m48t59
*/
#define CONFIG_RTC_MK48T59

#define CONFIG_WATCHDOG

#define CONFIG_NET_MULTI		/* Multi ethernet cards support */

#define CONFIG_EEPRO100
#define CONFIG_SYS_RX_ETH_BUFFER	8               /* use 8 rx buffer on eepro100  */
#define CONFIG_TULIP


#define CONFIG_SCSI_SYM53C8XX
#define CONFIG_SCSI_DEV_ID	0x000B	/* 53c896 */
#define CONFIG_SYS_SCSI_MAX_LUN	8	/* number of supported LUNs */
#define CONFIG_SYS_SCSI_MAX_SCSI_ID	15	/* maximum SCSI ID (0..6) */
#define CONFIG_SYS_SCSI_MAX_DEVICE	CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN /* maximum Target devices */
#define CONFIG_SYS_SCSI_SPIN_UP_TIME	2
#define CONFIG_SYS_SCSI_SCAN_BUS_REVERSE 0
#define CONFIG_DOS_PARTITION
#define CONFIG_MAC_PARTITION
#define CONFIG_ISO_PARTITION

#endif	/* __CONFIG_H */
Commit	Line	Data
e2211743	1	/*
414eec35	2	* (C) Copyright 2002-2005
e2211743 WD	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	*
	26	* Configuration settings for the PCIPPC-6 board.
	27	*
	28	*/
	29
	30	/* ------------------------------------------------------------------------- */
	31
	32	/*
	33	* board/config.h - configuration options, board specific
	34	*/
	35
	36	#ifndef __CONFIG_H
	37	#define __CONFIG_H
	38
	39	/*
	40	* High Level Configuration Options
	41	* (easy to change)
	42	*/
	43
	44	#define CONFIG_PCIPPC2 1 /* this is a PCIPPC2 board */
	45
c837dcb1	46	#define CONFIG_BOARD_EARLY_INIT_F 1
e2211743 WD	47	#define CONFIG_MISC_INIT_R 1
	48
	49	#define CONFIG_CONS_INDEX 1
	50	#define CONFIG_BAUDRATE 9600
6d0f6bcf	51	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
e2211743	52
e2211743 WD	53	#define CONFIG_PREBOOT ""
	54	#define CONFIG_BOOTDELAY 5
	55
18225e8d JL	56	/*
	57	* BOOTP options
	58	*/
	59	#define CONFIG_BOOTP_SUBNETMASK
	60	#define CONFIG_BOOTP_GATEWAY
	61	#define CONFIG_BOOTP_HOSTNAME
	62	#define CONFIG_BOOTP_BOOTPATH
	63	#define CONFIG_BOOTP_BOOTFILESIZE
e2211743 WD	64
	65	#define CONFIG_MAC_PARTITION
	66	#define CONFIG_DOS_PARTITION
	67
acf02697 JL	68
	69	/*
	70	* Command line configuration.
	71	*/
	72	#include <config_cmd_default.h>
	73
	74	#define CONFIG_CMD_ASKENV
	75	#define CONFIG_CMD_BSP
	76	#define CONFIG_CMD_DATE
	77	#define CONFIG_CMD_DHCP
acf02697 JL	78	#define CONFIG_CMD_ELF
	79	#define CONFIG_CMD_NFS
	80	#define CONFIG_CMD_PCI
	81	#define CONFIG_CMD_SCSI
	82	#define CONFIG_CMD_SNTP
e2211743 WD	83
	84
	85	#define CONFIG_PCI 1
	86	#define CONFIG_PCI_PNP 1 /* PCI plug-and-play */
	87
e2211743 WD	88	/*
	89	* Miscellaneous configurable options
	90	*/
6d0f6bcf JCPV	91	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	92	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
e2211743	93
6d0f6bcf JCPV	94	#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */
	95	#ifdef CONFIG_SYS_HUSH_PARSER
	96	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
e2211743	97	#endif
6d0f6bcf	98	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
e2211743 WD	99
	100	/* Print Buffer Size
	101	*/
6d0f6bcf	102	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
e2211743	103
6d0f6bcf JCPV	104	#define CONFIG_SYS_MAXARGS 64 /* max number of command args */
	105	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
	106	#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */
e2211743 WD	107
	108	/*-----------------------------------------------------------------------
	109	* Start addresses for the final memory configuration
	110	* (Set up by the startup code)
6d0f6bcf	111	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
e2211743	112	*/
6d0f6bcf JCPV	113	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	114	#define CONFIG_SYS_FLASH_BASE 0xFFF00000
	115	#define CONFIG_SYS_FLASH_MAX_SIZE 0x00100000
e2211743 WD	116	/* Maximum amount of RAM.
e2211743 WD	117	*/
6d0f6bcf	118	#define CONFIG_SYS_MAX_RAM_SIZE 0x20000000 /* 512Mb */
e2211743	119
6d0f6bcf	120	#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
e2211743	121
6d0f6bcf	122	#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
e2211743	123
6d0f6bcf JCPV	124	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
6d0f6bcf JCPV	125	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
e2211743	126
6d0f6bcf JCPV	127	#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_SDRAM_BASE && \
	128	CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_MAX_RAM_SIZE
	129	#define CONFIG_SYS_RAMBOOT
e2211743	130	#else
6d0f6bcf	131	#undef CONFIG_SYS_RAMBOOT
e2211743 WD	132	#endif
e2211743 WD	133
6d0f6bcf JCPV	134	#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */
6d0f6bcf JCPV	135	#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
e2211743 WD	136
	137	/*-----------------------------------------------------------------------
	138	* Definitions for initial stack pointer and data area
	139	*/
	140
	141	/* Size in bytes reserved for initial data
	142	*/
6d0f6bcf	143	#define CONFIG_SYS_GBL_DATA_SIZE 128
e2211743	144
6d0f6bcf JCPV	145	#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
	146	#define CONFIG_SYS_INIT_RAM_END 0x8000
	147	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
	148	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
e2211743	149
6d0f6bcf	150	#define CONFIG_SYS_INIT_RAM_LOCK
e2211743 WD	151
	152	/*
	153	* Temporary buffer for serial data until the real serial driver
	154	* is initialised (memtest will destroy this buffer)
	155	*/
6d0f6bcf JCPV	156	#define CONFIG_SYS_SCONSOLE_ADDR CONFIG_SYS_INIT_RAM_ADDR
6d0f6bcf JCPV	157	#define CONFIG_SYS_SCONSOLE_SIZE 0x0002000
e2211743 WD	158
	159	/* SDRAM 0 - 256MB
	160	*/
6d0f6bcf JCPV	161	#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE \| BATL_PP_10 \| BATL_MEMCOHERENCE)
6d0f6bcf JCPV	162	#define CONFIG_SYS_DBAT0U (CONFIG_SYS_SDRAM_BASE \| \
e2211743 WD	163	BATU_BL_256M \| BATU_VS \| BATU_VP)
	164	/* SDRAM 1 - 256MB
	165	*/
6d0f6bcf	166	#define CONFIG_SYS_DBAT1L ((CONFIG_SYS_SDRAM_BASE + 0x10000000) \| \
e2211743	167	BATL_PP_10 \| BATL_MEMCOHERENCE)
6d0f6bcf	168	#define CONFIG_SYS_DBAT1U ((CONFIG_SYS_SDRAM_BASE + 0x10000000) \| \
e2211743 WD	169	BATU_BL_256M \| BATU_VS \| BATU_VP)
	170
	171	/* Init RAM in the CPU DCache (no backing memory)
	172	*/
6d0f6bcf	173	#define CONFIG_SYS_DBAT2L (CONFIG_SYS_INIT_RAM_ADDR \| \
e2211743	174	BATL_PP_10 \| BATL_MEMCOHERENCE)
6d0f6bcf	175	#define CONFIG_SYS_DBAT2U (CONFIG_SYS_INIT_RAM_ADDR \| \
e2211743 WD	176	BATU_BL_128K \| BATU_VS \| BATU_VP)
	177
	178	/* I/O and PCI memory at 0xf0000000
	179	*/
6d0f6bcf JCPV	180	#define CONFIG_SYS_DBAT3L (0xf0000000 \| BATL_PP_10 \| BATL_CACHEINHIBIT)
	181	#define CONFIG_SYS_DBAT3U (0xf0000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	182
	183	#define CONFIG_SYS_IBAT0L CONFIG_SYS_DBAT0L
	184	#define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U
	185	#define CONFIG_SYS_IBAT1L CONFIG_SYS_DBAT1L
	186	#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
	187	#define CONFIG_SYS_IBAT2L CONFIG_SYS_DBAT2L
	188	#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
	189	#define CONFIG_SYS_IBAT3L CONFIG_SYS_DBAT3L
	190	#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
e2211743 WD	191
	192	/*
	193	* Low Level Configuration Settings
	194	* (address mappings, register initial values, etc.)
	195	* You should know what you are doing if you make changes here.
	196	* For the detail description refer to the PCIPPC2 user's manual.
	197	*/
6d0f6bcf JCPV	198	#define CONFIG_SYS_HZ 1000
	199	#define CONFIG_SYS_BUS_HZ 100000000 /* bus speed - 100 mhz */
	200	#define CONFIG_SYS_CPU_CLK 300000000
	201	#define CONFIG_SYS_BUS_CLK 100000000
e2211743 WD	202
	203	/*
	204	* For booting Linux, the board info and command line data
	205	* have to be in the first 8 MB of memory, since this is
	206	* the maximum mapped by the Linux kernel during initialization.
	207	*/
6d0f6bcf	208	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
e2211743 WD	209
	210	/*-----------------------------------------------------------------------
	211	* FLASH organization
	212	*/
6d0f6bcf JCPV	213	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */
6d0f6bcf JCPV	214	#define CONFIG_SYS_MAX_FLASH_SECT 16 /* Max number of sectors in one bank */
e2211743	215
6d0f6bcf JCPV	216	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	217	#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
e2211743 WD	218
	219	/*
	220	* Note: environment is not EMBEDDED in the U-Boot code.
	221	* It's stored in flash separately.
	222	*/
5a1aceb0	223	#define CONFIG_ENV_IS_IN_FLASH 1
6d0f6bcf	224	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x70000)
0e8d1586 JCPV	225	#define CONFIG_ENV_SIZE 0x1000 /* Size of the Environment */
0e8d1586 JCPV	226	#define CONFIG_ENV_SECT_SIZE 0x10000 /* Size of the Environment Sector */
e2211743 WD	227
	228	/*-----------------------------------------------------------------------
	229	* Cache Configuration
	230	*/
6d0f6bcf	231	#define CONFIG_SYS_CACHELINE_SIZE 32
acf02697	232	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	233	# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
e2211743 WD	234	#endif
	235
	236	/*
	237	* L2 cache
	238	*/
6d0f6bcf	239	#undef CONFIG_SYS_L2
e2211743 WD	240	#define L2_INIT (L2CR_L2SIZ_2M \| L2CR_L2CLK_3 \| L2CR_L2RAM_BURST \| \
	241	L2CR_L2OH_5 \| L2CR_L2CTL \| L2CR_L2WT)
	242	#define L2_ENABLE (L2_INIT \| L2CR_L2E)
	243
	244	/*
	245	* Internal Definitions
	246	*
	247	* Boot Flags
	248	*/
	249	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	250	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	251
e2211743 WD	252	/*-----------------------------------------------------------------------
	253	RTC m48t59
	254	*/
	255	#define CONFIG_RTC_MK48T59
	256
	257	#define CONFIG_WATCHDOG
	258
	259	#define CONFIG_NET_MULTI /* Multi ethernet cards support */
	260
	261	#define CONFIG_EEPRO100
6d0f6bcf	262	#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
e2211743 WD	263	#define CONFIG_TULIP
	264
	265
	266	#define CONFIG_SCSI_SYM53C8XX
	267	#define CONFIG_SCSI_DEV_ID 0x000B /* 53c896 */
6d0f6bcf JCPV	268	#define CONFIG_SYS_SCSI_MAX_LUN 8 /* number of supported LUNs */
	269	#define CONFIG_SYS_SCSI_MAX_SCSI_ID 15 /* maximum SCSI ID (0..6) */
	270	#define CONFIG_SYS_SCSI_MAX_DEVICE CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN /* maximum Target devices */
	271	#define CONFIG_SYS_SCSI_SPIN_UP_TIME 2
	272	#define CONFIG_SYS_SCSI_SCAN_BUS_REVERSE 0
e2211743 WD	273	#define CONFIG_DOS_PARTITION
	274	#define CONFIG_MAC_PARTITION
	275	#define CONFIG_ISO_PARTITION
	276
e2211743	277	#endif /* __CONFIG_H */