[people/ms/u-boot.git] / include / configs / PIP405.h

/*
 * (C) Copyright 2001
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/***********************************************************
 * High Level Configuration Options
 * (easy to change)
 ***********************************************************/
#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
#define CONFIG_PIP405		1	/* ...on a PIP405 board		*/
/***********************************************************
 * Clock
 ***********************************************************/
#define CONFIG_SYS_CLK_FREQ	33000000 /* external frequency to pll	*/


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_IDE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PCI
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_FDC
#define CONFIG_CMD_SCSI
#define CONFIG_CMD_FAT
#define CONFIG_CMD_DATE
#define CONFIG_CMD_ELF
#define CONFIG_CMD_USB
#define CONFIG_CMD_MII
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_DOC
#define CONFIG_CMD_PING
#define CONFIG_CMD_SAVES
#define CONFIG_CMD_BSP


#define CONFIG_NAND_LEGACY

#define	 CFG_HUSH_PARSER
#define	 CFG_PROMPT_HUSH_PS2 "> "
/**************************************************************
 * I2C Stuff:
 * the PIP405 is equiped with an Atmel 24C128/256 EEPROM at address
 * 0x53.
 * Caution: on the same bus is the SPD (Serial Presens Detect
 * EEPROM of the SDRAM
 * The Atmel EEPROM uses 16Bit addressing.
 ***************************************************************/
#define CONFIG_HARD_I2C			/* I2c with hardware support */
#define CFG_I2C_SPEED		50000	/* I2C speed and slave address */
#define CFG_I2C_SLAVE		0x7F

#define CFG_I2C_EEPROM_ADDR	0x53
#define CFG_I2C_EEPROM_ADDR_LEN	2
#define CONFIG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
#define CONFIG_ENV_OFFSET          0x000   /* environment starts at the beginning of the EEPROM */
#define CONFIG_ENV_SIZE            0x800   /* 2 kBytes may be used for env vars */

#undef CFG_I2C_EEPROM_ADDR_OVERFLOW
#define CFG_EEPROM_PAGE_WRITE_BITS 6	/* The Atmel 24C128/256 has	*/
					/* 64 byte page write mode using*/
					/* last	6 bits of the address	*/
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */


/***************************************************************
 * Definitions for Serial Presence Detect EEPROM address
 * (to get SDRAM settings)
 ***************************************************************/
#define SPD_EEPROM_ADDRESS      0x50

#define CONFIG_BOARD_EARLY_INIT_F
/**************************************************************
 * Environment definitions
 **************************************************************/
#define CONFIG_BAUDRATE		9600	/* STD Baudrate */


#define CONFIG_BOOTDELAY	5
/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
/* #define CONFIG_BOOT_RETRY_TIME	-10	/XXX* feature is available but not enabled */
#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check console even if bootdelay = 0 */


#define CONFIG_BOOTCOMMAND	"diskboot 400000 0:1; bootm" /* autoboot command		*/
#define CONFIG_BOOTARGS		"console=ttyS0,9600 root=/dev/hda5" /* boot arguments */

#define CONFIG_IPADDR		10.0.0.100
#define CONFIG_SERVERIP		10.0.0.1
#define CONFIG_PREBOOT
/***************************************************************
 * defines if the console is stored in the environment
 ***************************************************************/
#define CFG_CONSOLE_IS_IN_ENV	/* stdin, stdout and stderr are in evironment */
/***************************************************************
 * defines if an overwrite_console function exists
 *************************************************************/
#define CFG_CONSOLE_OVERWRITE_ROUTINE
#define CFG_CONSOLE_INFO_QUIET
/***************************************************************
 * defines if the overwrite_console should be stored in the
 * environment
 **************************************************************/
#undef CFG_CONSOLE_ENV_OVERWRITE

/**************************************************************
 * loads config
 *************************************************************/
#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

#define CONFIG_MISC_INIT_R
/***********************************************************
 * Miscellaneous configurable options
 **********************************************************/
#define CFG_LONGHELP			/* undef to save memory		*/
#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS	16		/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x0100000	/* memtest works on	*/
#define CFG_MEMTEST_END		0x0C00000	/* 1 ... 12 MB in DRAM	*/

#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
#define CFG_BASE_BAUD       691200

/* The following table includes the supported baudrates */
#define CFG_BAUDRATE_TABLE	\
	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
	 57600, 115200, 230400, 460800, 921600 }

#define CFG_LOAD_ADDR		0x400000	/* default load address */
#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */

#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
#define PCI_HOST_ADAPTER 0              /* configure ar pci adapter     */
#define PCI_HOST_FORCE  1               /* configure as pci host        */
#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */

#define CONFIG_PCI			/* include pci support		*/
#define CONFIG_PCI_HOST PCI_HOST_FORCE	/* configure as pci-host	*/
#define CONFIG_PCI_PNP			/* pci plug-and-play		*/
					/* resource configuration	*/
#define CFG_PCI_SUBSYS_VENDORID 0x0000	/* PCI Vendor ID: to-do!!!	*/
#define CFG_PCI_SUBSYS_DEVICEID 0x0000	/* PCI Device ID: to-do!!!	*/
#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
#define CFG_PCI_PTM1MS	0x80000001	/* 2GB, enable hard-wired to 1	*/
#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
#define CFG_PCI_PTM2LA	0x00000000	/* disabled			*/
#define CFG_PCI_PTM2MS	0x00000000	/* disabled			*/
#define CFG_PCI_PTM2PCI 0x00000000      /* Host: use this pci address   */

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
#define CFG_SDRAM_BASE		0x00000000
#define CFG_FLASH_BASE		0xFFF80000
#define CFG_MONITOR_BASE	CFG_FLASH_BASE
#define CFG_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Monitor	*/
#define CFG_MALLOC_LEN		(1024 * 1024)	/* Reserve 1024 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

/*
 * Init Memory Controller:
 */
#define FLASH_MAX_SIZE		0x00800000		/* 8MByte max */
#define FLASH_BASE_PRELIM	0xFF800000  /* open the flash CS */
/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
#define FLASH_SIZE_PRELIM	 3  /* maximal flash FLASH size bank #0	*/

#define CONFIG_BOARD_EARLY_INIT_F

/* Configuration Port location */
#define CONFIG_PORT_ADDR	0xF4000000
#define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000


/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in On Chip SRAM)
 */
#define CFG_TEMP_STACK_OCM	1
#define CFG_OCM_DATA_ADDR	0xF0000000
#define CFG_OCM_DATA_SIZE	0x1000
#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR	/* inside of On Chip SRAM    */
#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE	/* End of On Chip SRAM	       */
#define CFG_GBL_DATA_SIZE	64		/* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/


/***********************************************************************
 * External peripheral base address
 ***********************************************************************/
#define CFG_ISA_IO_BASE_ADDRESS 0xE8000000

/***********************************************************************
 * Last Stage Init
 ***********************************************************************/
#define CONFIG_LAST_STAGE_INIT
/************************************************************
 * Ethernet Stuff
 ***********************************************************/
#define CONFIG_MII		1	/* MII PHY management		*/
#define CONFIG_PHY_ADDR		1	/* PHY address			*/
/************************************************************
 * RTC
 ***********************************************************/
#define CONFIG_RTC_MC146818
#undef CONFIG_WATCHDOG			/* watchdog disabled		*/

/************************************************************
 * IDE/ATA stuff
 ************************************************************/
#define CFG_IDE_MAXBUS		2   /* max. 2 IDE busses	*/
#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */

#define CFG_ATA_BASE_ADDR	CFG_ISA_IO_BASE_ADDRESS /* base address */
#define CFG_ATA_IDE0_OFFSET	0x01F0	/* ide0 offste */
#define CFG_ATA_IDE1_OFFSET	0x0170	/* ide1 offset */
#define CFG_ATA_DATA_OFFSET	0	/* data reg offset	*/
#define CFG_ATA_REG_OFFSET	0	/* reg offset */
#define CFG_ATA_ALT_OFFSET	0x200	/* alternate register offset */

#undef	CONFIG_IDE_8xx_DIRECT		/* no pcmcia interface required */
#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
#define CONFIG_IDE_RESET		/* reset for ide supported...	*/
#define CONFIG_IDE_RESET_ROUTINE	/* with a special reset function */
#define CONFIG_SUPPORT_VFAT

/************************************************************
 * ATAPI support (experimental)
 ************************************************************/
#define CONFIG_ATAPI			/* enable ATAPI Support */

/************************************************************
 * SCSI support (experimental) only SYM53C8xx supported
 ************************************************************/
#define CONFIG_SCSI_SYM53C8XX
#define CFG_SCSI_MAX_LUN	8	/* number of supported LUNs */
#define CFG_SCSI_MAX_SCSI_ID	7	/* maximum SCSI ID (0..6) */
#define CFG_SCSI_MAX_DEVICE	CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN /* maximum Target devices */
#define CFG_SCSI_SPIN_UP_TIME	2

/************************************************************
 * Disk-On-Chip configuration
 ************************************************************/
#define CFG_MAX_DOC_DEVICE	1	/* Max number of DOC devices		*/
#define CFG_DOC_SHORT_TIMEOUT
#define CFG_DOC_SUPPORT_2000
#define CFG_DOC_SUPPORT_MILLENNIUM

/************************************************************
 * DISK Partition support
 ************************************************************/
#define CONFIG_DOS_PARTITION
#define CONFIG_MAC_PARTITION
#define CONFIG_ISO_PARTITION /* Experimental */

/************************************************************
 * Keyboard support
 ************************************************************/
#define CONFIG_ISA_KEYBOARD

/************************************************************
 * Video support
 ************************************************************/
#define CONFIG_VIDEO			/*To enable video controller support */
#define CONFIG_VIDEO_CT69000
#define CONFIG_CFB_CONSOLE
#define CONFIG_VIDEO_LOGO
#define CONFIG_CONSOLE_EXTRA_INFO
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_VIDEO_SW_CURSOR
#define CONFIG_VIDEO_ONBOARD		/* Video controller is on-board */

/************************************************************
 * USB support
 ************************************************************/
#define CONFIG_USB_UHCI
#define CONFIG_USB_KEYBOARD
#define CONFIG_USB_STORAGE

/* Enable needed helper functions */
#define CFG_DEVICE_DEREGISTER		/* needs device_deregister */

/************************************************************
 * Debug support
 ************************************************************/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
#endif

/************************************************************
 * support BZIP2 compression
 ************************************************************/
#define CONFIG_BZIP2		1

/************************************************************
 * Ident
 ************************************************************/
#define VERSION_TAG "released"
#define CONFIG_ISO_STRING "MEV-10066-001"
#define CONFIG_IDENT_STRING "\n(c) 2002 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG


#endif	/* __CONFIG_H */
Commit	Line	Data
c609719b WD	1	/*
	2	* (C) Copyright 2001
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* board/config.h - configuration options, board specific
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	/***********************************************************
	32	* High Level Configuration Options
	33	* (easy to change)
	34	***********************************************************/
	35	#define CONFIG_405GP 1 /* This is a PPC405 CPU */
	36	#define CONFIG_4xx 1 /* ...member of PPC4xx family */
	37	#define CONFIG_PIP405 1 /* ...on a PIP405 board */
	38	/***********************************************************
	39	* Clock
	40	***********************************************************/
	41	#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
	42
acf02697	43
a1aa0bb5 JL	44	/*
	45	* BOOTP options
	46	*/
	47	#define CONFIG_BOOTP_BOOTFILESIZE
	48	#define CONFIG_BOOTP_BOOTPATH
	49	#define CONFIG_BOOTP_GATEWAY
	50	#define CONFIG_BOOTP_HOSTNAME
	51
	52
acf02697 JL	53	/*
	54	* Command line configuration.
	55	*/
	56	#include <config_cmd_default.h>
	57
	58	#define CONFIG_CMD_IDE
	59	#define CONFIG_CMD_DHCP
	60	#define CONFIG_CMD_PCI
	61	#define CONFIG_CMD_CACHE
	62	#define CONFIG_CMD_IRQ
	63	#define CONFIG_CMD_EEPROM
	64	#define CONFIG_CMD_I2C
	65	#define CONFIG_CMD_REGINFO
	66	#define CONFIG_CMD_FDC
	67	#define CONFIG_CMD_SCSI
	68	#define CONFIG_CMD_FAT
	69	#define CONFIG_CMD_DATE
	70	#define CONFIG_CMD_ELF
	71	#define CONFIG_CMD_USB
	72	#define CONFIG_CMD_MII
	73	#define CONFIG_CMD_SDRAM
	74	#define CONFIG_CMD_DOC
	75	#define CONFIG_CMD_PING
	76	#define CONFIG_CMD_SAVES
	77	#define CONFIG_CMD_BSP
	78
c609719b	79
cc4a0cee	80	#define CONFIG_NAND_LEGACY
addb2e16	81
c609719b WD	82	#define CFG_HUSH_PARSER
	83	#define CFG_PROMPT_HUSH_PS2 "> "
	84	/**************************************************************
	85	* I2C Stuff:
	86	* the PIP405 is equiped with an Atmel 24C128/256 EEPROM at address
	87	* 0x53.
	88	* Caution: on the same bus is the SPD (Serial Presens Detect
	89	* EEPROM of the SDRAM
	90	* The Atmel EEPROM uses 16Bit addressing.
	91	***************************************************************/
	92	#define CONFIG_HARD_I2C /* I2c with hardware support */
	93	#define CFG_I2C_SPEED 50000 /* I2C speed and slave address */
	94	#define CFG_I2C_SLAVE 0x7F
	95
	96	#define CFG_I2C_EEPROM_ADDR 0x53
	97	#define CFG_I2C_EEPROM_ADDR_LEN 2
bb1f8b4f	98	#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
0e8d1586 JCPV	99	#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
0e8d1586 JCPV	100	#define CONFIG_ENV_SIZE 0x800 /* 2 kBytes may be used for env vars */
c609719b WD	101
	102	#undef CFG_I2C_EEPROM_ADDR_OVERFLOW
	103	#define CFG_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel 24C128/256 has */
	104	/* 64 byte page write mode using*/
	105	/* last 6 bits of the address */
c609719b WD	106	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
	107
	108
	109	/***************************************************************
	110	* Definitions for Serial Presence Detect EEPROM address
	111	* (to get SDRAM settings)
	112	***************************************************************/
	113	#define SPD_EEPROM_ADDRESS 0x50
	114
c837dcb1	115	#define CONFIG_BOARD_EARLY_INIT_F
c609719b WD	116	/**************************************************************
	117	* Environment definitions
	118	**************************************************************/
	119	#define CONFIG_BAUDRATE 9600 /* STD Baudrate */
	120
	121
	122	#define CONFIG_BOOTDELAY 5
	123	/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
2afbe4ed	124	/* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */
53677ef1	125	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */
c609719b WD	126
c609719b WD	127
3e38691e	128	#define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */
c609719b WD	129	#define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
	130
	131	#define CONFIG_IPADDR 10.0.0.100
	132	#define CONFIG_SERVERIP 10.0.0.1
	133	#define CONFIG_PREBOOT
	134	/***************************************************************
	135	* defines if the console is stored in the environment
	136	***************************************************************/
	137	#define CFG_CONSOLE_IS_IN_ENV /* stdin, stdout and stderr are in evironment */
	138	/***************************************************************
	139	* defines if an overwrite_console function exists
	140	*************************************************************/
	141	#define CFG_CONSOLE_OVERWRITE_ROUTINE
	142	#define CFG_CONSOLE_INFO_QUIET
	143	/***************************************************************
	144	* defines if the overwrite_console should be stored in the
	145	* environment
	146	**************************************************************/
	147	#undef CFG_CONSOLE_ENV_OVERWRITE
	148
	149	/**************************************************************
	150	* loads config
	151	*************************************************************/
	152	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	153	#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
	154
7205e407	155	#define CONFIG_MISC_INIT_R
c609719b WD	156	/***********************************************************
	157	* Miscellaneous configurable options
	158	**********************************************************/
	159	#define CFG_LONGHELP /* undef to save memory */
	160	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
acf02697	161	#if defined(CONFIG_CMD_KGDB)
c609719b WD	162	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	163	#else
	164	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	165	#endif
	166	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	167	#define CFG_MAXARGS 16 /* max number of command args */
	168	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	169
	170	#define CFG_MEMTEST_START 0x0100000 /* memtest works on */
	171	#define CFG_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */
	172
	173	#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
	174	#define CFG_BASE_BAUD 691200
	175
	176	/* The following table includes the supported baudrates */
	177	#define CFG_BAUDRATE_TABLE \
	178	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
	179	57600, 115200, 230400, 460800, 921600 }
	180
3e38691e	181	#define CFG_LOAD_ADDR 0x400000 /* default load address */
c609719b WD	182	#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
	183
	184	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
	185
	186	/*-----------------------------------------------------------------------
	187	* PCI stuff
	188	*-----------------------------------------------------------------------
	189	*/
	190	#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
	191	#define PCI_HOST_FORCE 1 /* configure as pci host */
	192	#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
	193
	194	#define CONFIG_PCI /* include pci support */
	195	#define CONFIG_PCI_HOST PCI_HOST_FORCE /* configure as pci-host */
	196	#define CONFIG_PCI_PNP /* pci plug-and-play */
	197	/* resource configuration */
	198	#define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
	199	#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
	200	#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
	201	#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
	202	#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
	203	#define CFG_PCI_PTM2LA 0x00000000 /* disabled */
	204	#define CFG_PCI_PTM2MS 0x00000000 /* disabled */
	205	#define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
	206
	207	/*-----------------------------------------------------------------------
	208	* Start addresses for the final memory configuration
	209	* (Set up by the startup code)
	210	* Please note that CFG_SDRAM_BASE _must_ start at 0
	211	*/
	212	#define CFG_SDRAM_BASE 0x00000000
	213	#define CFG_FLASH_BASE 0xFFF80000
	214	#define CFG_MONITOR_BASE CFG_FLASH_BASE
	215	#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
a2663ea4	216	#define CFG_MALLOC_LEN (1024 * 1024) /* Reserve 1024 kB for malloc() */
c609719b WD	217
	218	/*
	219	* For booting Linux, the board info and command line data
	220	* have to be in the first 8 MB of memory, since this is
	221	* the maximum mapped by the Linux kernel during initialization.
	222	*/
	223	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	224	/*-----------------------------------------------------------------------
	225	* FLASH organization
	226	*/
	227	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
	228	#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
	229
	230	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
	231	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
	232
c609719b WD	233	/*
	234	* Init Memory Controller:
	235	*/
7205e407 WD	236	#define FLASH_MAX_SIZE 0x00800000 /* 8MByte max */
	237	#define FLASH_BASE_PRELIM 0xFF800000 /* open the flash CS */
	238	/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
	239	#define FLASH_SIZE_PRELIM 3 /* maximal flash FLASH size bank #0 */
c609719b	240
c837dcb1	241	#define CONFIG_BOARD_EARLY_INIT_F
c609719b WD	242
	243	/* Configuration Port location */
	244	#define CONFIG_PORT_ADDR 0xF4000000
	245	#define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
	246
	247
c609719b WD	248	/*-----------------------------------------------------------------------
	249	* Definitions for initial stack pointer and data area (in On Chip SRAM)
	250	*/
	251	#define CFG_TEMP_STACK_OCM 1
	252	#define CFG_OCM_DATA_ADDR 0xF0000000
	253	#define CFG_OCM_DATA_SIZE 0x1000
53677ef1	254	#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of On Chip SRAM */
c609719b WD	255	#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of On Chip SRAM */
	256	#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
	257	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	258	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	259
	260	/*
	261	* Internal Definitions
	262	*
	263	* Boot Flags
	264	*/
	265	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	266	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	267
	268
	269	/***********************************************************************
	270	* External peripheral base address
	271	***********************************************************************/
	272	#define CFG_ISA_IO_BASE_ADDRESS 0xE8000000
	273
	274	/***********************************************************************
	275	* Last Stage Init
	276	***********************************************************************/
	277	#define CONFIG_LAST_STAGE_INIT
	278	/************************************************************
	279	* Ethernet Stuff
	280	***********************************************************/
	281	#define CONFIG_MII 1 /* MII PHY management */
	282	#define CONFIG_PHY_ADDR 1 /* PHY address */
c609719b WD	283	/************************************************************
	284	* RTC
	285	***********************************************************/
	286	#define CONFIG_RTC_MC146818
	287	#undef CONFIG_WATCHDOG /* watchdog disabled */
	288
	289	/************************************************************
	290	* IDE/ATA stuff
	291	************************************************************/
	292	#define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */
	293	#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS2) / max. 2 drives per IDE bus */
	294
	295	#define CFG_ATA_BASE_ADDR CFG_ISA_IO_BASE_ADDRESS /* base address */
	296	#define CFG_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
	297	#define CFG_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */
	298	#define CFG_ATA_DATA_OFFSET 0 /* data reg offset */
	299	#define CFG_ATA_REG_OFFSET 0 /* reg offset */
	300	#define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */
	301
	302	#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
	303	#undef CONFIG_IDE_LED /* no led for ide supported */
	304	#define CONFIG_IDE_RESET /* reset for ide supported... */
	305	#define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
7205e407	306	#define CONFIG_SUPPORT_VFAT
c609719b WD	307
	308	/************************************************************
	309	* ATAPI support (experimental)
	310	************************************************************/
	311	#define CONFIG_ATAPI /* enable ATAPI Support */
	312
	313	/************************************************************
	314	* SCSI support (experimental) only SYM53C8xx supported
	315	************************************************************/
	316	#define CONFIG_SCSI_SYM53C8XX
	317	#define CFG_SCSI_MAX_LUN 8 /* number of supported LUNs */
	318	#define CFG_SCSI_MAX_SCSI_ID 7 /* maximum SCSI ID (0..6) */
	319	#define CFG_SCSI_MAX_DEVICE CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN /* maximum Target devices */
	320	#define CFG_SCSI_SPIN_UP_TIME 2
	321
	322	/************************************************************
	323	* Disk-On-Chip configuration
	324	************************************************************/
	325	#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
	326	#define CFG_DOC_SHORT_TIMEOUT
	327	#define CFG_DOC_SUPPORT_2000
	328	#define CFG_DOC_SUPPORT_MILLENNIUM
	329
	330	/************************************************************
	331	* DISK Partition support
	332	************************************************************/
	333	#define CONFIG_DOS_PARTITION
	334	#define CONFIG_MAC_PARTITION
	335	#define CONFIG_ISO_PARTITION /* Experimental */
	336
	337	/************************************************************
	338	* Keyboard support
	339	************************************************************/
	340	#define CONFIG_ISA_KEYBOARD
	341
	342	/************************************************************
	343	* Video support
	344	************************************************************/
	345	#define CONFIG_VIDEO /To enable video controller support /
	346	#define CONFIG_VIDEO_CT69000
	347	#define CONFIG_CFB_CONSOLE
	348	#define CONFIG_VIDEO_LOGO
	349	#define CONFIG_CONSOLE_EXTRA_INFO
	350	#define CONFIG_VGA_AS_SINGLE_DEVICE
	351	#define CONFIG_VIDEO_SW_CURSOR
	352	#define CONFIG_VIDEO_ONBOARD /* Video controller is on-board */
	353
	354	/************************************************************
	355	* USB support
	356	************************************************************/
	357	#define CONFIG_USB_UHCI
	358	#define CONFIG_USB_KEYBOARD
	359	#define CONFIG_USB_STORAGE
	360
	361	/* Enable needed helper functions */
	362	#define CFG_DEVICE_DEREGISTER /* needs device_deregister */
	363
	364	/************************************************************
	365	* Debug support
	366	************************************************************/
acf02697	367	#if defined(CONFIG_CMD_KGDB)
c609719b WD	368	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
	369	#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
	370	#endif
	371
a2663ea4 WD	372	/************************************************************
	373	* support BZIP2 compression
	374	************************************************************/
	375	#define CONFIG_BZIP2 1
	376
c609719b WD	377	/************************************************************
	378	* Ident
	379	************************************************************/
	380	#define VERSION_TAG "released"
f3e0de60 WD	381	#define CONFIG_ISO_STRING "MEV-10066-001"
f3e0de60 WD	382	#define CONFIG_IDENT_STRING "\n(c) 2002 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG
c609719b WD	383
	384
	385	#endif /* __CONFIG_H */