[people/ms/u-boot.git] / include / configs / PK1C20.h

/*
 * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
 * Scott McNutt <smcnutt@psyent.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*------------------------------------------------------------------------
 * BOARD/CPU
 *----------------------------------------------------------------------*/
#define CONFIG_PK1C20		1		/* PK1C20 board		*/
#define CONFIG_SYS_CLK_FREQ	50000000	/* 50 MHz core clk	*/

#define CONFIG_SYS_RESET_ADDR		0x00000000	/* Hard-reset address	*/
#define CONFIG_SYS_EXCEPTION_ADDR	0x01000020	/* Exception entry point*/
#define CONFIG_SYS_NIOS_SYSID_BASE	0x021208b8	/* System id address	*/
#define CONFIG_BOARD_EARLY_INIT_F 1	/* enable early board-spec. init*/

/*------------------------------------------------------------------------
 * CACHE -- the following will support II/s and II/f. The II/s does not
 * have dcache, so the cache instructions will behave as NOPs.
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_ICACHE_SIZE		4096		/* 4 KByte total	*/
#define CONFIG_SYS_ICACHELINE_SIZE	32		/* 32 bytes/line	*/
#define CONFIG_SYS_DCACHE_SIZE		2048		/* 2 KByte (II/f)	*/
#define CONFIG_SYS_DCACHELINE_SIZE	4		/* 4 bytes/line (II/f)	*/

/*------------------------------------------------------------------------
 * MEMORY BASE ADDRESSES
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_FLASH_BASE		0x00000000	/* FLASH base addr	*/
#define CONFIG_SYS_FLASH_SIZE		0x00800000	/* 8 MByte		*/
#define CONFIG_SYS_SDRAM_BASE		0x01000000	/* SDRAM base addr	*/
#define CONFIG_SYS_SDRAM_SIZE		0x01000000	/* 16 MByte		*/
#define CONFIG_SYS_SRAM_BASE		0x02000000	/* SRAM base addr	*/
#define CONFIG_SYS_SRAM_SIZE		0x00100000	/* 1 MB (only 1M mapped)*/

/*------------------------------------------------------------------------
 * MEMORY ORGANIZATION
 *	-Monitor at top.
 *	-The heap is placed below the monitor.
 *	-Global data is placed below the heap.
 *	-The stack is placed below global data (&grows down).
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 128k		*/
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)

#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_MALLOC_BASE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP		CONFIG_SYS_GBL_DATA_OFFSET

/*------------------------------------------------------------------------
 * FLASH (AM29LV065D)
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_MAX_FLASH_SECT	128		/* Max # sects per bank */
#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* Max # of flash banks */
#define CONFIG_SYS_FLASH_ERASE_TOUT	8000		/* Erase timeout (msec) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	100		/* Write timeout (msec) */
#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned char	/* flash word size	*/

/*------------------------------------------------------------------------
 * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
 * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the
 * reset address, no? This will keep the environment in user region
 * of flash. NOTE: the monitor length must be multiple of sector size
 * (which is common practice).
 *----------------------------------------------------------------------*/
#define CONFIG_ENV_IS_IN_FLASH	1		/* Environment in flash */
#define CONFIG_ENV_SIZE		(64 * 1024)	/* 64 KByte (1 sector)	*/
#define CONFIG_ENV_OVERWRITE			/* Serial change Ok	*/
#define CONFIG_ENV_ADDR	(CONFIG_SYS_RESET_ADDR + CONFIG_SYS_MONITOR_LEN)

/*------------------------------------------------------------------------
 * CONSOLE
 *----------------------------------------------------------------------*/
#define CONFIG_ALTERA_UART		1	/* Use altera uart */
#if defined(CONFIG_ALTERA_JTAG_UART)
#define CONFIG_SYS_NIOS_CONSOLE	0x021208b0	/* JTAG UART base addr	*/
#else
#define CONFIG_SYS_NIOS_CONSOLE	0x02120840	/* UART base addr	*/
#endif

#define CONFIG_SYS_NIOS_FIXEDBAUD	1		/* Baudrate is fixed	*/
#define CONFIG_BAUDRATE		115200		/* Initial baudrate	*/
#define CONFIG_SYS_BAUDRATE_TABLE	{115200}	/* It's fixed ;-)	*/

#define CONFIG_SYS_CONSOLE_INFO_QUIET	1		/* Suppress console info*/

/*------------------------------------------------------------------------
 * EPCS Device -- wne CONFIG_SYS_NIOS_EPCSBASE is defined code/commands for
 * epcs device access is enabled. The base address is the epcs
 * _register_ base address, NOT THE ADDRESS OF THE MEMORY BLOCK.
 * The register base is currently at offset 0x600 from the memory base.
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_NIOS_EPCSBASE	0x02100200	/* EPCS register base	*/

/*------------------------------------------------------------------------
 * DEBUG
 *----------------------------------------------------------------------*/
#undef CONFIG_ROM_STUBS				/* Stubs not in ROM	*/

/*------------------------------------------------------------------------
 * TIMEBASE --
 *
 * The high res timer defaults to 1 msec. Since it includes the period
 * registers, the interrupt frequency can be reduced using TMRCNT.
 * If the default period is acceptable, TMRCNT can be left undefined.
 * TMRMS represents the desired mecs per tick (msecs per interrupt).
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_HZ			1000	/* Always 1000 */
#define CONFIG_SYS_LOW_RES_TIMER
#define CONFIG_SYS_NIOS_TMRBASE	0x02120820	/* Tick timer base addr */
#define CONFIG_SYS_NIOS_TMRIRQ		3	/* Timer IRQ num */
#define CONFIG_SYS_NIOS_TMRMS		10	/* Desired period */
#define CONFIG_SYS_NIOS_TMRCNT \
		(CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))

/*------------------------------------------------------------------------
 * STATUS LED -- Provides a simple blinking led. For Nios2 each board
 * must implement its own led routines -- leds are, after all,
 * board-specific, no?
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_LEDPIO_ADDR		0x02120870	/* LED PIO base addr	*/
#define CONFIG_STATUS_LED			/* Enable status driver */
#define CONFIG_BOARD_SPECIFIC_LED

#define STATUS_LED_BIT		1		/* Bit-0 on PIO		*/
#define STATUS_LED_STATE	1		/* Blinking		*/
#define STATUS_LED_PERIOD	(500/CONFIG_SYS_NIOS_TMRMS) /* Every 500 msec	*/

/*------------------------------------------------------------------------
 * ETHERNET -- The header file for the SMC91111 driver hurts my eyes ...
 * and really doesn't need any additional clutter. So I choose the lazy
 * way out to avoid changes there -- define the base address to ensure
 * cache bypass so there's no need to monkey with inx/outx macros.
 *----------------------------------------------------------------------*/
#define CONFIG_SMC91111_BASE	0x82110300	/* Base addr (bypass)	*/
#define CONFIG_SMC91111			/* Using SMC91c111	*/
#undef	CONFIG_SMC91111_EXT_PHY			/* Internal PHY		*/
#define CONFIG_SMC_USE_32_BIT			/* 32-bit interface	*/

#define CONFIG_ETHADDR		08:00:3e:26:0a:5b
#define CONFIG_NETMASK		255.255.255.0
#define CONFIG_IPADDR		192.168.2.21
#define CONFIG_SERVERIP		192.168.2.16


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */

#define CONFIG_CMD_BDI
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ECHO
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_IMI
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_LOADS
#define CONFIG_CMD_LOADB
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_MISC
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_RUN
#define CONFIG_CMD_SAVES


/*------------------------------------------------------------------------
 * COMPACT FLASH
 *----------------------------------------------------------------------*/
#if defined(CONFIG_CMD_IDE)
#define CONFIG_IDE_PREINIT			/* Implement id_preinit	*/
#define CONFIG_SYS_IDE_MAXBUS		1		/* 1 IDE bus		*/
#define CONFIG_SYS_IDE_MAXDEVICE	1		/* 1 drive per IDE bus	*/

#define CONFIG_SYS_ATA_BASE_ADDR	0x00900800	/* ATA base addr	*/
#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000		/* IDE0 offset		*/
#define CONFIG_SYS_ATA_DATA_OFFSET	0x0040		/* Data IO offset	*/
#define CONFIG_SYS_ATA_REG_OFFSET	0x0040		/* Register offset	*/
#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100		/* Alternate reg offset	*/
#define CONFIG_SYS_ATA_STRIDE          4		/* Width betwix addrs	*/
#define CONFIG_DOS_PARTITION

/* Board-specific cf regs */
#define CONFIG_SYS_CF_PRESENT		0x00900880	/* CF Present PIO base	*/
#define CONFIG_SYS_CF_POWER		0x00900890	/* CF Power FET PIO base*/
#define CONFIG_SYS_CF_ATASEL		0x009008a0	/* CF ATASEL PIO base	*/

#endif

/*------------------------------------------------------------------------
 * JFFS2
 *----------------------------------------------------------------------*/
#if defined(CONFIG_CMD_JFFS2)
#define CONFIG_SYS_JFFS_CUSTOM_PART			/* board defined part	*/
#endif

/*------------------------------------------------------------------------
 * MISC
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_LONGHELP				/* Provide extended help*/
#define CONFIG_SYS_PROMPT		"==> "		/* Command prompt	*/
#define CONFIG_SYS_CBSIZE		256		/* Console I/O buf size */
#define CONFIG_SYS_MAXARGS		16		/* Max command args	*/
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot arg buf size	*/
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buf size */
#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE	/* Default load address */
#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE	/* Start addr for test	*/
#define CONFIG_SYS_MEMTEST_END		CONFIG_SYS_INIT_SP - 0x00020000

#define CONFIG_SYS_HUSH_PARSER

#endif	/* __CONFIG_H */
Commit	Line	Data
5c952cf0 WD	1	/*
	2	* (C) Copyright 2004, Psyent Corporation <www.psyent.com>
	3	* Scott McNutt <smcnutt@psyent.com>
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#ifndef __CONFIG_H
	25	#define __CONFIG_H
	26
	27	/*------------------------------------------------------------------------
	28	* BOARD/CPU
	29	----------------------------------------------------------------------/
	30	#define CONFIG_PK1C20 1 /* PK1C20 board */
	31	#define CONFIG_SYS_CLK_FREQ 50000000 /* 50 MHz core clk */
	32
6d0f6bcf JCPV	33	#define CONFIG_SYS_RESET_ADDR 0x00000000 /* Hard-reset address */
	34	#define CONFIG_SYS_EXCEPTION_ADDR 0x01000020 /* Exception entry point*/
	35	#define CONFIG_SYS_NIOS_SYSID_BASE 0x021208b8 /* System id address */
5c952cf0 WD	36	#define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/
	37
	38	/*------------------------------------------------------------------------
	39	* CACHE -- the following will support II/s and II/f. The II/s does not
	40	* have dcache, so the cache instructions will behave as NOPs.
	41	----------------------------------------------------------------------/
6d0f6bcf JCPV	42	#define CONFIG_SYS_ICACHE_SIZE 4096 /* 4 KByte total */
	43	#define CONFIG_SYS_ICACHELINE_SIZE 32 /* 32 bytes/line */
	44	#define CONFIG_SYS_DCACHE_SIZE 2048 /* 2 KByte (II/f) */
	45	#define CONFIG_SYS_DCACHELINE_SIZE 4 /* 4 bytes/line (II/f) */
5c952cf0 WD	46
	47	/*------------------------------------------------------------------------
	48	* MEMORY BASE ADDRESSES
	49	----------------------------------------------------------------------/
6d0f6bcf JCPV	50	#define CONFIG_SYS_FLASH_BASE 0x00000000 /* FLASH base addr */
	51	#define CONFIG_SYS_FLASH_SIZE 0x00800000 /* 8 MByte */
	52	#define CONFIG_SYS_SDRAM_BASE 0x01000000 /* SDRAM base addr */
	53	#define CONFIG_SYS_SDRAM_SIZE 0x01000000 /* 16 MByte */
	54	#define CONFIG_SYS_SRAM_BASE 0x02000000 /* SRAM base addr */
	55	#define CONFIG_SYS_SRAM_SIZE 0x00100000 /* 1 MB (only 1M mapped)*/
5c952cf0 WD	56
	57	/*------------------------------------------------------------------------
	58	* MEMORY ORGANIZATION
	59	* -Monitor at top.
	60	* -The heap is placed below the monitor.
	61	* -Global data is placed below the heap.
	62	* -The stack is placed below global data (&grows down).
	63	----------------------------------------------------------------------/
6d0f6bcf	64	#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 128k */
6d0f6bcf	65	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
5c952cf0	66
14d0a02a	67	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
6d0f6bcf	68	#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
25ddd1fb	69	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_MALLOC_BASE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	70	#define CONFIG_SYS_INIT_SP CONFIG_SYS_GBL_DATA_OFFSET
5c952cf0 WD	71
	72	/*------------------------------------------------------------------------
	73	* FLASH (AM29LV065D)
	74	----------------------------------------------------------------------/
6d0f6bcf JCPV	75	#define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max # sects per bank */
	76	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max # of flash banks */
	77	#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */
	78	#define CONFIG_SYS_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */
	79	#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char /* flash word size */
5c952cf0 WD	80
5c952cf0 WD	81	/*------------------------------------------------------------------------
6d0f6bcf JCPV	82	* ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
6d0f6bcf JCPV	83	* CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the
5c952cf0 WD	84	* reset address, no? This will keep the environment in user region
	85	* of flash. NOTE: the monitor length must be multiple of sector size
	86	* (which is common practice).
	87	----------------------------------------------------------------------/
5a1aceb0	88	#define CONFIG_ENV_IS_IN_FLASH 1 /* Environment in flash */
0e8d1586	89	#define CONFIG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */
5c952cf0	90	#define CONFIG_ENV_OVERWRITE /* Serial change Ok */
6d0f6bcf	91	#define CONFIG_ENV_ADDR (CONFIG_SYS_RESET_ADDR + CONFIG_SYS_MONITOR_LEN)
5c952cf0 WD	92
	93	/*------------------------------------------------------------------------
	94	* CONSOLE
	95	----------------------------------------------------------------------/
c9d4f46b SM	96	#define CONFIG_ALTERA_UART 1 /* Use altera uart */
c9d4f46b SM	97	#if defined(CONFIG_ALTERA_JTAG_UART)
6d0f6bcf	98	#define CONFIG_SYS_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */
5c952cf0	99	#else
6d0f6bcf	100	#define CONFIG_SYS_NIOS_CONSOLE 0x02120840 /* UART base addr */
5c952cf0 WD	101	#endif
5c952cf0 WD	102
6d0f6bcf	103	#define CONFIG_SYS_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */
5c952cf0	104	#define CONFIG_BAUDRATE 115200 /* Initial baudrate */
6d0f6bcf	105	#define CONFIG_SYS_BAUDRATE_TABLE {115200} /* It's fixed ;-) */
5c952cf0	106
6d0f6bcf	107	#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* Suppress console info*/
5c952cf0	108
0c1c117c	109	/*------------------------------------------------------------------------
6d0f6bcf	110	* EPCS Device -- wne CONFIG_SYS_NIOS_EPCSBASE is defined code/commands for
0c1c117c WD	111	* epcs device access is enabled. The base address is the epcs
0c1c117c WD	112	* _register_ base address, NOT THE ADDRESS OF THE MEMORY BLOCK.
3d22d0b8	113	* The register base is currently at offset 0x600 from the memory base.
0c1c117c	114	----------------------------------------------------------------------/
6d0f6bcf	115	#define CONFIG_SYS_NIOS_EPCSBASE 0x02100200 /* EPCS register base */
0c1c117c	116
5c952cf0 WD	117	/*------------------------------------------------------------------------
	118	* DEBUG
	119	----------------------------------------------------------------------/
	120	#undef CONFIG_ROM_STUBS /* Stubs not in ROM */
	121
	122	/*------------------------------------------------------------------------
	123	* TIMEBASE --
	124	*
	125	* The high res timer defaults to 1 msec. Since it includes the period
3a89a91a SM	126	* registers, the interrupt frequency can be reduced using TMRCNT.
	127	* If the default period is acceptable, TMRCNT can be left undefined.
	128	* TMRMS represents the desired mecs per tick (msecs per interrupt).
5c952cf0	129	----------------------------------------------------------------------/
3a89a91a	130	#define CONFIG_SYS_HZ 1000 /* Always 1000 */
e110c4fe	131	#define CONFIG_SYS_LOW_RES_TIMER
6d0f6bcf	132	#define CONFIG_SYS_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */
3a89a91a SM	133	#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */
	134	#define CONFIG_SYS_NIOS_TMRMS 10 /* Desired period */
	135	#define CONFIG_SYS_NIOS_TMRCNT \
	136	(CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
5c952cf0 WD	137
	138	/*------------------------------------------------------------------------
	139	* STATUS LED -- Provides a simple blinking led. For Nios2 each board
	140	* must implement its own led routines -- leds are, after all,
	141	* board-specific, no?
	142	----------------------------------------------------------------------/
6d0f6bcf	143	#define CONFIG_SYS_LEDPIO_ADDR 0x02120870 /* LED PIO base addr */
5c952cf0	144	#define CONFIG_STATUS_LED /* Enable status driver */
db719642	145	#define CONFIG_BOARD_SPECIFIC_LED
5c952cf0 WD	146
	147	#define STATUS_LED_BIT 1 /* Bit-0 on PIO */
	148	#define STATUS_LED_STATE 1 /* Blinking */
6d0f6bcf	149	#define STATUS_LED_PERIOD (500/CONFIG_SYS_NIOS_TMRMS) /* Every 500 msec */
5c952cf0 WD	150
	151	/*------------------------------------------------------------------------
	152	* ETHERNET -- The header file for the SMC91111 driver hurts my eyes ...
	153	* and really doesn't need any additional clutter. So I choose the lazy
	154	* way out to avoid changes there -- define the base address to ensure
	155	* cache bypass so there's no need to monkey with inx/outx macros.
	156	----------------------------------------------------------------------/
3d22d0b8	157	#define CONFIG_SMC91111_BASE 0x82110300 /* Base addr (bypass) */
7194ab80	158	#define CONFIG_SMC91111 /* Using SMC91c111 */
5c952cf0 WD	159	#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */
	160	#define CONFIG_SMC_USE_32_BIT /* 32-bit interface */
	161
	162	#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
	163	#define CONFIG_NETMASK 255.255.255.0
	164	#define CONFIG_IPADDR 192.168.2.21
	165	#define CONFIG_SERVERIP 192.168.2.16
	166
acf02697	167
a1aa0bb5 JL	168	/*
	169	* BOOTP options
	170	*/
	171	#define CONFIG_BOOTP_BOOTFILESIZE
	172	#define CONFIG_BOOTP_BOOTPATH
	173	#define CONFIG_BOOTP_GATEWAY
	174	#define CONFIG_BOOTP_HOSTNAME
	175
	176
acf02697 JL	177	/*
	178	* Command line configuration.
	179	*/
	180
	181	#define CONFIG_CMD_BDI
	182	#define CONFIG_CMD_DHCP
	183	#define CONFIG_CMD_ECHO
bdab39d3	184	#define CONFIG_CMD_SAVEENV
acf02697 JL	185	#define CONFIG_CMD_FLASH
	186	#define CONFIG_CMD_IMI
	187	#define CONFIG_CMD_IRQ
	188	#define CONFIG_CMD_LOADS
	189	#define CONFIG_CMD_LOADB
	190	#define CONFIG_CMD_MEMORY
	191	#define CONFIG_CMD_MISC
	192	#define CONFIG_CMD_NET
	193	#define CONFIG_CMD_PING
	194	#define CONFIG_CMD_RUN
	195	#define CONFIG_CMD_SAVES
	196
5c952cf0	197
0c1c117c WD	198	/*------------------------------------------------------------------------
	199	* COMPACT FLASH
	200	----------------------------------------------------------------------/
acf02697	201	#if defined(CONFIG_CMD_IDE)
0c1c117c	202	#define CONFIG_IDE_PREINIT /* Implement id_preinit */
6d0f6bcf JCPV	203	#define CONFIG_SYS_IDE_MAXBUS 1 /* 1 IDE bus */
	204	#define CONFIG_SYS_IDE_MAXDEVICE 1 /* 1 drive per IDE bus */
	205
	206	#define CONFIG_SYS_ATA_BASE_ADDR 0x00900800 /* ATA base addr */
	207	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 /* IDE0 offset */
	208	#define CONFIG_SYS_ATA_DATA_OFFSET 0x0040 /* Data IO offset */
	209	#define CONFIG_SYS_ATA_REG_OFFSET 0x0040 /* Register offset */
	210	#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 /* Alternate reg offset */
	211	#define CONFIG_SYS_ATA_STRIDE 4 /* Width betwix addrs */
0c1c117c WD	212	#define CONFIG_DOS_PARTITION
	213
	214	/* Board-specific cf regs */
6d0f6bcf JCPV	215	#define CONFIG_SYS_CF_PRESENT 0x00900880 /* CF Present PIO base */
	216	#define CONFIG_SYS_CF_POWER 0x00900890 /* CF Power FET PIO base*/
	217	#define CONFIG_SYS_CF_ATASEL 0x009008a0 /* CF ATASEL PIO base */
0c1c117c	218
acf02697	219	#endif
0c1c117c WD	220
	221	/*------------------------------------------------------------------------
	222	* JFFS2
	223	----------------------------------------------------------------------/
acf02697	224	#if defined(CONFIG_CMD_JFFS2)
6d0f6bcf	225	#define CONFIG_SYS_JFFS_CUSTOM_PART /* board defined part */
0c1c117c WD	226	#endif
0c1c117c WD	227
5c952cf0 WD	228	/*------------------------------------------------------------------------
	229	* MISC
	230	----------------------------------------------------------------------/
6d0f6bcf JCPV	231	#define CONFIG_SYS_LONGHELP /* Provide extended help*/
	232	#define CONFIG_SYS_PROMPT "==> " /* Command prompt */
	233	#define CONFIG_SYS_CBSIZE 256 /* Console I/O buf size */
	234	#define CONFIG_SYS_MAXARGS 16 /* Max command args */
	235	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot arg buf size */
	236	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buf size */
	237	#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* Default load address */
	238	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE /* Start addr for test */
	239	#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_INIT_SP - 0x00020000
	240
	241	#define CONFIG_SYS_HUSH_PARSER
0c1c117c	242
5c952cf0	243	#endif /* __CONFIG_H */