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13fdf8a6 SR |
1 | /* |
2 | * (C) Copyright 2001-2003 | |
3 | * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * board/config.h - configuration options, board specific | |
26 | */ | |
27 | ||
28 | #ifndef __CONFIG_H | |
29 | #define __CONFIG_H | |
30 | ||
31 | /* | |
32 | * High Level Configuration Options | |
33 | * (easy to change) | |
34 | */ | |
35 | ||
36 | #define CONFIG_405EP 1 /* This is a PPC405 CPU */ | |
c837dcb1 WD |
37 | #define CONFIG_4xx 1 /* ...member of PPC4xx family */ |
38 | #define CONFIG_PLU405 1 /* ...on a PLU405 board */ | |
13fdf8a6 | 39 | |
c837dcb1 WD |
40 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ |
41 | #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ | |
13fdf8a6 | 42 | |
a20b27a3 | 43 | #define CONFIG_SYS_CLK_FREQ 33333400 /* external frequency to pll */ |
13fdf8a6 SR |
44 | |
45 | #define CONFIG_BAUDRATE 9600 | |
13fdf8a6 SR |
46 | |
47 | #undef CONFIG_BOOTARGS | |
a20b27a3 SR |
48 | #undef CONFIG_BOOTCOMMAND |
49 | ||
50 | #define CONFIG_PREBOOT /* enable preboot variable */ | |
51 | ||
6d0f6bcf | 52 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
13fdf8a6 | 53 | |
a20b27a3 | 54 | #define CONFIG_NET_MULTI 1 |
f9fc6a58 | 55 | #undef CONFIG_HAS_ETH1 |
a20b27a3 | 56 | |
96e21f86 | 57 | #define CONFIG_PPC4xx_EMAC |
13fdf8a6 | 58 | #define CONFIG_MII 1 /* MII PHY management */ |
c837dcb1 | 59 | #define CONFIG_PHY_ADDR 0 /* PHY address */ |
a20b27a3 | 60 | #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ |
9ec367aa | 61 | #define CONFIG_RESET_PHY_R 1 /* use reset_phy() */ |
a20b27a3 SR |
62 | |
63 | #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ | |
13fdf8a6 | 64 | |
acf02697 | 65 | |
a1aa0bb5 JL |
66 | /* |
67 | * BOOTP options | |
68 | */ | |
69 | #define CONFIG_BOOTP_BOOTFILESIZE | |
70 | #define CONFIG_BOOTP_BOOTPATH | |
71 | #define CONFIG_BOOTP_GATEWAY | |
72 | #define CONFIG_BOOTP_HOSTNAME | |
73 | ||
74 | ||
acf02697 JL |
75 | /* |
76 | * Command line configuration. | |
77 | */ | |
78 | #include <config_cmd_default.h> | |
79 | ||
80 | #define CONFIG_CMD_DHCP | |
81 | #define CONFIG_CMD_PCI | |
82 | #define CONFIG_CMD_IRQ | |
83 | #define CONFIG_CMD_IDE | |
84 | #define CONFIG_CMD_FAT | |
85 | #define CONFIG_CMD_ELF | |
86 | #define CONFIG_CMD_NAND | |
87 | #define CONFIG_CMD_DATE | |
88 | #define CONFIG_CMD_I2C | |
89 | #define CONFIG_CMD_MII | |
90 | #define CONFIG_CMD_PING | |
91 | #define CONFIG_CMD_EEPROM | |
17e65c21 | 92 | #define CONFIG_CMD_USB |
acf02697 | 93 | |
3bc1054c MF |
94 | #define CONFIG_OF_LIBFDT |
95 | #define CONFIG_OF_BOARD_SETUP | |
13fdf8a6 SR |
96 | |
97 | #define CONFIG_MAC_PARTITION | |
98 | #define CONFIG_DOS_PARTITION | |
99 | ||
a20b27a3 SR |
100 | #define CONFIG_SUPPORT_VFAT |
101 | ||
c837dcb1 | 102 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
13fdf8a6 | 103 | |
c837dcb1 | 104 | #define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/ |
6d0f6bcf | 105 | #define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */ |
13fdf8a6 | 106 | |
c837dcb1 | 107 | #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ |
13fdf8a6 SR |
108 | |
109 | /* | |
110 | * Miscellaneous configurable options | |
111 | */ | |
6d0f6bcf JCPV |
112 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
113 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
13fdf8a6 | 114 | |
6d0f6bcf JCPV |
115 | #undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ |
116 | #ifdef CONFIG_SYS_HUSH_PARSER | |
117 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
13fdf8a6 SR |
118 | #endif |
119 | ||
acf02697 | 120 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 121 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
13fdf8a6 | 122 | #else |
6d0f6bcf | 123 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
13fdf8a6 | 124 | #endif |
6d0f6bcf JCPV |
125 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
126 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
127 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
13fdf8a6 | 128 | |
6d0f6bcf | 129 | #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ |
13fdf8a6 | 130 | |
6d0f6bcf | 131 | #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ |
13fdf8a6 | 132 | |
a20b27a3 SR |
133 | #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ |
134 | ||
6d0f6bcf JCPV |
135 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
136 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
13fdf8a6 | 137 | |
6d0f6bcf | 138 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ |
6d0f6bcf | 139 | #define CONFIG_SYS_BASE_BAUD 691200 |
c837dcb1 | 140 | #undef CONFIG_UART1_CONSOLE /* define for uart1 as console */ |
13fdf8a6 SR |
141 | |
142 | /* The following table includes the supported baudrates */ | |
6d0f6bcf | 143 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
13fdf8a6 SR |
144 | { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ |
145 | 57600, 115200, 230400, 460800, 921600 } | |
146 | ||
6d0f6bcf JCPV |
147 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
148 | #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ | |
13fdf8a6 | 149 | |
6d0f6bcf | 150 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
13fdf8a6 | 151 | |
17e65c21 | 152 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
13fdf8a6 | 153 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ |
a20b27a3 SR |
154 | #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ |
155 | ||
156 | /* Only interrupt boot if space is pressed */ | |
157 | /* If a long serial cable is connected but */ | |
158 | /* other end is dead, garbage will be read */ | |
f2302d44 SR |
159 | #define CONFIG_AUTOBOOT_KEYED 1 |
160 | #define CONFIG_AUTOBOOT_PROMPT \ | |
161 | "Press SPACE to abort autoboot in %d seconds\n", bootdelay | |
a20b27a3 SR |
162 | #undef CONFIG_AUTOBOOT_DELAY_STR |
163 | #define CONFIG_AUTOBOOT_STOP_STR " " | |
13fdf8a6 | 164 | |
c837dcb1 | 165 | #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ |
13fdf8a6 | 166 | |
6d0f6bcf | 167 | #define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ |
13fdf8a6 | 168 | |
9ec367aa | 169 | /* |
13fdf8a6 | 170 | * NAND-FLASH stuff |
13fdf8a6 | 171 | */ |
6d0f6bcf | 172 | #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} |
6d0f6bcf | 173 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ |
bd84ee4c | 174 | #define NAND_BIG_DELAY_US 25 |
addb2e16 | 175 | |
6d0f6bcf JCPV |
176 | #define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ |
177 | #define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ | |
178 | #define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ | |
179 | #define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ | |
13fdf8a6 | 180 | |
6d0f6bcf JCPV |
181 | #define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ |
182 | #define CONFIG_SYS_NAND_QUIET 1 | |
a20b27a3 | 183 | |
9ec367aa | 184 | /* |
13fdf8a6 | 185 | * PCI stuff |
13fdf8a6 | 186 | */ |
a20b27a3 SR |
187 | #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ |
188 | #define PCI_HOST_FORCE 1 /* configure as pci host */ | |
189 | #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ | |
190 | ||
191 | #define CONFIG_PCI /* include pci support */ | |
17e65c21 | 192 | #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ |
a20b27a3 SR |
193 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
194 | /* resource configuration */ | |
195 | ||
196 | #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ | |
197 | ||
198 | #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ | |
199 | ||
6d0f6bcf JCPV |
200 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ |
201 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ | |
202 | #define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ | |
203 | #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ | |
204 | #define CONFIG_SYS_PCI_PTM1MS 0xf8000001 /* 128MB, enable hard-wired to 1 */ | |
205 | #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ | |
206 | #define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */ | |
207 | #define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ | |
208 | #define CONFIG_SYS_PCI_PTM2PCI 0x08000000 /* Host: use this pci address */ | |
13fdf8a6 | 209 | |
9ec367aa | 210 | /* |
13fdf8a6 | 211 | * IDE/ATA stuff |
13fdf8a6 | 212 | */ |
c837dcb1 WD |
213 | #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ |
214 | #undef CONFIG_IDE_LED /* no led for ide supported */ | |
13fdf8a6 SR |
215 | #define CONFIG_IDE_RESET 1 /* reset for ide supported */ |
216 | ||
6d0f6bcf | 217 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */ |
9ec367aa | 218 | /* max. 1 drives per IDE bus */ |
6d0f6bcf | 219 | #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) |
13fdf8a6 | 220 | |
6d0f6bcf JCPV |
221 | #define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000 |
222 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 | |
13fdf8a6 | 223 | |
6d0f6bcf JCPV |
224 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ |
225 | #define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register access */ | |
226 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ | |
13fdf8a6 SR |
227 | |
228 | /* | |
229 | * For booting Linux, the board info and command line data | |
230 | * have to be in the first 8 MB of memory, since this is | |
231 | * the maximum mapped by the Linux kernel during initialization. | |
232 | */ | |
6d0f6bcf | 233 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
9ec367aa MF |
234 | |
235 | /* | |
13fdf8a6 SR |
236 | * FLASH organization |
237 | */ | |
9ec367aa | 238 | #define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ |
13fdf8a6 | 239 | |
6d0f6bcf JCPV |
240 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
241 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ | |
13fdf8a6 | 242 | |
6d0f6bcf JCPV |
243 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
244 | #define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ | |
13fdf8a6 | 245 | |
6d0f6bcf JCPV |
246 | #define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ |
247 | #define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st addr for flash config cycles */ | |
248 | #define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd addr for flash config cycles */ | |
13fdf8a6 SR |
249 | /* |
250 | * The following defines are added for buggy IOP480 byte interface. | |
251 | * All other boards should use the standard values (CPCI405 etc.) | |
252 | */ | |
6d0f6bcf JCPV |
253 | #define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ |
254 | #define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ | |
255 | #define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ | |
13fdf8a6 | 256 | |
6d0f6bcf | 257 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector */ |
13fdf8a6 | 258 | |
9ec367aa | 259 | /* |
13fdf8a6 SR |
260 | * Start addresses for the final memory configuration |
261 | * (Set up by the startup code) | |
6d0f6bcf | 262 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
13fdf8a6 | 263 | */ |
6d0f6bcf | 264 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
985edacc MF |
265 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE |
266 | #define CONFIG_SYS_MONITOR_BASE TEXT_BASE | |
267 | #define CONFIG_SYS_MONITOR_LEN (~(TEXT_BASE) + 1) | |
268 | #define CONFIG_SYS_MALLOC_LEN (1024 << 10) | |
13fdf8a6 | 269 | |
9ec367aa | 270 | /* |
13fdf8a6 SR |
271 | * Environment Variable setup |
272 | */ | |
bb1f8b4f | 273 | #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ |
0e8d1586 JCPV |
274 | #define CONFIG_ENV_OFFSET 0x100 /* reseve 0x100 bytes for strapping */ |
275 | #define CONFIG_ENV_SIZE 0x700 | |
13fdf8a6 | 276 | |
9ec367aa MF |
277 | /* |
278 | * I2C EEPROM (24WC16) for environment | |
13fdf8a6 SR |
279 | */ |
280 | #define CONFIG_HARD_I2C /* I2c with hardware support */ | |
d0b0dcaa | 281 | #define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ |
6d0f6bcf JCPV |
282 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
283 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
13fdf8a6 | 284 | |
6d0f6bcf JCPV |
285 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM 24WC16 */ |
286 | #define CONFIG_SYS_EEPROM_WREN 1 | |
bd84ee4c | 287 | |
9ec367aa | 288 | /* 24WC16 */ |
6d0f6bcf | 289 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ |
9ec367aa | 290 | /* mask of address bits that overflow into the "EEPROM chip address" */ |
6d0f6bcf JCPV |
291 | #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 |
292 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The 24WC16 has */ | |
9ec367aa MF |
293 | /* 16 byte page write mode using */ |
294 | /* last 4 bits of the address */ | |
6d0f6bcf | 295 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
13fdf8a6 | 296 | |
9ec367aa | 297 | /* |
13fdf8a6 SR |
298 | * External Bus Controller (EBC) Setup |
299 | */ | |
be0db3e3 MF |
300 | #define CAN0_BA 0xF0000000 /* CAN0 Base Address */ |
301 | #define CAN1_BA 0xF0000100 /* CAN1 Base Address */ | |
9ec367aa MF |
302 | #define DUART0_BA 0xF0000400 /* DUART Base Address */ |
303 | #define DUART1_BA 0xF0000408 /* DUART Base Address */ | |
304 | #define RTC_BA 0xF0000500 /* RTC Base Address */ | |
305 | #define VGA_BA 0xF1000000 /* Epson VGA Base Address */ | |
6d0f6bcf | 306 | #define CONFIG_SYS_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */ |
9ec367aa MF |
307 | |
308 | /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ | |
309 | /* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */ | |
6d0f6bcf | 310 | #define CONFIG_SYS_EBC_PB0AP 0x92015480 |
9ec367aa | 311 | /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ |
6d0f6bcf | 312 | #define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 |
13fdf8a6 | 313 | |
9ec367aa | 314 | /* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */ |
6d0f6bcf | 315 | #define CONFIG_SYS_EBC_PB1AP 0x92015480 |
9ec367aa | 316 | /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */ |
6d0f6bcf | 317 | #define CONFIG_SYS_EBC_PB1CR 0xF4018000 |
13fdf8a6 | 318 | |
9ec367aa MF |
319 | /* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */ |
320 | /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ | |
6d0f6bcf | 321 | #define CONFIG_SYS_EBC_PB2AP 0x010053C0 |
9ec367aa | 322 | /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ |
6d0f6bcf | 323 | #define CONFIG_SYS_EBC_PB2CR 0xF0018000 |
13fdf8a6 | 324 | |
9ec367aa MF |
325 | /* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */ |
326 | /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ | |
6d0f6bcf | 327 | #define CONFIG_SYS_EBC_PB3AP 0x010053C0 |
9ec367aa | 328 | /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ |
6d0f6bcf | 329 | #define CONFIG_SYS_EBC_PB3CR 0xF011A000 |
13fdf8a6 | 330 | |
9ec367aa | 331 | /* |
13fdf8a6 SR |
332 | * FPGA stuff |
333 | */ | |
6d0f6bcf | 334 | #define CONFIG_SYS_FPGA_BASE_ADDR 0xF0100100 /* FPGA internal Base Address */ |
13fdf8a6 SR |
335 | |
336 | /* FPGA internal regs */ | |
6d0f6bcf | 337 | #define CONFIG_SYS_FPGA_CTRL 0x000 |
13fdf8a6 SR |
338 | |
339 | /* FPGA Control Reg */ | |
6d0f6bcf JCPV |
340 | #define CONFIG_SYS_FPGA_CTRL_CF_RESET 0x0001 |
341 | #define CONFIG_SYS_FPGA_CTRL_WDI 0x0002 | |
342 | #define CONFIG_SYS_FPGA_CTRL_PS2_RESET 0x0020 | |
13fdf8a6 | 343 | |
6d0f6bcf JCPV |
344 | #define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ |
345 | #define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/ | |
13fdf8a6 SR |
346 | |
347 | /* FPGA program pin configuration */ | |
6d0f6bcf JCPV |
348 | #define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ |
349 | #define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ | |
350 | #define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ | |
351 | #define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ | |
352 | #define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ | |
13fdf8a6 | 353 | |
9ec367aa | 354 | /* |
13fdf8a6 SR |
355 | * Definitions for initial stack pointer and data area (in data cache) |
356 | */ | |
357 | /* use on chip memory ( OCM ) for temperary stack until sdram is tested */ | |
6d0f6bcf | 358 | #define CONFIG_SYS_TEMP_STACK_OCM 1 |
13fdf8a6 SR |
359 | |
360 | /* On Chip Memory location */ | |
6d0f6bcf JCPV |
361 | #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 |
362 | #define CONFIG_SYS_OCM_DATA_SIZE 0x1000 | |
363 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ | |
364 | #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */ | |
13fdf8a6 | 365 | |
6d0f6bcf JCPV |
366 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ |
367 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
368 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
13fdf8a6 | 369 | |
9ec367aa | 370 | /* |
13fdf8a6 SR |
371 | * Definitions for GPIO setup (PPC405EP specific) |
372 | * | |
c837dcb1 WD |
373 | * GPIO0[0] - External Bus Controller BLAST output |
374 | * GPIO0[1-9] - Instruction trace outputs -> GPIO | |
13fdf8a6 SR |
375 | * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs |
376 | * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO | |
377 | * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs | |
378 | * GPIO0[24-27] - UART0 control signal inputs/outputs | |
379 | * GPIO0[28-29] - UART1 data signal input/output | |
380 | * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs | |
381 | */ | |
6d0f6bcf JCPV |
382 | #define CONFIG_SYS_GPIO0_OSRH 0x00000550 |
383 | #define CONFIG_SYS_GPIO0_OSRL 0x00000110 | |
384 | #define CONFIG_SYS_GPIO0_ISR1H 0x00000000 | |
385 | #define CONFIG_SYS_GPIO0_ISR1L 0x15555445 | |
386 | #define CONFIG_SYS_GPIO0_TSRH 0x00000000 | |
387 | #define CONFIG_SYS_GPIO0_TSRL 0x00000000 | |
388 | #define CONFIG_SYS_GPIO0_TCR 0x77FE0014 | |
13fdf8a6 | 389 | |
6d0f6bcf JCPV |
390 | #define CONFIG_SYS_DUART_RST (0x80000000 >> 14) |
391 | #define CONFIG_SYS_EEPROM_WP (0x80000000 >> 0) | |
13fdf8a6 SR |
392 | |
393 | /* | |
394 | * Internal Definitions | |
395 | * | |
396 | * Boot Flags | |
397 | */ | |
9ec367aa MF |
398 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
399 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
13fdf8a6 SR |
400 | |
401 | /* | |
9ec367aa | 402 | * Default speed selection (cpu_plb_opb_ebc) in MHz. |
13fdf8a6 SR |
403 | * This value will be set if iic boot eprom is disabled. |
404 | */ | |
17e65c21 | 405 | #if 1 |
c837dcb1 WD |
406 | #define PLLMR0_DEFAULT PLLMR0_266_133_66_33 |
407 | #define PLLMR1_DEFAULT PLLMR1_266_133_66_33 | |
13fdf8a6 SR |
408 | #endif |
409 | #if 0 | |
c837dcb1 WD |
410 | #define PLLMR0_DEFAULT PLLMR0_200_100_50_33 |
411 | #define PLLMR1_DEFAULT PLLMR1_200_100_50_33 | |
13fdf8a6 | 412 | #endif |
17e65c21 | 413 | #if 0 |
c837dcb1 WD |
414 | #define PLLMR0_DEFAULT PLLMR0_133_66_66_33 |
415 | #define PLLMR1_DEFAULT PLLMR1_133_66_66_33 | |
13fdf8a6 SR |
416 | #endif |
417 | ||
17e65c21 MF |
418 | /* |
419 | * PCI OHCI controller | |
420 | */ | |
421 | #define CONFIG_USB_OHCI_NEW 1 | |
422 | #define CONFIG_PCI_OHCI 1 | |
6d0f6bcf JCPV |
423 | #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 |
424 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 | |
425 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" | |
17e65c21 MF |
426 | #define CONFIG_USB_STORAGE 1 |
427 | ||
985edacc MF |
428 | /* |
429 | * UBI | |
430 | */ | |
431 | #define CONFIG_CMD_UBI | |
432 | #define CONFIG_RBTREE | |
433 | #define CONFIG_MTD_DEVICE | |
434 | #define CONFIG_MTD_PARTITIONS | |
435 | #define CONFIG_CMD_MTDPARTS | |
436 | #define CONFIG_LZO | |
437 | ||
13fdf8a6 | 438 | #endif /* __CONFIG_H */ |