[people/ms/u-boot.git] / include / configs / PLU405.h

/*
 * (C) Copyright 2001-2003
 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
#define CONFIG_PLU405		1	/* ...on a PLU405 board		*/

#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/

#define CONFIG_SYS_CLK_FREQ     33333400 /* external frequency to pll   */

#define CONFIG_BAUDRATE		9600

#undef	CONFIG_BOOTARGS
#undef	CONFIG_BOOTCOMMAND

#define CONFIG_PREBOOT                  /* enable preboot variable      */

#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

#define CONFIG_NET_MULTI	1
#undef  CONFIG_HAS_ETH1

#define CONFIG_MII		1	/* MII PHY management		*/
#define CONFIG_PHY_ADDR		0	/* PHY address			*/
#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
#define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */

#define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PCI
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_IDE
#define CONFIG_CMD_FAT
#define CONFIG_CMD_ELF
#define CONFIG_CMD_NAND
#define CONFIG_CMD_DATE
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_EEPROM


#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION

#define CONFIG_SUPPORT_VFAT

#define CONFIG_AUTO_UPDATE      1       /* autoupdate via compactflash  */

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

#define CONFIG_RTC_MC146818		/* DS1685 is MC146818 compatible*/
#define CFG_RTC_REG_BASE_ADDR	 0xF0000500 /* RTC Base Address		*/

#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory		*/
#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/

#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
#ifdef	CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2	"> "
#endif

#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS	16		/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/

#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/

#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */

#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
#define CFG_BASE_BAUD	    691200
#undef	CONFIG_UART1_CONSOLE		/* define for uart1 as console	*/

/* The following table includes the supported baudrates */
#define CFG_BAUDRATE_TABLE	\
	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
	 57600, 115200, 230400, 460800, 921600 }

#define CFG_LOAD_ADDR	0x100000	/* default load address */
#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */

#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */

#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/

/* Only interrupt boot if space is pressed */
/* If a long serial cable is connected but */
/* other end is dead, garbage will be read */
#define CONFIG_AUTOBOOT_KEYED 1
#define CONFIG_AUTOBOOT_PROMPT "Press SPACE to abort autoboot in %d seconds\n"
#undef CONFIG_AUTOBOOT_DELAY_STR
#define CONFIG_AUTOBOOT_STOP_STR " "

#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */

#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */

/*-----------------------------------------------------------------------
 * NAND-FLASH stuff
 *-----------------------------------------------------------------------
 */
#define CFG_NAND_BASE_LIST	{ CFG_NAND_BASE }
#define NAND_MAX_CHIPS          1
#define CFG_MAX_NAND_DEVICE	1         /* Max number of NAND devices */
#define NAND_BIG_DELAY_US	25

#define CFG_NAND_CE             (0x80000000 >> 1)   /* our CE is GPIO1  */
#define CFG_NAND_RDY            (0x80000000 >> 4)   /* our RDY is GPIO4 */
#define CFG_NAND_CLE            (0x80000000 >> 2)   /* our CLE is GPIO2 */
#define CFG_NAND_ALE            (0x80000000 >> 3)   /* our ALE is GPIO3 */

#define CFG_NAND_SKIP_BAD_DOT_I 1       /* ".i" read skips bad blocks   */
#define CFG_NAND_QUIET          1

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
#define PCI_HOST_FORCE  1               /* configure as pci host        */
#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */

#define CONFIG_PCI			/* include pci support	        */
#define CONFIG_PCI_HOST	PCI_HOST_HOST   /* select pci host function     */
#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
					/* resource configuration       */

#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */

#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/

#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
#define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
#define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
#define CFG_PCI_PTM1MS  0xf8000001      /* 128MB, enable hard-wired to 1 */
#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
#define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
#define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */

/*-----------------------------------------------------------------------
 * IDE/ATA stuff
 *-----------------------------------------------------------------------
 */
#undef	CONFIG_IDE_8xx_DIRECT		    /* no pcmcia interface required */
#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
#define CONFIG_IDE_RESET	1	/* reset for ide supported	*/

#define CFG_IDE_MAXBUS		1		/* max. 1 IDE busses	*/
#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */

#define CFG_ATA_BASE_ADDR	0xF0100000
#define CFG_ATA_IDE0_OFFSET	0x0000

#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
#define CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
#define CFG_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/

#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/

#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
/*
 * The following defines are added for buggy IOP480 byte interface.
 * All other boards should use the standard values (CPCI405 etc.)
 */
#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/

#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
#define CFG_SDRAM_BASE		0x00000000
#define CFG_FLASH_BASE		0xFFFC0000
#define CFG_MONITOR_BASE	TEXT_BASE
#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/

#if (CFG_MONITOR_BASE < FLASH_BASE0_PRELIM)
# define CFG_RAMBOOT		1
#else
# undef CFG_RAMBOOT
#endif

/*-----------------------------------------------------------------------
 * Environment Variable setup
 */
#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
#define CFG_ENV_OFFSET		0x100	/* environment starts at the beginning of the EEPROM */
#define CFG_ENV_SIZE		0x700	/* 2048 bytes may be used for env vars*/
				   /* total size of a CAT24WC16 is 2048 bytes */

/*-----------------------------------------------------------------------
 * I2C EEPROM (CAT24WC16) for environment
 */
#define CONFIG_HARD_I2C			/* I2c with hardware support */
#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
#define CFG_I2C_SLAVE		0x7F

#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT24WC08		*/
#define CFG_EEPROM_WREN         1

/* CAT24WC08/16... */
#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
/* mask of address bits that overflow into the "EEPROM chip address"	*/
#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
					/* 16 byte page write mode using*/
					/* last 4 bits of the address	*/
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
#define CFG_EEPROM_PAGE_WRITE_ENABLE

/*-----------------------------------------------------------------------
 * External Bus Controller (EBC) Setup
 */

#define CAN_BA		0xF0000000	    /* CAN Base Address			*/
#define DUART0_BA	0xF0000400	    /* DUART Base Address		*/
#define DUART1_BA	0xF0000408	    /* DUART Base Address		*/
#define RTC_BA		0xF0000500	    /* RTC Base Address			*/
#define VGA_BA		0xF1000000	    /* Epson VGA Base Address		*/
#define CFG_NAND_BASE	0xF4000000	    /* NAND FLASH Base Address		*/

/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
#define CFG_EBC_PB0AP		0x92015480
/*#define CFG_EBC_PB0AP		  0x08055880  /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */

/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization			*/
#define CFG_EBC_PB1AP		0x92015480
#define CFG_EBC_PB1CR		0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit	*/

/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization		*/
#define CFG_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/

/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization	*/
#define CFG_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
#define CFG_EBC_PB3CR		0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */

/*-----------------------------------------------------------------------
 * FPGA stuff
 */

#define CFG_FPGA_BASE_ADDR 0xF0100100	    /* FPGA internal Base Address	*/

/* FPGA internal regs */
#define CFG_FPGA_CTRL		0x000

/* FPGA Control Reg */
#define CFG_FPGA_CTRL_CF_RESET	0x0001
#define CFG_FPGA_CTRL_WDI	0x0002
#define CFG_FPGA_CTRL_PS2_RESET 0x0020

#define CFG_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
#define CFG_FPGA_MAX_SIZE	128*1024    /* 128kByte is enough for XC2S50E*/

/* FPGA program pin configuration */
#define CFG_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
#define CFG_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
#define CFG_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
#define CFG_FPGA_INIT		0x00010000  /* FPGA init pin (ppc input)     */
#define CFG_FPGA_DONE		0x00008000  /* FPGA done pin (ppc input)     */

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in data cache)
 */
/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
#define CFG_TEMP_STACK_OCM	  1

/* On Chip Memory location */
#define CFG_OCM_DATA_ADDR	0xF8000000
#define CFG_OCM_DATA_SIZE	0x1000
#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/

#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Definitions for GPIO setup (PPC405EP specific)
 *
 * GPIO0[0]	- External Bus Controller BLAST output
 * GPIO0[1-9]	- Instruction trace outputs -> GPIO
 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
 * GPIO0[24-27] - UART0 control signal inputs/outputs
 * GPIO0[28-29] - UART1 data signal input/output
 * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
 */
#define CFG_GPIO0_OSRH		0x00000550
#define CFG_GPIO0_OSRL		0x00000110
#define CFG_GPIO0_ISR1H		0x00000000
#define CFG_GPIO0_ISR1L		0x15555445
#define CFG_GPIO0_TSRH		0x00000000
#define CFG_GPIO0_TSRL		0x00000000
#define CFG_GPIO0_TCR		0x77FE0014

#define CFG_DUART_RST		(0x80000000 >> 14)
#define CFG_EEPROM_WP		(0x80000000 >> 0)

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

/*
 * Default speed selection (cpu_plb_opb_ebc) in mhz.
 * This value will be set if iic boot eprom is disabled.
 */
#if 0
#define PLLMR0_DEFAULT	 PLLMR0_266_133_66_33
#define PLLMR1_DEFAULT	 PLLMR1_266_133_66_33
#endif
#if 0
#define PLLMR0_DEFAULT	 PLLMR0_200_100_50_33
#define PLLMR1_DEFAULT	 PLLMR1_200_100_50_33
#endif
#if 1
#define PLLMR0_DEFAULT	 PLLMR0_133_66_66_33
#define PLLMR1_DEFAULT	 PLLMR1_133_66_66_33
#endif

#endif	/* __CONFIG_H */
Commit	Line	Data
13fdf8a6 SR	1	/*
	2	* (C) Copyright 2001-2003
	3	* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* board/config.h - configuration options, board specific
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	/*
	32	* High Level Configuration Options
	33	* (easy to change)
	34	*/
	35
	36	#define CONFIG_405EP 1 /* This is a PPC405 CPU */
c837dcb1 WD	37	#define CONFIG_4xx 1 /* ...member of PPC4xx family */
c837dcb1 WD	38	#define CONFIG_PLU405 1 /* ...on a PLU405 board */
13fdf8a6	39
c837dcb1 WD	40	#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
c837dcb1 WD	41	#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
13fdf8a6	42
a20b27a3	43	#define CONFIG_SYS_CLK_FREQ 33333400 /* external frequency to pll */
13fdf8a6 SR	44
13fdf8a6 SR	45	#define CONFIG_BAUDRATE 9600
13fdf8a6 SR	46
13fdf8a6 SR	47	#undef CONFIG_BOOTARGS
a20b27a3 SR	48	#undef CONFIG_BOOTCOMMAND
	49
	50	#define CONFIG_PREBOOT /* enable preboot variable */
	51
13fdf8a6 SR	52	#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
13fdf8a6 SR	53
a20b27a3	54	#define CONFIG_NET_MULTI 1
f9fc6a58	55	#undef CONFIG_HAS_ETH1
a20b27a3	56
13fdf8a6	57	#define CONFIG_MII 1 /* MII PHY management */
c837dcb1	58	#define CONFIG_PHY_ADDR 0 /* PHY address */
a20b27a3	59	#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
f9fc6a58	60	#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
a20b27a3 SR	61
a20b27a3 SR	62	#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
13fdf8a6	63
acf02697	64
a1aa0bb5 JL	65	/*
	66	* BOOTP options
	67	*/
	68	#define CONFIG_BOOTP_BOOTFILESIZE
	69	#define CONFIG_BOOTP_BOOTPATH
	70	#define CONFIG_BOOTP_GATEWAY
	71	#define CONFIG_BOOTP_HOSTNAME
	72
	73
acf02697 JL	74	/*
	75	* Command line configuration.
	76	*/
	77	#include <config_cmd_default.h>
	78
	79	#define CONFIG_CMD_DHCP
	80	#define CONFIG_CMD_PCI
	81	#define CONFIG_CMD_IRQ
	82	#define CONFIG_CMD_IDE
	83	#define CONFIG_CMD_FAT
	84	#define CONFIG_CMD_ELF
	85	#define CONFIG_CMD_NAND
	86	#define CONFIG_CMD_DATE
	87	#define CONFIG_CMD_I2C
	88	#define CONFIG_CMD_MII
	89	#define CONFIG_CMD_PING
	90	#define CONFIG_CMD_EEPROM
	91
13fdf8a6 SR	92
	93	#define CONFIG_MAC_PARTITION
	94	#define CONFIG_DOS_PARTITION
	95
a20b27a3 SR	96	#define CONFIG_SUPPORT_VFAT
	97
	98	#define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */
a20b27a3	99
c837dcb1	100	#undef CONFIG_WATCHDOG /* watchdog disabled */
13fdf8a6	101
c837dcb1 WD	102	#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
c837dcb1 WD	103	#define CFG_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
13fdf8a6	104
c837dcb1	105	#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
13fdf8a6 SR	106
	107	/*
	108	* Miscellaneous configurable options
	109	*/
	110	#define CFG_LONGHELP /* undef to save memory */
	111	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	112
	113	#undef CFG_HUSH_PARSER /* use "hush" command parser */
	114	#ifdef CFG_HUSH_PARSER
c837dcb1	115	#define CFG_PROMPT_HUSH_PS2 "> "
13fdf8a6 SR	116	#endif
13fdf8a6 SR	117
acf02697	118	#if defined(CONFIG_CMD_KGDB)
c837dcb1	119	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
13fdf8a6	120	#else
c837dcb1	121	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
13fdf8a6 SR	122	#endif
	123	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	124	#define CFG_MAXARGS 16 /* max number of command args */
	125	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	126
c837dcb1	127	#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
13fdf8a6	128
c837dcb1	129	#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
13fdf8a6	130
a20b27a3 SR	131	#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
a20b27a3 SR	132
13fdf8a6 SR	133	#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
	134	#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
	135
c837dcb1 WD	136	#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
	137	#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
	138	#define CFG_BASE_BAUD 691200
	139	#undef CONFIG_UART1_CONSOLE /* define for uart1 as console */
13fdf8a6 SR	140
13fdf8a6 SR	141	/* The following table includes the supported baudrates */
c837dcb1	142	#define CFG_BAUDRATE_TABLE \
13fdf8a6 SR	143	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
	144	57600, 115200, 230400, 460800, 921600 }
	145
	146	#define CFG_LOAD_ADDR 0x100000 /* default load address */
	147	#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
	148
c837dcb1	149	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
13fdf8a6 SR	150
13fdf8a6 SR	151	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
a20b27a3 SR	152	#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
	153
	154	/* Only interrupt boot if space is pressed */
	155	/* If a long serial cable is connected but */
	156	/* other end is dead, garbage will be read */
	157	#define CONFIG_AUTOBOOT_KEYED 1
	158	#define CONFIG_AUTOBOOT_PROMPT "Press SPACE to abort autoboot in %d seconds\n"
	159	#undef CONFIG_AUTOBOOT_DELAY_STR
	160	#define CONFIG_AUTOBOOT_STOP_STR " "
13fdf8a6	161
c837dcb1	162	#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
13fdf8a6	163
c837dcb1	164	#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
13fdf8a6 SR	165
	166	/*-----------------------------------------------------------------------
	167	* NAND-FLASH stuff
	168	*-----------------------------------------------------------------------
	169	*/
bd84ee4c MF	170	#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
	171	#define NAND_MAX_CHIPS 1
	172	#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
	173	#define NAND_BIG_DELAY_US 25
addb2e16	174
bd84ee4c MF	175	#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
	176	#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
	177	#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
	178	#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
13fdf8a6	179
c750d2e6 MF	180	#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
c750d2e6 MF	181	#define CFG_NAND_QUIET 1
a20b27a3	182
13fdf8a6 SR	183	/*-----------------------------------------------------------------------
	184	* PCI stuff
	185	*-----------------------------------------------------------------------
	186	*/
a20b27a3 SR	187	#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
	188	#define PCI_HOST_FORCE 1 /* configure as pci host */
	189	#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
	190
	191	#define CONFIG_PCI /* include pci support */
	192	#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */
	193	#define CONFIG_PCI_PNP /* do pci plug-and-play */
	194	/* resource configuration */
	195
	196	#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
	197
	198	#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
	199
	200	#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
	201	#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
	202	#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
	203	#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
81b83c9e	204	#define CFG_PCI_PTM1MS 0xf8000001 /* 128MB, enable hard-wired to 1 */
a20b27a3 SR	205	#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
	206	#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
	207	#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
	208	#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
13fdf8a6 SR	209
	210	/*-----------------------------------------------------------------------
	211	* IDE/ATA stuff
	212	*-----------------------------------------------------------------------
	213	*/
c837dcb1 WD	214	#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
c837dcb1 WD	215	#undef CONFIG_IDE_LED /* no led for ide supported */
13fdf8a6 SR	216	#define CONFIG_IDE_RESET 1 /* reset for ide supported */
13fdf8a6 SR	217
c837dcb1 WD	218	#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
c837dcb1 WD	219	#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS1) / max. 1 drives per IDE bus */
13fdf8a6	220
c837dcb1 WD	221	#define CFG_ATA_BASE_ADDR 0xF0100000
c837dcb1 WD	222	#define CFG_ATA_IDE0_OFFSET 0x0000
13fdf8a6 SR	223
13fdf8a6 SR	224	#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
c837dcb1	225	#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
13fdf8a6 SR	226	#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
	227
	228	/*
	229	* For booting Linux, the board info and command line data
	230	* have to be in the first 8 MB of memory, since this is
	231	* the maximum mapped by the Linux kernel during initialization.
	232	*/
	233	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	234	/*-----------------------------------------------------------------------
	235	* FLASH organization
	236	*/
	237	#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
	238
	239	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
	240	#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
	241
	242	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
	243	#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
	244
c837dcb1 WD	245	#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
	246	#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
	247	#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
13fdf8a6 SR	248	/*
	249	* The following defines are added for buggy IOP480 byte interface.
	250	* All other boards should use the standard values (CPCI405 etc.)
	251	*/
c837dcb1 WD	252	#define CFG_FLASH_READ0 0x0000 /* 0 is standard */
	253	#define CFG_FLASH_READ1 0x0001 /* 1 is standard */
	254	#define CFG_FLASH_READ2 0x0002 /* 2 is standard */
13fdf8a6	255
c837dcb1	256	#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
13fdf8a6	257
13fdf8a6 SR	258	/*-----------------------------------------------------------------------
	259	* Start addresses for the final memory configuration
	260	* (Set up by the startup code)
	261	* Please note that CFG_SDRAM_BASE _must_ start at 0
	262	*/
	263	#define CFG_SDRAM_BASE 0x00000000
	264	#define CFG_FLASH_BASE 0xFFFC0000
	265	#define CFG_MONITOR_BASE TEXT_BASE
	266	#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
	267	#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
	268
	269	#if (CFG_MONITOR_BASE < FLASH_BASE0_PRELIM)
	270	# define CFG_RAMBOOT 1
	271	#else
	272	# undef CFG_RAMBOOT
	273	#endif
	274
	275	/*-----------------------------------------------------------------------
	276	* Environment Variable setup
	277	*/
c837dcb1 WD	278	#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
	279	#define CFG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
	280	#define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
13fdf8a6 SR	281	/* total size of a CAT24WC16 is 2048 bytes */
13fdf8a6 SR	282
13fdf8a6 SR	283	/*-----------------------------------------------------------------------
	284	* I2C EEPROM (CAT24WC16) for environment
	285	*/
	286	#define CONFIG_HARD_I2C /* I2c with hardware support */
	287	#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
	288	#define CFG_I2C_SLAVE 0x7F
	289
	290	#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */
f6e0f1f6	291	#define CFG_EEPROM_WREN 1
bd84ee4c	292
13fdf8a6	293	/* CAT24WC08/16... */
c837dcb1 WD	294	#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
c837dcb1 WD	295	/* mask of address bits that overflow into the "EEPROM chip address" */
13fdf8a6 SR	296	#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
	297	#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
	298	/* 16 byte page write mode using*/
c837dcb1	299	/* last 4 bits of the address */
13fdf8a6 SR	300	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
	301	#define CFG_EEPROM_PAGE_WRITE_ENABLE
	302
13fdf8a6 SR	303	/*-----------------------------------------------------------------------
	304	* External Bus Controller (EBC) Setup
	305	*/
	306
c837dcb1 WD	307	#define CAN_BA 0xF0000000 /* CAN Base Address */
	308	#define DUART0_BA 0xF0000400 /* DUART Base Address */
	309	#define DUART1_BA 0xF0000408 /* DUART Base Address */
	310	#define RTC_BA 0xF0000500 /* RTC Base Address */
	311	#define VGA_BA 0xF1000000 /* Epson VGA Base Address */
	312	#define CFG_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */
13fdf8a6	313
c837dcb1 WD	314	/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
	315	#define CFG_EBC_PB0AP 0x92015480
	316	/#define CFG_EBC_PB0AP 0x08055880 /XXX TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
	317	#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
13fdf8a6	318
c837dcb1 WD	319	/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */
	320	#define CFG_EBC_PB1AP 0x92015480
	321	#define CFG_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */
13fdf8a6	322
c837dcb1 WD	323	/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
	324	#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
	325	#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
13fdf8a6	326
c837dcb1 WD	327	/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */
	328	#define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
	329	#define CFG_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
13fdf8a6 SR	330
	331	/*-----------------------------------------------------------------------
	332	* FPGA stuff
	333	*/
	334
c837dcb1	335	#define CFG_FPGA_BASE_ADDR 0xF0100100 /* FPGA internal Base Address */
13fdf8a6 SR	336
13fdf8a6 SR	337	/* FPGA internal regs */
c837dcb1	338	#define CFG_FPGA_CTRL 0x000
13fdf8a6 SR	339
13fdf8a6 SR	340	/* FPGA Control Reg */
c837dcb1 WD	341	#define CFG_FPGA_CTRL_CF_RESET 0x0001
c837dcb1 WD	342	#define CFG_FPGA_CTRL_WDI 0x0002
13fdf8a6 SR	343	#define CFG_FPGA_CTRL_PS2_RESET 0x0020
13fdf8a6 SR	344
c837dcb1 WD	345	#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
c837dcb1 WD	346	#define CFG_FPGA_MAX_SIZE 1281024 / 128kByte is enough for XC2S50E*/
13fdf8a6 SR	347
13fdf8a6 SR	348	/* FPGA program pin configuration */
c837dcb1 WD	349	#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
	350	#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
	351	#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
	352	#define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
	353	#define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
13fdf8a6 SR	354
	355	/*-----------------------------------------------------------------------
	356	* Definitions for initial stack pointer and data area (in data cache)
	357	*/
	358	/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
c837dcb1	359	#define CFG_TEMP_STACK_OCM 1
13fdf8a6 SR	360
	361	/* On Chip Memory location */
	362	#define CFG_OCM_DATA_ADDR 0xF8000000
	363	#define CFG_OCM_DATA_SIZE 0x1000
	364	#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
	365	#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
	366
	367	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	368	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
c837dcb1	369	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
13fdf8a6 SR	370
	371	/*-----------------------------------------------------------------------
	372	* Definitions for GPIO setup (PPC405EP specific)
	373	*
c837dcb1 WD	374	* GPIO0[0] - External Bus Controller BLAST output
c837dcb1 WD	375	* GPIO0[1-9] - Instruction trace outputs -> GPIO
13fdf8a6 SR	376	* GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
	377	* GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
	378	* GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
	379	* GPIO0[24-27] - UART0 control signal inputs/outputs
	380	* GPIO0[28-29] - UART1 data signal input/output
	381	* GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
	382	*/
f6e0f1f6	383	#define CFG_GPIO0_OSRH 0x00000550
c837dcb1 WD	384	#define CFG_GPIO0_OSRL 0x00000110
	385	#define CFG_GPIO0_ISR1H 0x00000000
	386	#define CFG_GPIO0_ISR1L 0x15555445
	387	#define CFG_GPIO0_TSRH 0x00000000
	388	#define CFG_GPIO0_TSRL 0x00000000
f6e0f1f6	389	#define CFG_GPIO0_TCR 0x77FE0014
13fdf8a6	390
c837dcb1	391	#define CFG_DUART_RST (0x80000000 >> 14)
f6e0f1f6	392	#define CFG_EEPROM_WP (0x80000000 >> 0)
13fdf8a6 SR	393
	394	/*
	395	* Internal Definitions
	396	*
	397	* Boot Flags
	398	*/
	399	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	400	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	401
	402	/*
	403	* Default speed selection (cpu_plb_opb_ebc) in mhz.
	404	* This value will be set if iic boot eprom is disabled.
	405	*/
	406	#if 0
c837dcb1 WD	407	#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
c837dcb1 WD	408	#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
13fdf8a6 SR	409	#endif
13fdf8a6 SR	410	#if 0
c837dcb1 WD	411	#define PLLMR0_DEFAULT PLLMR0_200_100_50_33
c837dcb1 WD	412	#define PLLMR1_DEFAULT PLLMR1_200_100_50_33
13fdf8a6 SR	413	#endif
13fdf8a6 SR	414	#if 1
c837dcb1 WD	415	#define PLLMR0_DEFAULT PLLMR0_133_66_66_33
c837dcb1 WD	416	#define PLLMR1_DEFAULT PLLMR1_133_66_66_33
13fdf8a6 SR	417	#endif
	418
	419	#endif /* __CONFIG_H */