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Commit | Line | Data |
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13fdf8a6 SR |
1 | /* |
2 | * (C) Copyright 2001-2003 | |
3 | * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com | |
4 | * | |
3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
13fdf8a6 SR |
6 | */ |
7 | ||
8 | /* | |
9 | * board/config.h - configuration options, board specific | |
10 | */ | |
11 | ||
12 | #ifndef __CONFIG_H | |
13 | #define __CONFIG_H | |
14 | ||
15 | /* | |
16 | * High Level Configuration Options | |
17 | * (easy to change) | |
18 | */ | |
19 | ||
20 | #define CONFIG_405EP 1 /* This is a PPC405 CPU */ | |
c837dcb1 | 21 | #define CONFIG_PLU405 1 /* ...on a PLU405 board */ |
13fdf8a6 | 22 | |
2ae18241 | 23 | #define CONFIG_SYS_TEXT_BASE 0xFFF80000 |
a5ee5c69 MF |
24 | #define CONFIG_SYS_GENERIC_BOARD |
25 | #define CONFIG_DISPLAY_BOARDINFO | |
2ae18241 | 26 | |
c837dcb1 WD |
27 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ |
28 | #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ | |
13fdf8a6 | 29 | |
a20b27a3 | 30 | #define CONFIG_SYS_CLK_FREQ 33333400 /* external frequency to pll */ |
13fdf8a6 SR |
31 | |
32 | #define CONFIG_BAUDRATE 9600 | |
13fdf8a6 SR |
33 | |
34 | #undef CONFIG_BOOTARGS | |
a20b27a3 SR |
35 | #undef CONFIG_BOOTCOMMAND |
36 | ||
37 | #define CONFIG_PREBOOT /* enable preboot variable */ | |
38 | ||
6d0f6bcf | 39 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
13fdf8a6 | 40 | |
f9fc6a58 | 41 | #undef CONFIG_HAS_ETH1 |
a20b27a3 | 42 | |
96e21f86 | 43 | #define CONFIG_PPC4xx_EMAC |
13fdf8a6 | 44 | #define CONFIG_MII 1 /* MII PHY management */ |
c837dcb1 | 45 | #define CONFIG_PHY_ADDR 0 /* PHY address */ |
a20b27a3 | 46 | #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ |
9ec367aa | 47 | #define CONFIG_RESET_PHY_R 1 /* use reset_phy() */ |
a20b27a3 SR |
48 | |
49 | #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ | |
13fdf8a6 | 50 | |
acf02697 | 51 | |
a1aa0bb5 JL |
52 | /* |
53 | * BOOTP options | |
54 | */ | |
55 | #define CONFIG_BOOTP_BOOTFILESIZE | |
56 | #define CONFIG_BOOTP_BOOTPATH | |
57 | #define CONFIG_BOOTP_GATEWAY | |
58 | #define CONFIG_BOOTP_HOSTNAME | |
59 | ||
60 | ||
acf02697 JL |
61 | /* |
62 | * Command line configuration. | |
63 | */ | |
acf02697 JL |
64 | #define CONFIG_CMD_DHCP |
65 | #define CONFIG_CMD_PCI | |
66 | #define CONFIG_CMD_IRQ | |
67 | #define CONFIG_CMD_IDE | |
68 | #define CONFIG_CMD_FAT | |
69 | #define CONFIG_CMD_ELF | |
70 | #define CONFIG_CMD_NAND | |
71 | #define CONFIG_CMD_DATE | |
72 | #define CONFIG_CMD_I2C | |
73 | #define CONFIG_CMD_MII | |
74 | #define CONFIG_CMD_PING | |
75 | #define CONFIG_CMD_EEPROM | |
17e65c21 | 76 | #define CONFIG_CMD_USB |
acf02697 | 77 | |
3bc1054c MF |
78 | #define CONFIG_OF_LIBFDT |
79 | #define CONFIG_OF_BOARD_SETUP | |
13fdf8a6 SR |
80 | |
81 | #define CONFIG_MAC_PARTITION | |
82 | #define CONFIG_DOS_PARTITION | |
83 | ||
a20b27a3 SR |
84 | #define CONFIG_SUPPORT_VFAT |
85 | ||
c837dcb1 | 86 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
13fdf8a6 | 87 | |
c837dcb1 | 88 | #define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/ |
6d0f6bcf | 89 | #define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */ |
13fdf8a6 | 90 | |
c837dcb1 | 91 | #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ |
13fdf8a6 SR |
92 | |
93 | /* | |
94 | * Miscellaneous configurable options | |
95 | */ | |
6d0f6bcf | 96 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
13fdf8a6 | 97 | |
6d0f6bcf | 98 | #undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ |
13fdf8a6 | 99 | |
acf02697 | 100 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 101 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
13fdf8a6 | 102 | #else |
6d0f6bcf | 103 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
13fdf8a6 | 104 | #endif |
6d0f6bcf JCPV |
105 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
106 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
107 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
13fdf8a6 | 108 | |
6d0f6bcf | 109 | #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ |
13fdf8a6 | 110 | |
6d0f6bcf | 111 | #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ |
13fdf8a6 | 112 | |
a20b27a3 SR |
113 | #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ |
114 | ||
6d0f6bcf JCPV |
115 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
116 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
13fdf8a6 | 117 | |
550650dd SR |
118 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
119 | #define CONFIG_SYS_NS16550 | |
120 | #define CONFIG_SYS_NS16550_SERIAL | |
121 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
122 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() | |
123 | ||
6d0f6bcf | 124 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ |
6d0f6bcf | 125 | #define CONFIG_SYS_BASE_BAUD 691200 |
13fdf8a6 SR |
126 | |
127 | /* The following table includes the supported baudrates */ | |
6d0f6bcf | 128 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
13fdf8a6 SR |
129 | { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ |
130 | 57600, 115200, 230400, 460800, 921600 } | |
131 | ||
6d0f6bcf JCPV |
132 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
133 | #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ | |
13fdf8a6 | 134 | |
17e65c21 | 135 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
13fdf8a6 | 136 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ |
a20b27a3 SR |
137 | #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ |
138 | ||
c837dcb1 | 139 | #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ |
13fdf8a6 | 140 | |
6d0f6bcf | 141 | #define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ |
13fdf8a6 | 142 | |
9ec367aa | 143 | /* |
13fdf8a6 | 144 | * NAND-FLASH stuff |
13fdf8a6 | 145 | */ |
6d0f6bcf | 146 | #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} |
6d0f6bcf | 147 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ |
bd84ee4c | 148 | #define NAND_BIG_DELAY_US 25 |
addb2e16 | 149 | |
6d0f6bcf JCPV |
150 | #define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ |
151 | #define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ | |
152 | #define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ | |
153 | #define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ | |
13fdf8a6 | 154 | |
6d0f6bcf JCPV |
155 | #define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ |
156 | #define CONFIG_SYS_NAND_QUIET 1 | |
a20b27a3 | 157 | |
9ec367aa | 158 | /* |
13fdf8a6 | 159 | * PCI stuff |
13fdf8a6 | 160 | */ |
a20b27a3 SR |
161 | #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ |
162 | #define PCI_HOST_FORCE 1 /* configure as pci host */ | |
163 | #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ | |
164 | ||
165 | #define CONFIG_PCI /* include pci support */ | |
842033e6 | 166 | #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ |
17e65c21 | 167 | #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ |
a20b27a3 SR |
168 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
169 | /* resource configuration */ | |
170 | ||
171 | #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ | |
172 | ||
173 | #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ | |
174 | ||
6d0f6bcf JCPV |
175 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ |
176 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ | |
177 | #define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ | |
178 | #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ | |
179 | #define CONFIG_SYS_PCI_PTM1MS 0xf8000001 /* 128MB, enable hard-wired to 1 */ | |
180 | #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ | |
181 | #define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */ | |
182 | #define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ | |
183 | #define CONFIG_SYS_PCI_PTM2PCI 0x08000000 /* Host: use this pci address */ | |
13fdf8a6 | 184 | |
9ec367aa | 185 | /* |
13fdf8a6 | 186 | * IDE/ATA stuff |
13fdf8a6 | 187 | */ |
c837dcb1 WD |
188 | #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ |
189 | #undef CONFIG_IDE_LED /* no led for ide supported */ | |
13fdf8a6 SR |
190 | #define CONFIG_IDE_RESET 1 /* reset for ide supported */ |
191 | ||
6d0f6bcf | 192 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */ |
9ec367aa | 193 | /* max. 1 drives per IDE bus */ |
6d0f6bcf | 194 | #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) |
13fdf8a6 | 195 | |
6d0f6bcf JCPV |
196 | #define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000 |
197 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 | |
13fdf8a6 | 198 | |
6d0f6bcf JCPV |
199 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ |
200 | #define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register access */ | |
201 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ | |
13fdf8a6 SR |
202 | |
203 | /* | |
204 | * For booting Linux, the board info and command line data | |
205 | * have to be in the first 8 MB of memory, since this is | |
206 | * the maximum mapped by the Linux kernel during initialization. | |
207 | */ | |
6d0f6bcf | 208 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
9ec367aa MF |
209 | |
210 | /* | |
13fdf8a6 SR |
211 | * FLASH organization |
212 | */ | |
9ec367aa | 213 | #define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ |
13fdf8a6 | 214 | |
6d0f6bcf JCPV |
215 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
216 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ | |
13fdf8a6 | 217 | |
6d0f6bcf JCPV |
218 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
219 | #define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ | |
13fdf8a6 | 220 | |
6d0f6bcf JCPV |
221 | #define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ |
222 | #define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st addr for flash config cycles */ | |
223 | #define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd addr for flash config cycles */ | |
13fdf8a6 SR |
224 | /* |
225 | * The following defines are added for buggy IOP480 byte interface. | |
226 | * All other boards should use the standard values (CPCI405 etc.) | |
227 | */ | |
6d0f6bcf JCPV |
228 | #define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ |
229 | #define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ | |
230 | #define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ | |
13fdf8a6 | 231 | |
6d0f6bcf | 232 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector */ |
13fdf8a6 | 233 | |
9ec367aa | 234 | /* |
13fdf8a6 SR |
235 | * Start addresses for the final memory configuration |
236 | * (Set up by the startup code) | |
6d0f6bcf | 237 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
13fdf8a6 | 238 | */ |
6d0f6bcf | 239 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
985edacc | 240 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE |
14d0a02a WD |
241 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
242 | #define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1) | |
985edacc | 243 | #define CONFIG_SYS_MALLOC_LEN (1024 << 10) |
13fdf8a6 | 244 | |
9ec367aa | 245 | /* |
13fdf8a6 SR |
246 | * Environment Variable setup |
247 | */ | |
bb1f8b4f | 248 | #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ |
0e8d1586 JCPV |
249 | #define CONFIG_ENV_OFFSET 0x100 /* reseve 0x100 bytes for strapping */ |
250 | #define CONFIG_ENV_SIZE 0x700 | |
13fdf8a6 | 251 | |
9ec367aa MF |
252 | /* |
253 | * I2C EEPROM (24WC16) for environment | |
13fdf8a6 | 254 | */ |
880540de DE |
255 | #define CONFIG_SYS_I2C |
256 | #define CONFIG_SYS_I2C_PPC4XX | |
257 | #define CONFIG_SYS_I2C_PPC4XX_CH0 | |
258 | #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 | |
259 | #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F | |
13fdf8a6 | 260 | |
6d0f6bcf JCPV |
261 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM 24WC16 */ |
262 | #define CONFIG_SYS_EEPROM_WREN 1 | |
bd84ee4c | 263 | |
9ec367aa | 264 | /* 24WC16 */ |
6d0f6bcf | 265 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ |
9ec367aa | 266 | /* mask of address bits that overflow into the "EEPROM chip address" */ |
6d0f6bcf JCPV |
267 | #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 |
268 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The 24WC16 has */ | |
9ec367aa MF |
269 | /* 16 byte page write mode using */ |
270 | /* last 4 bits of the address */ | |
6d0f6bcf | 271 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
13fdf8a6 | 272 | |
9ec367aa | 273 | /* |
13fdf8a6 SR |
274 | * External Bus Controller (EBC) Setup |
275 | */ | |
be0db3e3 MF |
276 | #define CAN0_BA 0xF0000000 /* CAN0 Base Address */ |
277 | #define CAN1_BA 0xF0000100 /* CAN1 Base Address */ | |
9ec367aa MF |
278 | #define DUART0_BA 0xF0000400 /* DUART Base Address */ |
279 | #define DUART1_BA 0xF0000408 /* DUART Base Address */ | |
280 | #define RTC_BA 0xF0000500 /* RTC Base Address */ | |
281 | #define VGA_BA 0xF1000000 /* Epson VGA Base Address */ | |
6d0f6bcf | 282 | #define CONFIG_SYS_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */ |
9ec367aa MF |
283 | |
284 | /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ | |
285 | /* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */ | |
6d0f6bcf | 286 | #define CONFIG_SYS_EBC_PB0AP 0x92015480 |
9ec367aa | 287 | /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ |
6d0f6bcf | 288 | #define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 |
13fdf8a6 | 289 | |
9ec367aa | 290 | /* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */ |
6d0f6bcf | 291 | #define CONFIG_SYS_EBC_PB1AP 0x92015480 |
9ec367aa | 292 | /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */ |
6d0f6bcf | 293 | #define CONFIG_SYS_EBC_PB1CR 0xF4018000 |
13fdf8a6 | 294 | |
9ec367aa MF |
295 | /* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */ |
296 | /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ | |
6d0f6bcf | 297 | #define CONFIG_SYS_EBC_PB2AP 0x010053C0 |
9ec367aa | 298 | /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ |
6d0f6bcf | 299 | #define CONFIG_SYS_EBC_PB2CR 0xF0018000 |
13fdf8a6 | 300 | |
9ec367aa MF |
301 | /* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */ |
302 | /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ | |
6d0f6bcf | 303 | #define CONFIG_SYS_EBC_PB3AP 0x010053C0 |
9ec367aa | 304 | /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ |
6d0f6bcf | 305 | #define CONFIG_SYS_EBC_PB3CR 0xF011A000 |
13fdf8a6 | 306 | |
9ec367aa | 307 | /* |
13fdf8a6 SR |
308 | * FPGA stuff |
309 | */ | |
6d0f6bcf | 310 | #define CONFIG_SYS_FPGA_BASE_ADDR 0xF0100100 /* FPGA internal Base Address */ |
13fdf8a6 SR |
311 | |
312 | /* FPGA internal regs */ | |
6d0f6bcf | 313 | #define CONFIG_SYS_FPGA_CTRL 0x000 |
13fdf8a6 SR |
314 | |
315 | /* FPGA Control Reg */ | |
6d0f6bcf JCPV |
316 | #define CONFIG_SYS_FPGA_CTRL_CF_RESET 0x0001 |
317 | #define CONFIG_SYS_FPGA_CTRL_WDI 0x0002 | |
318 | #define CONFIG_SYS_FPGA_CTRL_PS2_RESET 0x0020 | |
13fdf8a6 | 319 | |
6d0f6bcf JCPV |
320 | #define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ |
321 | #define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/ | |
13fdf8a6 SR |
322 | |
323 | /* FPGA program pin configuration */ | |
6d0f6bcf JCPV |
324 | #define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ |
325 | #define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ | |
326 | #define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ | |
327 | #define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ | |
328 | #define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ | |
13fdf8a6 | 329 | |
9ec367aa | 330 | /* |
13fdf8a6 SR |
331 | * Definitions for initial stack pointer and data area (in data cache) |
332 | */ | |
333 | /* use on chip memory ( OCM ) for temperary stack until sdram is tested */ | |
6d0f6bcf | 334 | #define CONFIG_SYS_TEMP_STACK_OCM 1 |
13fdf8a6 SR |
335 | |
336 | /* On Chip Memory location */ | |
6d0f6bcf JCPV |
337 | #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 |
338 | #define CONFIG_SYS_OCM_DATA_SIZE 0x1000 | |
339 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ | |
553f0982 | 340 | #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ |
13fdf8a6 | 341 | |
25ddd1fb | 342 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 343 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
13fdf8a6 | 344 | |
9ec367aa | 345 | /* |
13fdf8a6 SR |
346 | * Definitions for GPIO setup (PPC405EP specific) |
347 | * | |
c837dcb1 WD |
348 | * GPIO0[0] - External Bus Controller BLAST output |
349 | * GPIO0[1-9] - Instruction trace outputs -> GPIO | |
13fdf8a6 SR |
350 | * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs |
351 | * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO | |
352 | * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs | |
353 | * GPIO0[24-27] - UART0 control signal inputs/outputs | |
354 | * GPIO0[28-29] - UART1 data signal input/output | |
355 | * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs | |
356 | */ | |
afabb498 SR |
357 | #define CONFIG_SYS_GPIO0_OSRL 0x00000550 |
358 | #define CONFIG_SYS_GPIO0_OSRH 0x00000110 | |
359 | #define CONFIG_SYS_GPIO0_ISR1L 0x00000000 | |
360 | #define CONFIG_SYS_GPIO0_ISR1H 0x15555445 | |
6d0f6bcf | 361 | #define CONFIG_SYS_GPIO0_TSRL 0x00000000 |
afabb498 | 362 | #define CONFIG_SYS_GPIO0_TSRH 0x00000000 |
6d0f6bcf | 363 | #define CONFIG_SYS_GPIO0_TCR 0x77FE0014 |
13fdf8a6 | 364 | |
6d0f6bcf JCPV |
365 | #define CONFIG_SYS_DUART_RST (0x80000000 >> 14) |
366 | #define CONFIG_SYS_EEPROM_WP (0x80000000 >> 0) | |
13fdf8a6 | 367 | |
13fdf8a6 | 368 | /* |
9ec367aa | 369 | * Default speed selection (cpu_plb_opb_ebc) in MHz. |
13fdf8a6 SR |
370 | * This value will be set if iic boot eprom is disabled. |
371 | */ | |
17e65c21 | 372 | #if 1 |
c837dcb1 WD |
373 | #define PLLMR0_DEFAULT PLLMR0_266_133_66_33 |
374 | #define PLLMR1_DEFAULT PLLMR1_266_133_66_33 | |
13fdf8a6 SR |
375 | #endif |
376 | #if 0 | |
c837dcb1 WD |
377 | #define PLLMR0_DEFAULT PLLMR0_200_100_50_33 |
378 | #define PLLMR1_DEFAULT PLLMR1_200_100_50_33 | |
13fdf8a6 | 379 | #endif |
17e65c21 | 380 | #if 0 |
c837dcb1 WD |
381 | #define PLLMR0_DEFAULT PLLMR0_133_66_66_33 |
382 | #define PLLMR1_DEFAULT PLLMR1_133_66_66_33 | |
13fdf8a6 SR |
383 | #endif |
384 | ||
17e65c21 MF |
385 | /* |
386 | * PCI OHCI controller | |
387 | */ | |
388 | #define CONFIG_USB_OHCI_NEW 1 | |
389 | #define CONFIG_PCI_OHCI 1 | |
6d0f6bcf JCPV |
390 | #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 |
391 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 | |
392 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" | |
17e65c21 MF |
393 | #define CONFIG_USB_STORAGE 1 |
394 | ||
985edacc MF |
395 | /* |
396 | * UBI | |
397 | */ | |
398 | #define CONFIG_CMD_UBI | |
399 | #define CONFIG_RBTREE | |
400 | #define CONFIG_MTD_DEVICE | |
401 | #define CONFIG_MTD_PARTITIONS | |
402 | #define CONFIG_CMD_MTDPARTS | |
403 | #define CONFIG_LZO | |
404 | ||
13fdf8a6 | 405 | #endif /* __CONFIG_H */ |