[people/ms/u-boot.git] / include / configs / PM520.h

/*
 * (C) Copyright 2003-2005
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC5200
#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
#define CONFIG_PM520		1	/* ... on PM520 board */

#define	CONFIG_SYS_TEXT_BASE	0xfff00000

#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33MHz */

#define CONFIG_MISC_INIT_R

#define CONFIG_HIGH_BATS	1	/* High BATs supported */

/*
 * Serial console configuration
 */
#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
#define CONFIG_BAUDRATE		9600	/* ... at 9600 bps */
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }


/*
 * PCI Mapping:
 * 0x40000000 - 0x4fffffff - PCI Memory
 * 0x50000000 - 0x50ffffff - PCI IO Space
 */
#define CONFIG_PCI		1
#define CONFIG_PCI_PNP		1
#define CONFIG_PCI_SCAN_SHOW	1
#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1

#define CONFIG_PCI_MEM_BUS	0x40000000
#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE	0x10000000

#define CONFIG_PCI_IO_BUS	0x50000000
#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE	0x01000000

#define CONFIG_MII		1
#define CONFIG_EEPRO100		1
#define CONFIG_SYS_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
#undef  CONFIG_NS8382X


/* Partitions */
#define CONFIG_DOS_PARTITION

/* USB */
#if 1
#define CONFIG_USB_OHCI
#define CONFIG_USB_STORAGE
#endif

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_BEDBUG
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_FAT
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IDE
#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP
#define CONFIG_CMD_USB

#define CONFIG_CMD_PCI


/*
 * Autobooting
 */
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */

#define CONFIG_PREBOOT	"echo;"	\
	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"hostname=pm520\0"							\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"flash_nfs=run nfsargs addip;"					\
		"bootm ${kernel_addr}\0"				\
	"flash_self=run ramargs addip;"					\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
	"rootpath=/opt/eldk30/ppc_82xx\0"					\
	"bootfile=/tftpboot/PM520/uImage\0"				\
	""

#define CONFIG_BOOTCOMMAND	"run flash_self"

/*
 * IPB Bus clocking configuration.
 */
#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
/*
 * I2C configuration
 */
#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
#define CONFIG_SYS_I2C_MODULE		2	/* Select I2C module #1 or #2 */

#define CONFIG_SYS_I2C_SPEED		100000 /* 100 kHz */
#define CONFIG_SYS_I2C_SLAVE		0x7F

/*
 * EEPROM configuration
 */
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x58
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10

/*
 * RTC configuration
 */
#define CONFIG_RTC_PCF8563
#define CONFIG_SYS_I2C_RTC_ADDR		0x51

#define CONFIG_SYS_DOC_BASE		0xE0000000
#define CONFIG_SYS_DOC_SIZE		0x00100000

#if defined(CONFIG_BOOT_ROM)
/*
 * Flash configuration (8,16 or 32 MB)
 * TEXT base always at 0xFFF00000
 * ENV_ADDR always at  0xFFF40000
 * FLASH_BASE at 0xFA000000 for 64 MB
 *               0xFC000000 for 32 MB
 *               0xFD000000 for 16 MB
 *               0xFD800000 for  8 MB
 */
#define CONFIG_SYS_FLASH_BASE		0xFA000000
#define CONFIG_SYS_FLASH_SIZE		0x04000000
#define CONFIG_SYS_BOOTROM_BASE	0xFFF00000
#define CONFIG_SYS_BOOTROM_SIZE	0x00080000
#define CONFIG_ENV_ADDR		(0xFDF00000 + 0x40000)
#else
/*
 * Flash configuration (8,16 or 32 MB)
 * TEXT base always at 0xFFF00000
 * ENV_ADDR always at  0xFFF40000
 * FLASH_BASE at 0xFC000000 for 64 MB
 *               0xFE000000 for 32 MB
 *               0xFF000000 for 16 MB
 *               0xFF800000 for  8 MB
 */
#define CONFIG_SYS_FLASH_BASE		0xFC000000
#define CONFIG_SYS_FLASH_SIZE		0x04000000
#define CONFIG_ENV_ADDR		(0xFFF00000 + 0x40000)
#endif
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks      */

#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max num of sects on one chip */

#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
#define CONFIG_SYS_FLASH_LOCK_TOUT	5	/* Timeout for Flash Set Lock Bit (in ms) */
#define CONFIG_SYS_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */
#define CONFIG_SYS_FLASH_PROTECTION		/* "Real" (hardware) sectors protection */

#define PHYS_FLASH_SECT_SIZE	0x00040000 /* 256 KB sectors (x2) */

#undef CONFIG_FLASH_16BIT	/* Flash is 32-bit */


/*
 * Environment settings
 */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_SIZE		0x10000
#define CONFIG_ENV_SECT_SIZE	0x40000
#define CONFIG_ENV_OVERWRITE	1

/*
 * Memory map
 */
#define CONFIG_SYS_MBAR		0xf0000000
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_DEFAULT_MBAR	0x80000000

/* Use SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE	/* Size of used area in DPRAM */


#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#   define CONFIG_SYS_RAMBOOT		1
#endif

#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*
 * Ethernet configuration
 */
#define CONFIG_MPC5xxx_FEC	1
#define CONFIG_MPC5xxx_FEC_MII100
/*
 * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
 */
/* #define CONFIG_MPC5xxx_FEC_MII10 */
#define CONFIG_PHY_ADDR		0x00

/*
 * GPIO configuration
 */
#define CONFIG_SYS_GPS_PORT_CONFIG	0x10000004

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
#else
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/

#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */

#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
#if defined(CONFIG_CMD_KGDB)
#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif

/*
 * Various low-level settings
 */
#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL		HID0_ICE

#if defined(CONFIG_BOOT_ROM)
#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_BOOTROM_BASE
#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_BOOTROM_SIZE
#define CONFIG_SYS_BOOTCS_CFG		0x00047800
#define CONFIG_SYS_CS0_START		CONFIG_SYS_BOOTROM_BASE
#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_BOOTROM_SIZE
#define CONFIG_SYS_CS1_START		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CS1_SIZE		CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_CS1_CFG		0x0004FF00
#else
#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_BOOTCS_CFG		0x0004FF00
#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_CS1_START		CONFIG_SYS_DOC_BASE
#define CONFIG_SYS_CS1_SIZE		CONFIG_SYS_DOC_SIZE
#define CONFIG_SYS_CS1_CFG		0x00047800
#endif

#define CONFIG_SYS_CS_BURST		0x00000000
#define CONFIG_SYS_CS_DEADCYCLE	0x33333333

#define CONFIG_SYS_RESET_ADDRESS	0xff000000

/*-----------------------------------------------------------------------
 * USB stuff
 *-----------------------------------------------------------------------
 */
#define CONFIG_USB_CLOCK	0x0001BBBB
#define CONFIG_USB_CONFIG	0x00005000

/*-----------------------------------------------------------------------
 * IDE/ATA stuff Supports IDE harddisk
 *-----------------------------------------------------------------------
 */

#undef  CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/

#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/

#undef	CONFIG_IDE_RESET		/* reset for ide supported	*/
#define CONFIG_IDE_PREINIT

#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CONFIG_SYS_IDE_MAXDEVICE	2	/* max. 2 drive per IDE bus	*/

#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000

#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA

/* Offset for data I/O			*/
#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)

/* Offset for normal register accesses	*/
#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)

/* Offset for alternate registers	*/
#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)

/* Interval between registers                                                */
#define CONFIG_SYS_ATA_STRIDE          4

#endif /* __CONFIG_H */
Commit	Line	Data
efa329cb	1	/*
414eec35	2	* (C) Copyright 2003-2005
efa329cb WD	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
efa329cb WD	4	*
3765b3e7	5	* SPDX-License-Identifier: GPL-2.0+
efa329cb WD	6	*/
	7
	8	#ifndef __CONFIG_H
	9	#define __CONFIG_H
	10
	11	/*
	12	* High Level Configuration Options
	13	* (easy to change)
	14	*/
	15
	16	#define CONFIG_MPC5200
62b4ac98	17	#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
efa329cb WD	18	#define CONFIG_PM520 1 /* ... on PM520 board */
efa329cb WD	19
2ae18241 WD	20	#define CONFIG_SYS_TEXT_BASE 0xfff00000
2ae18241 WD	21
6d0f6bcf	22	#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */
efa329cb	23
49822e23 WD	24	#define CONFIG_MISC_INIT_R
49822e23 WD	25
31d82672 BB	26	#define CONFIG_HIGH_BATS 1 /* High BATs supported */
31d82672 BB	27
efa329cb WD	28	/*
	29	* Serial console configuration
	30	*/
	31	#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
	32	#define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */
6d0f6bcf	33	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
efa329cb WD	34
efa329cb WD	35
efa329cb WD	36	/*
	37	* PCI Mapping:
	38	* 0x40000000 - 0x4fffffff - PCI Memory
	39	* 0x50000000 - 0x50ffffff - PCI IO Space
	40	*/
	41	#define CONFIG_PCI 1
	42	#define CONFIG_PCI_PNP 1
	43	#define CONFIG_PCI_SCAN_SHOW 1
f33fca22	44	#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
efa329cb WD	45
	46	#define CONFIG_PCI_MEM_BUS 0x40000000
	47	#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
	48	#define CONFIG_PCI_MEM_SIZE 0x10000000
	49
	50	#define CONFIG_PCI_IO_BUS 0x50000000
	51	#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
	52	#define CONFIG_PCI_IO_SIZE 0x01000000
	53
63ff004c	54	#define CONFIG_MII 1
efa329cb	55	#define CONFIG_EEPRO100 1
6d0f6bcf	56	#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
efa329cb WD	57	#undef CONFIG_NS8382X
efa329cb WD	58
efa329cb	59
49822e23 WD	60	/* Partitions */
	61	#define CONFIG_DOS_PARTITION
	62
	63	/* USB */
	64	#if 1
	65	#define CONFIG_USB_OHCI
49822e23	66	#define CONFIG_USB_STORAGE
49822e23 WD	67	#endif
49822e23 WD	68
a1aa0bb5 JL	69	/*
	70	* BOOTP options
	71	*/
	72	#define CONFIG_BOOTP_BOOTFILESIZE
	73	#define CONFIG_BOOTP_BOOTPATH
	74	#define CONFIG_BOOTP_GATEWAY
	75	#define CONFIG_BOOTP_HOSTNAME
	76
	77
efa329cb	78	/*
acf02697	79	* Command line configuration.
efa329cb	80	*/
acf02697 JL	81	#include <config_cmd_default.h>
	82
	83	#define CONFIG_CMD_BEDBUG
	84	#define CONFIG_CMD_DATE
	85	#define CONFIG_CMD_DHCP
	86	#define CONFIG_CMD_EEPROM
	87	#define CONFIG_CMD_FAT
	88	#define CONFIG_CMD_I2C
	89	#define CONFIG_CMD_IDE
	90	#define CONFIG_CMD_NFS
	91	#define CONFIG_CMD_SNTP
	92	#define CONFIG_CMD_USB
	93
acf02697	94	#define CONFIG_CMD_PCI
acf02697	95
efa329cb WD	96
	97	/*
	98	* Autobooting
	99	*/
	100	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
49822e23 WD	101
49822e23 WD	102	#define CONFIG_PREBOOT "echo;" \
32bf3d14	103	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
49822e23 WD	104	"echo"
	105
	106	#undef CONFIG_BOOTARGS
	107
	108	#define CONFIG_EXTRA_ENV_SETTINGS \
	109	"netdev=eth0\0" \
	110	"hostname=pm520\0" \
	111	"nfsargs=setenv bootargs root=/dev/nfs rw " \
fe126d8b	112	"nfsroot=${serverip}:${rootpath}\0" \
49822e23	113	"ramargs=setenv bootargs root=/dev/ram rw\0" \
fe126d8b WD	114	"addip=setenv bootargs ${bootargs} " \
	115	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	116	":${hostname}:${netdev}:off panic=1\0" \
49822e23	117	"flash_nfs=run nfsargs addip;" \
fe126d8b	118	"bootm ${kernel_addr}\0" \
49822e23	119	"flash_self=run ramargs addip;" \
fe126d8b WD	120	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
fe126d8b WD	121	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
49822e23 WD	122	"rootpath=/opt/eldk30/ppc_82xx\0" \
	123	"bootfile=/tftpboot/PM520/uImage\0" \
	124	""
	125
	126	#define CONFIG_BOOTCOMMAND "run flash_self"
efa329cb	127
efa329cb WD	128	/*
	129	* IPB Bus clocking configuration.
	130	*/
6d0f6bcf	131	#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
efa329cb WD	132	/*
	133	* I2C configuration
	134	*/
	135	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
6d0f6bcf	136	#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
efa329cb	137
6d0f6bcf JCPV	138	#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
6d0f6bcf JCPV	139	#define CONFIG_SYS_I2C_SLAVE 0x7F
efa329cb WD	140
	141	/*
	142	* EEPROM configuration
	143	*/
6d0f6bcf JCPV	144	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58
	145	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	146	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
	147	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
efa329cb WD	148
	149	/*
	150	* RTC configuration
	151	*/
	152	#define CONFIG_RTC_PCF8563
6d0f6bcf	153	#define CONFIG_SYS_I2C_RTC_ADDR 0x51
efa329cb	154
6d0f6bcf JCPV	155	#define CONFIG_SYS_DOC_BASE 0xE0000000
6d0f6bcf JCPV	156	#define CONFIG_SYS_DOC_SIZE 0x00100000
49822e23 WD	157
	158	#if defined(CONFIG_BOOT_ROM)
	159	/*
	160	* Flash configuration (8,16 or 32 MB)
	161	* TEXT base always at 0xFFF00000
	162	* ENV_ADDR always at 0xFFF40000
c7428d49 WD	163	* FLASH_BASE at 0xFA000000 for 64 MB
c7428d49 WD	164	* 0xFC000000 for 32 MB
49822e23 WD	165	* 0xFD000000 for 16 MB
	166	* 0xFD800000 for 8 MB
	167	*/
6d0f6bcf JCPV	168	#define CONFIG_SYS_FLASH_BASE 0xFA000000
	169	#define CONFIG_SYS_FLASH_SIZE 0x04000000
	170	#define CONFIG_SYS_BOOTROM_BASE 0xFFF00000
	171	#define CONFIG_SYS_BOOTROM_SIZE 0x00080000
0e8d1586	172	#define CONFIG_ENV_ADDR (0xFDF00000 + 0x40000)
49822e23 WD	173	#else
	174	/*
	175	* Flash configuration (8,16 or 32 MB)
	176	* TEXT base always at 0xFFF00000
	177	* ENV_ADDR always at 0xFFF40000
c7428d49 WD	178	* FLASH_BASE at 0xFC000000 for 64 MB
c7428d49 WD	179	* 0xFE000000 for 32 MB
49822e23 WD	180	* 0xFF000000 for 16 MB
49822e23 WD	181	* 0xFF800000 for 8 MB
efa329cb	182	*/
6d0f6bcf JCPV	183	#define CONFIG_SYS_FLASH_BASE 0xFC000000
6d0f6bcf JCPV	184	#define CONFIG_SYS_FLASH_SIZE 0x04000000
0e8d1586	185	#define CONFIG_ENV_ADDR (0xFFF00000 + 0x40000)
49822e23	186	#endif
6d0f6bcf	187	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
efa329cb	188
6d0f6bcf	189	#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
efa329cb	190
6d0f6bcf JCPV	191	#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
	192	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
	193	#define CONFIG_SYS_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
	194	#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
	195	#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
efa329cb WD	196
	197	#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
	198
	199	#undef CONFIG_FLASH_16BIT /* Flash is 32-bit */
	200
	201
	202	/*
	203	* Environment settings
	204	*/
5a1aceb0	205	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	206	#define CONFIG_ENV_SIZE 0x10000
0e8d1586 JCPV	207	#define CONFIG_ENV_SECT_SIZE 0x40000
efa329cb WD	208	#define CONFIG_ENV_OVERWRITE 1
	209
	210	/*
	211	* Memory map
	212	*/
6d0f6bcf JCPV	213	#define CONFIG_SYS_MBAR 0xf0000000
	214	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	215	#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
efa329cb WD	216
efa329cb WD	217	/* Use SRAM until RAM will be available */
6d0f6bcf	218	#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
553f0982	219	#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
efa329cb WD	220
efa329cb WD	221
25ddd1fb	222	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	223	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
efa329cb	224
14d0a02a	225	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
6d0f6bcf JCPV	226	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
6d0f6bcf JCPV	227	# define CONFIG_SYS_RAMBOOT 1
efa329cb WD	228	#endif
efa329cb WD	229
6d0f6bcf JCPV	230	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	231	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
	232	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
efa329cb WD	233
	234	/*
	235	* Ethernet configuration
	236	*/
62b4ac98	237	#define CONFIG_MPC5xxx_FEC 1
86321fc1	238	#define CONFIG_MPC5xxx_FEC_MII100
62b4ac98	239	/*
86321fc1	240	* Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
62b4ac98	241	*/
86321fc1	242	/* #define CONFIG_MPC5xxx_FEC_MII10 */
efa329cb WD	243	#define CONFIG_PHY_ADDR 0x00
	244
	245	/*
	246	* GPIO configuration
	247	*/
6d0f6bcf	248	#define CONFIG_SYS_GPS_PORT_CONFIG 0x10000004
efa329cb WD	249
	250	/*
	251	* Miscellaneous configurable options
	252	*/
6d0f6bcf	253	#define CONFIG_SYS_LONGHELP /* undef to save memory */
acf02697	254	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	255	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
efa329cb	256	#else
6d0f6bcf	257	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
efa329cb	258	#endif
6d0f6bcf JCPV	259	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	260	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	261	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
efa329cb	262
6d0f6bcf JCPV	263	#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
6d0f6bcf JCPV	264	#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
efa329cb	265
6d0f6bcf	266	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
efa329cb	267
6d0f6bcf	268	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
acf02697	269	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	270	# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
acf02697 JL	271	#endif
acf02697 JL	272
efa329cb WD	273	/*
	274	* Various low-level settings
	275	*/
6d0f6bcf JCPV	276	#define CONFIG_SYS_HID0_INIT HID0_ICE \| HID0_ICFI
6d0f6bcf JCPV	277	#define CONFIG_SYS_HID0_FINAL HID0_ICE
efa329cb	278
49822e23	279	#if defined(CONFIG_BOOT_ROM)
6d0f6bcf JCPV	280	#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_BOOTROM_BASE
	281	#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_BOOTROM_SIZE
	282	#define CONFIG_SYS_BOOTCS_CFG 0x00047800
	283	#define CONFIG_SYS_CS0_START CONFIG_SYS_BOOTROM_BASE
	284	#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_BOOTROM_SIZE
	285	#define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE
	286	#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_FLASH_SIZE
	287	#define CONFIG_SYS_CS1_CFG 0x0004FF00
49822e23	288	#else
6d0f6bcf JCPV	289	#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
	290	#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
	291	#define CONFIG_SYS_BOOTCS_CFG 0x0004FF00
	292	#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
	293	#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
	294	#define CONFIG_SYS_CS1_START CONFIG_SYS_DOC_BASE
	295	#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_DOC_SIZE
	296	#define CONFIG_SYS_CS1_CFG 0x00047800
49822e23	297	#endif
efa329cb	298
6d0f6bcf JCPV	299	#define CONFIG_SYS_CS_BURST 0x00000000
6d0f6bcf JCPV	300	#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
efa329cb	301
6d0f6bcf	302	#define CONFIG_SYS_RESET_ADDRESS 0xff000000
efa329cb	303
49822e23 WD	304	/*-----------------------------------------------------------------------
	305	* USB stuff
	306	*-----------------------------------------------------------------------
	307	*/
	308	#define CONFIG_USB_CLOCK 0x0001BBBB
	309	#define CONFIG_USB_CONFIG 0x00005000
	310
	311	/*-----------------------------------------------------------------------
	312	* IDE/ATA stuff Supports IDE harddisk
	313	*-----------------------------------------------------------------------
	314	*/
	315
	316	#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
	317
	318	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
	319	#undef CONFIG_IDE_LED /* LED for ide not supported */
	320
	321	#undef CONFIG_IDE_RESET /* reset for ide supported */
	322	#define CONFIG_IDE_PREINIT
	323
6d0f6bcf JCPV	324	#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
6d0f6bcf JCPV	325	#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drive per IDE bus */
49822e23	326
6d0f6bcf	327	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
49822e23	328
6d0f6bcf	329	#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
49822e23 WD	330
49822e23 WD	331	/* Offset for data I/O */
6d0f6bcf	332	#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
49822e23 WD	333
49822e23 WD	334	/* Offset for normal register accesses */
6d0f6bcf	335	#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
49822e23 WD	336
49822e23 WD	337	/* Offset for alternate registers */
6d0f6bcf	338	#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
49822e23 WD	339
49822e23 WD	340	/* Interval between registers */
6d0f6bcf	341	#define CONFIG_SYS_ATA_STRIDE 4
49822e23	342
efa329cb	343	#endif /* __CONFIG_H */