[people/ms/u-boot.git] / include / configs / PM520.h

/*
 * (C) Copyright 2003-2005
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC5200
#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
#define CONFIG_PM520		1	/* ... on PM520 board */

#define	CONFIG_SYS_TEXT_BASE	0xfff00000

#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33MHz */

#define CONFIG_MISC_INIT_R

#define CONFIG_HIGH_BATS	1	/* High BATs supported */

/*
 * Serial console configuration
 */
#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
#define CONFIG_BAUDRATE		9600	/* ... at 9600 bps */
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }


/*
 * PCI Mapping:
 * 0x40000000 - 0x4fffffff - PCI Memory
 * 0x50000000 - 0x50ffffff - PCI IO Space
 */
#define CONFIG_PCI		1
#define CONFIG_PCI_PNP		1
#define CONFIG_PCI_SCAN_SHOW	1
#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1

#define CONFIG_PCI_MEM_BUS	0x40000000
#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE	0x10000000

#define CONFIG_PCI_IO_BUS	0x50000000
#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE	0x01000000

#define CONFIG_NET_MULTI	1
#define CONFIG_MII		1
#define CONFIG_EEPRO100		1
#define CONFIG_SYS_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
#undef  CONFIG_NS8382X


/* Partitions */
#define CONFIG_DOS_PARTITION

/* USB */
#if 1
#define CONFIG_USB_OHCI
#define CONFIG_USB_STORAGE
#endif

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_BEDBUG
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_FAT
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IDE
#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP
#define CONFIG_CMD_USB

#define CONFIG_CMD_PCI


/*
 * Autobooting
 */
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */

#define CONFIG_PREBOOT	"echo;"	\
	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"hostname=pm520\0"							\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"flash_nfs=run nfsargs addip;"					\
		"bootm ${kernel_addr}\0"				\
	"flash_self=run ramargs addip;"					\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
	"rootpath=/opt/eldk30/ppc_82xx\0"					\
	"bootfile=/tftpboot/PM520/uImage\0"				\
	""

#define CONFIG_BOOTCOMMAND	"run flash_self"

/*
 * IPB Bus clocking configuration.
 */
#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
/*
 * I2C configuration
 */
#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
#define CONFIG_SYS_I2C_MODULE		2	/* Select I2C module #1 or #2 */

#define CONFIG_SYS_I2C_SPEED		100000 /* 100 kHz */
#define CONFIG_SYS_I2C_SLAVE		0x7F

/*
 * EEPROM configuration
 */
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x58
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10

/*
 * RTC configuration
 */
#define CONFIG_RTC_PCF8563
#define CONFIG_SYS_I2C_RTC_ADDR		0x51

#define CONFIG_SYS_DOC_BASE		0xE0000000
#define CONFIG_SYS_DOC_SIZE		0x00100000

#if defined(CONFIG_BOOT_ROM)
/*
 * Flash configuration (8,16 or 32 MB)
 * TEXT base always at 0xFFF00000
 * ENV_ADDR always at  0xFFF40000
 * FLASH_BASE at 0xFA000000 for 64 MB
 *               0xFC000000 for 32 MB
 *               0xFD000000 for 16 MB
 *               0xFD800000 for  8 MB
 */
#define CONFIG_SYS_FLASH_BASE		0xFA000000
#define CONFIG_SYS_FLASH_SIZE		0x04000000
#define CONFIG_SYS_BOOTROM_BASE	0xFFF00000
#define CONFIG_SYS_BOOTROM_SIZE	0x00080000
#define CONFIG_ENV_ADDR		(0xFDF00000 + 0x40000)
#else
/*
 * Flash configuration (8,16 or 32 MB)
 * TEXT base always at 0xFFF00000
 * ENV_ADDR always at  0xFFF40000
 * FLASH_BASE at 0xFC000000 for 64 MB
 *               0xFE000000 for 32 MB
 *               0xFF000000 for 16 MB
 *               0xFF800000 for  8 MB
 */
#define CONFIG_SYS_FLASH_BASE		0xFC000000
#define CONFIG_SYS_FLASH_SIZE		0x04000000
#define CONFIG_ENV_ADDR		(0xFFF00000 + 0x40000)
#endif
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks      */

#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max num of sects on one chip */

#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
#define CONFIG_SYS_FLASH_LOCK_TOUT	5	/* Timeout for Flash Set Lock Bit (in ms) */
#define CONFIG_SYS_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */
#define CONFIG_SYS_FLASH_PROTECTION		/* "Real" (hardware) sectors protection */

#define PHYS_FLASH_SECT_SIZE	0x00040000 /* 256 KB sectors (x2) */

#undef CONFIG_FLASH_16BIT	/* Flash is 32-bit */


/*
 * Environment settings
 */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_SIZE		0x10000
#define CONFIG_ENV_SECT_SIZE	0x40000
#define CONFIG_ENV_OVERWRITE	1

/*
 * Memory map
 */
#define CONFIG_SYS_MBAR		0xf0000000
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_DEFAULT_MBAR	0x80000000

/* Use SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE	/* Size of used area in DPRAM */


#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#   define CONFIG_SYS_RAMBOOT		1
#endif

#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*
 * Ethernet configuration
 */
#define CONFIG_MPC5xxx_FEC	1
#define CONFIG_MPC5xxx_FEC_MII100
/*
 * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
 */
/* #define CONFIG_MPC5xxx_FEC_MII10 */
#define CONFIG_PHY_ADDR		0x00

/*
 * GPIO configuration
 */
#define CONFIG_SYS_GPS_PORT_CONFIG	0x10000004

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
#else
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/

#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */

#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */

#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
#if defined(CONFIG_CMD_KGDB)
#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif

/*
 * Various low-level settings
 */
#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL		HID0_ICE

#if defined(CONFIG_BOOT_ROM)
#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_BOOTROM_BASE
#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_BOOTROM_SIZE
#define CONFIG_SYS_BOOTCS_CFG		0x00047800
#define CONFIG_SYS_CS0_START		CONFIG_SYS_BOOTROM_BASE
#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_BOOTROM_SIZE
#define CONFIG_SYS_CS1_START		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CS1_SIZE		CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_CS1_CFG		0x0004FF00
#else
#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_BOOTCS_CFG		0x0004FF00
#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_CS1_START		CONFIG_SYS_DOC_BASE
#define CONFIG_SYS_CS1_SIZE		CONFIG_SYS_DOC_SIZE
#define CONFIG_SYS_CS1_CFG		0x00047800
#endif

#define CONFIG_SYS_CS_BURST		0x00000000
#define CONFIG_SYS_CS_DEADCYCLE	0x33333333

#define CONFIG_SYS_RESET_ADDRESS	0xff000000

/*-----------------------------------------------------------------------
 * USB stuff
 *-----------------------------------------------------------------------
 */
#define CONFIG_USB_CLOCK	0x0001BBBB
#define CONFIG_USB_CONFIG	0x00005000

/*-----------------------------------------------------------------------
 * IDE/ATA stuff Supports IDE harddisk
 *-----------------------------------------------------------------------
 */

#undef  CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/

#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/

#undef	CONFIG_IDE_RESET		/* reset for ide supported	*/
#define CONFIG_IDE_PREINIT

#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CONFIG_SYS_IDE_MAXDEVICE	2	/* max. 2 drive per IDE bus	*/

#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000

#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA

/* Offset for data I/O			*/
#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)

/* Offset for normal register accesses	*/
#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)

/* Offset for alternate registers	*/
#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)

/* Interval between registers                                                */
#define CONFIG_SYS_ATA_STRIDE          4

#endif /* __CONFIG_H */
Commit	Line	Data
efa329cb	1	/*
414eec35	2	* (C) Copyright 2003-2005
efa329cb WD	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#ifndef __CONFIG_H
	25	#define __CONFIG_H
	26
	27	/*
	28	* High Level Configuration Options
	29	* (easy to change)
	30	*/
	31
	32	#define CONFIG_MPC5200
62b4ac98	33	#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
efa329cb WD	34	#define CONFIG_PM520 1 /* ... on PM520 board */
efa329cb WD	35
2ae18241 WD	36	#define CONFIG_SYS_TEXT_BASE 0xfff00000
2ae18241 WD	37
6d0f6bcf	38	#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */
efa329cb	39
49822e23 WD	40	#define CONFIG_MISC_INIT_R
49822e23 WD	41
31d82672 BB	42	#define CONFIG_HIGH_BATS 1 /* High BATs supported */
31d82672 BB	43
efa329cb WD	44	/*
	45	* Serial console configuration
	46	*/
	47	#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
	48	#define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */
6d0f6bcf	49	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
efa329cb WD	50
efa329cb WD	51
efa329cb WD	52	/*
	53	* PCI Mapping:
	54	* 0x40000000 - 0x4fffffff - PCI Memory
	55	* 0x50000000 - 0x50ffffff - PCI IO Space
	56	*/
	57	#define CONFIG_PCI 1
	58	#define CONFIG_PCI_PNP 1
	59	#define CONFIG_PCI_SCAN_SHOW 1
f33fca22	60	#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
efa329cb WD	61
	62	#define CONFIG_PCI_MEM_BUS 0x40000000
	63	#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
	64	#define CONFIG_PCI_MEM_SIZE 0x10000000
	65
	66	#define CONFIG_PCI_IO_BUS 0x50000000
	67	#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
	68	#define CONFIG_PCI_IO_SIZE 0x01000000
	69
	70	#define CONFIG_NET_MULTI 1
63ff004c	71	#define CONFIG_MII 1
efa329cb	72	#define CONFIG_EEPRO100 1
6d0f6bcf	73	#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
efa329cb WD	74	#undef CONFIG_NS8382X
efa329cb WD	75
efa329cb	76
49822e23 WD	77	/* Partitions */
	78	#define CONFIG_DOS_PARTITION
	79
	80	/* USB */
	81	#if 1
	82	#define CONFIG_USB_OHCI
49822e23	83	#define CONFIG_USB_STORAGE
49822e23 WD	84	#endif
49822e23 WD	85
a1aa0bb5 JL	86	/*
	87	* BOOTP options
	88	*/
	89	#define CONFIG_BOOTP_BOOTFILESIZE
	90	#define CONFIG_BOOTP_BOOTPATH
	91	#define CONFIG_BOOTP_GATEWAY
	92	#define CONFIG_BOOTP_HOSTNAME
	93
	94
efa329cb	95	/*
acf02697	96	* Command line configuration.
efa329cb	97	*/
acf02697 JL	98	#include <config_cmd_default.h>
	99
	100	#define CONFIG_CMD_BEDBUG
	101	#define CONFIG_CMD_DATE
	102	#define CONFIG_CMD_DHCP
	103	#define CONFIG_CMD_EEPROM
	104	#define CONFIG_CMD_FAT
	105	#define CONFIG_CMD_I2C
	106	#define CONFIG_CMD_IDE
	107	#define CONFIG_CMD_NFS
	108	#define CONFIG_CMD_SNTP
	109	#define CONFIG_CMD_USB
	110
acf02697	111	#define CONFIG_CMD_PCI
acf02697	112
efa329cb WD	113
	114	/*
	115	* Autobooting
	116	*/
	117	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
49822e23 WD	118
49822e23 WD	119	#define CONFIG_PREBOOT "echo;" \
32bf3d14	120	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
49822e23 WD	121	"echo"
	122
	123	#undef CONFIG_BOOTARGS
	124
	125	#define CONFIG_EXTRA_ENV_SETTINGS \
	126	"netdev=eth0\0" \
	127	"hostname=pm520\0" \
	128	"nfsargs=setenv bootargs root=/dev/nfs rw " \
fe126d8b	129	"nfsroot=${serverip}:${rootpath}\0" \
49822e23	130	"ramargs=setenv bootargs root=/dev/ram rw\0" \
fe126d8b WD	131	"addip=setenv bootargs ${bootargs} " \
	132	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	133	":${hostname}:${netdev}:off panic=1\0" \
49822e23	134	"flash_nfs=run nfsargs addip;" \
fe126d8b	135	"bootm ${kernel_addr}\0" \
49822e23	136	"flash_self=run ramargs addip;" \
fe126d8b WD	137	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
fe126d8b WD	138	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
49822e23 WD	139	"rootpath=/opt/eldk30/ppc_82xx\0" \
	140	"bootfile=/tftpboot/PM520/uImage\0" \
	141	""
	142
	143	#define CONFIG_BOOTCOMMAND "run flash_self"
efa329cb	144
efa329cb WD	145	/*
	146	* IPB Bus clocking configuration.
	147	*/
6d0f6bcf	148	#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
efa329cb WD	149	/*
	150	* I2C configuration
	151	*/
	152	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
6d0f6bcf	153	#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
efa329cb	154
6d0f6bcf JCPV	155	#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
6d0f6bcf JCPV	156	#define CONFIG_SYS_I2C_SLAVE 0x7F
efa329cb WD	157
	158	/*
	159	* EEPROM configuration
	160	*/
6d0f6bcf JCPV	161	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58
	162	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	163	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
	164	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
efa329cb WD	165
	166	/*
	167	* RTC configuration
	168	*/
	169	#define CONFIG_RTC_PCF8563
6d0f6bcf	170	#define CONFIG_SYS_I2C_RTC_ADDR 0x51
efa329cb	171
6d0f6bcf JCPV	172	#define CONFIG_SYS_DOC_BASE 0xE0000000
6d0f6bcf JCPV	173	#define CONFIG_SYS_DOC_SIZE 0x00100000
49822e23 WD	174
	175	#if defined(CONFIG_BOOT_ROM)
	176	/*
	177	* Flash configuration (8,16 or 32 MB)
	178	* TEXT base always at 0xFFF00000
	179	* ENV_ADDR always at 0xFFF40000
c7428d49 WD	180	* FLASH_BASE at 0xFA000000 for 64 MB
c7428d49 WD	181	* 0xFC000000 for 32 MB
49822e23 WD	182	* 0xFD000000 for 16 MB
	183	* 0xFD800000 for 8 MB
	184	*/
6d0f6bcf JCPV	185	#define CONFIG_SYS_FLASH_BASE 0xFA000000
	186	#define CONFIG_SYS_FLASH_SIZE 0x04000000
	187	#define CONFIG_SYS_BOOTROM_BASE 0xFFF00000
	188	#define CONFIG_SYS_BOOTROM_SIZE 0x00080000
0e8d1586	189	#define CONFIG_ENV_ADDR (0xFDF00000 + 0x40000)
49822e23 WD	190	#else
	191	/*
	192	* Flash configuration (8,16 or 32 MB)
	193	* TEXT base always at 0xFFF00000
	194	* ENV_ADDR always at 0xFFF40000
c7428d49 WD	195	* FLASH_BASE at 0xFC000000 for 64 MB
c7428d49 WD	196	* 0xFE000000 for 32 MB
49822e23 WD	197	* 0xFF000000 for 16 MB
49822e23 WD	198	* 0xFF800000 for 8 MB
efa329cb	199	*/
6d0f6bcf JCPV	200	#define CONFIG_SYS_FLASH_BASE 0xFC000000
6d0f6bcf JCPV	201	#define CONFIG_SYS_FLASH_SIZE 0x04000000
0e8d1586	202	#define CONFIG_ENV_ADDR (0xFFF00000 + 0x40000)
49822e23	203	#endif
6d0f6bcf	204	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
efa329cb	205
6d0f6bcf	206	#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
efa329cb	207
6d0f6bcf JCPV	208	#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
	209	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
	210	#define CONFIG_SYS_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
	211	#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
	212	#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
efa329cb WD	213
	214	#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
	215
	216	#undef CONFIG_FLASH_16BIT /* Flash is 32-bit */
	217
	218
	219	/*
	220	* Environment settings
	221	*/
5a1aceb0	222	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	223	#define CONFIG_ENV_SIZE 0x10000
0e8d1586 JCPV	224	#define CONFIG_ENV_SECT_SIZE 0x40000
efa329cb WD	225	#define CONFIG_ENV_OVERWRITE 1
	226
	227	/*
	228	* Memory map
	229	*/
6d0f6bcf JCPV	230	#define CONFIG_SYS_MBAR 0xf0000000
	231	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	232	#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
efa329cb WD	233
efa329cb WD	234	/* Use SRAM until RAM will be available */
6d0f6bcf	235	#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
553f0982	236	#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
efa329cb WD	237
efa329cb WD	238
25ddd1fb	239	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	240	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
efa329cb	241
14d0a02a	242	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
6d0f6bcf JCPV	243	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
6d0f6bcf JCPV	244	# define CONFIG_SYS_RAMBOOT 1
efa329cb WD	245	#endif
efa329cb WD	246
6d0f6bcf JCPV	247	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	248	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
	249	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
efa329cb WD	250
	251	/*
	252	* Ethernet configuration
	253	*/
62b4ac98	254	#define CONFIG_MPC5xxx_FEC 1
86321fc1	255	#define CONFIG_MPC5xxx_FEC_MII100
62b4ac98	256	/*
86321fc1	257	* Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
62b4ac98	258	*/
86321fc1	259	/* #define CONFIG_MPC5xxx_FEC_MII10 */
efa329cb WD	260	#define CONFIG_PHY_ADDR 0x00
	261
	262	/*
	263	* GPIO configuration
	264	*/
6d0f6bcf	265	#define CONFIG_SYS_GPS_PORT_CONFIG 0x10000004
efa329cb WD	266
	267	/*
	268	* Miscellaneous configurable options
	269	*/
6d0f6bcf JCPV	270	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	271	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
acf02697	272	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	273	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
efa329cb	274	#else
6d0f6bcf	275	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
efa329cb	276	#endif
6d0f6bcf JCPV	277	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	278	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	279	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
efa329cb	280
6d0f6bcf JCPV	281	#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
6d0f6bcf JCPV	282	#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
efa329cb	283
6d0f6bcf	284	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
efa329cb	285
6d0f6bcf	286	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
efa329cb	287
6d0f6bcf	288	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
acf02697	289	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	290	# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
acf02697 JL	291	#endif
acf02697 JL	292
efa329cb WD	293	/*
	294	* Various low-level settings
	295	*/
6d0f6bcf JCPV	296	#define CONFIG_SYS_HID0_INIT HID0_ICE \| HID0_ICFI
6d0f6bcf JCPV	297	#define CONFIG_SYS_HID0_FINAL HID0_ICE
efa329cb	298
49822e23	299	#if defined(CONFIG_BOOT_ROM)
6d0f6bcf JCPV	300	#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_BOOTROM_BASE
	301	#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_BOOTROM_SIZE
	302	#define CONFIG_SYS_BOOTCS_CFG 0x00047800
	303	#define CONFIG_SYS_CS0_START CONFIG_SYS_BOOTROM_BASE
	304	#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_BOOTROM_SIZE
	305	#define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE
	306	#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_FLASH_SIZE
	307	#define CONFIG_SYS_CS1_CFG 0x0004FF00
49822e23	308	#else
6d0f6bcf JCPV	309	#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
	310	#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
	311	#define CONFIG_SYS_BOOTCS_CFG 0x0004FF00
	312	#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
	313	#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
	314	#define CONFIG_SYS_CS1_START CONFIG_SYS_DOC_BASE
	315	#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_DOC_SIZE
	316	#define CONFIG_SYS_CS1_CFG 0x00047800
49822e23	317	#endif
efa329cb	318
6d0f6bcf JCPV	319	#define CONFIG_SYS_CS_BURST 0x00000000
6d0f6bcf JCPV	320	#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
efa329cb	321
6d0f6bcf	322	#define CONFIG_SYS_RESET_ADDRESS 0xff000000
efa329cb	323
49822e23 WD	324	/*-----------------------------------------------------------------------
	325	* USB stuff
	326	*-----------------------------------------------------------------------
	327	*/
	328	#define CONFIG_USB_CLOCK 0x0001BBBB
	329	#define CONFIG_USB_CONFIG 0x00005000
	330
	331	/*-----------------------------------------------------------------------
	332	* IDE/ATA stuff Supports IDE harddisk
	333	*-----------------------------------------------------------------------
	334	*/
	335
	336	#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
	337
	338	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
	339	#undef CONFIG_IDE_LED /* LED for ide not supported */
	340
	341	#undef CONFIG_IDE_RESET /* reset for ide supported */
	342	#define CONFIG_IDE_PREINIT
	343
6d0f6bcf JCPV	344	#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
6d0f6bcf JCPV	345	#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drive per IDE bus */
49822e23	346
6d0f6bcf	347	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
49822e23	348
6d0f6bcf	349	#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
49822e23 WD	350
49822e23 WD	351	/* Offset for data I/O */
6d0f6bcf	352	#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
49822e23 WD	353
49822e23 WD	354	/* Offset for normal register accesses */
6d0f6bcf	355	#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
49822e23 WD	356
49822e23 WD	357	/* Offset for alternate registers */
6d0f6bcf	358	#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
49822e23 WD	359
49822e23 WD	360	/* Interval between registers */
6d0f6bcf	361	#define CONFIG_SYS_ATA_STRIDE 4
49822e23	362
efa329cb	363	#endif /* __CONFIG_H */