[people/ms/u-boot.git] / include / configs / PM826.h

/*
 * (C) Copyright 2001-2005
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#undef CONFIG_SYS_RAMBOOT

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_PM826		1	/* ...on a PM8260 module	*/
#define CONFIG_CPM2		1	/* Has a CPM2 */

#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE	0xFF000000	/* Standard: boot 64-bit flash */
#endif

#undef CONFIG_DB_CR826_J30x_ON		/* J30x jumpers on D.B. carrier	*/

#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/

#define CONFIG_PREBOOT	"echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"

#undef	CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND							\
	"bootp; "								\
	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
	"bootm"

/* enable I2C and select the hardware/software driver */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
#define CONFIG_SYS_I2C_SOFT_SPEED	50000
#define CONFIG_SYS_I2C_SOFT_SLAVE	0xFE
/*
 * Software (bit-bang) I2C driver configuration
 */
#define I2C_PORT	3		/* Port A=0, B=1, C=2, D=3 */
#define I2C_ACTIVE	(iop->pdir |=  0x00010000)
#define I2C_TRISTATE	(iop->pdir &= ~0x00010000)
#define I2C_READ	((iop->pdat & 0x00010000) != 0)
#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00010000; \
			else    iop->pdat &= ~0x00010000
#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00020000; \
			else    iop->pdat &= ~0x00020000
#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */


#define CONFIG_RTC_PCF8563
#define CONFIG_SYS_I2C_RTC_ADDR	0x51

/*
 * select serial console configuration
 *
 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
 * for SCC).
 *
 * if CONFIG_CONS_NONE is defined, then the serial console routines must
 * defined elsewhere (for example, on the cogent platform, there are serial
 * ports on the motherboard which are used for the serial console - see
 * cogent/cma101/serial.[ch]).
 */
#define CONFIG_CONS_ON_SMC		/* define if console on SMC */
#undef  CONFIG_CONS_ON_SCC		/* define if console on SCC */
#undef  CONFIG_CONS_NONE		/* define if console on something else*/
#define CONFIG_CONS_INDEX	2	/* which serial channel for console */

/*
 * select ethernet configuration
 *
 * if CONFIG_ETHER_ON_SCC is selected, then
 *   - CONFIG_ETHER_INDEX must be set to the channel number (1-4)
 *
 * if CONFIG_ETHER_ON_FCC is selected, then
 *   - one or more CONFIG_ETHER_ON_FCCx (x=1,2,3) must also be selected
 *
 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
 */
#undef	CONFIG_ETHER_NONE		/* define if ether on something else */

#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC       */
#define	CONFIG_ETHER_INDEX    1		/* which SCC channel for ethernet */

#define	CONFIG_ETHER_ON_FCC		/* define if ether on FCC       */
/*
 * - Rx-CLK is CLK11
 * - Tx-CLK is CLK10
 */
#define	CONFIG_ETHER_ON_FCC1
# define CONFIG_SYS_CMXFCR_MASK1	(CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
#ifndef CONFIG_DB_CR826_J30x_ON
# define CONFIG_SYS_CMXFCR_VALUE1	(CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK10)
#else
# define CONFIG_SYS_CMXFCR_VALUE1	(CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
#endif
/*
 * - Rx-CLK is CLK15
 * - Tx-CLK is CLK14
 */
#define	CONFIG_ETHER_ON_FCC2
# define CONFIG_SYS_CMXFCR_MASK2	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
# define CONFIG_SYS_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
/*
 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
 * - Enable Full Duplex in FSMR
 */
# define CONFIG_SYS_CPMFCR_RAMTYPE	0
# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)

/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
#define CONFIG_8260_CLKIN	64000000	/* in Hz */

#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
#define CONFIG_BAUDRATE		230400
#else
#define CONFIG_BAUDRATE		9600
#endif

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_BEDBUG
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP

#ifdef CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_CMD_PCI
#endif

/*
 * Miscellaneous configurable options
 */
#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#if defined(CONFIG_CMD_KGDB)
#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END	0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define	CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address	*/

#define	CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC	/* "bad" address		*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * Flash and Boot ROM mapping
 */
#ifdef CONFIG_FLASH_32MB
#define	CONFIG_SYS_FLASH0_BASE		0x40000000
#define	CONFIG_SYS_FLASH0_SIZE		0x02000000
#else
#define	CONFIG_SYS_FLASH0_BASE		0xFF000000
#define	CONFIG_SYS_FLASH0_SIZE		0x00800000
#endif
#define	CONFIG_SYS_BOOTROM_BASE	0xFF800000
#define	CONFIG_SYS_BOOTROM_SIZE	0x00080000
#define CONFIG_SYS_DOC_BASE		0xFF800000
#define CONFIG_SYS_DOC_SIZE		0x00100000

/* Flash bank size (for preliminary settings)
 */
#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks      */
#ifdef CONFIG_FLASH_32MB
#define CONFIG_SYS_MAX_FLASH_SECT	135	/* max num of sects on one chip */
#else
#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */
#endif
#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */

#if 0
/* Start port with environment in flash; switch to EEPROM later */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE+0x40000)
#define CONFIG_ENV_SIZE		0x40000
#define CONFIG_ENV_SECT_SIZE	0x40000
#else
/* Final version: environment in EEPROM */
#define CONFIG_ENV_IS_IN_EEPROM	1
#define CONFIG_SYS_I2C_EEPROM_ADDR	0x58
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
#define CONFIG_ENV_OFFSET		512
#define CONFIG_ENV_SIZE		(2048 - 512)
#endif

/*-----------------------------------------------------------------------
 * Hard Reset Configuration Words
 *
 * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
 * defines for the various registers affected by the HRCW e.g. changing
 * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
 */
#if defined(CONFIG_BOOT_ROM)
#define CONFIG_SYS_HRCW_MASTER		(HRCW_BPS01 | HRCW_CIP | HRCW_ISB100 | HRCW_BMS)
#else
#define CONFIG_SYS_HRCW_MASTER		(HRCW_CIP | HRCW_ISB100 | HRCW_BMS)
#endif

/* no slaves so just fill with zeros */
#define CONFIG_SYS_HRCW_SLAVE1		0
#define CONFIG_SYS_HRCW_SLAVE2		0
#define CONFIG_SYS_HRCW_SLAVE3		0
#define CONFIG_SYS_HRCW_SLAVE4		0
#define CONFIG_SYS_HRCW_SLAVE5		0
#define CONFIG_SYS_HRCW_SLAVE6		0
#define CONFIG_SYS_HRCW_SLAVE7		0

/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CONFIG_SYS_IMMR		0xF0000000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
#define CONFIG_SYS_INIT_RAM_SIZE	0x4000  /* Size of used area in DPRAM    */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 *
 * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE, local SDRAM
 * is mapped at SDRAM_BASE2_PRELIM.
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_FLASH0_BASE
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/

#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
# define CONFIG_SYS_RAMBOOT
#endif

#ifdef	CONFIG_PCI
#define CONFIG_PCI_PNP
#define CONFIG_EEPRO100
#define CONFIG_SYS_RX_ETH_BUFFER	8               /* use 8 rx buffer on eepro100  */
#endif

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
#if defined(CONFIG_CMD_KGDB)
#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif

/*-----------------------------------------------------------------------
 * HIDx - Hardware Implementation-dependent Registers                    2-11
 *-----------------------------------------------------------------------
 * HID0 also contains cache control - initially enable both caches and
 * invalidate contents, then the final state leaves only the instruction
 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 * but Soft reset does not.
 *
 * HID1 has only read-only information - nothing to set.
 */
#define CONFIG_SYS_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
				HID0_IFEM|HID0_ABE)
#define CONFIG_SYS_HID0_FINAL  (HID0_ICE|HID0_IFEM|HID0_ABE)
#define CONFIG_SYS_HID2        0

/*-----------------------------------------------------------------------
 * RMR - Reset Mode Register                                     5-5
 *-----------------------------------------------------------------------
 * turn on Checkstop Reset Enable
 */
#define CONFIG_SYS_RMR         RMR_CSRE

/*-----------------------------------------------------------------------
 * BCR - Bus Configuration                                       4-25
 *-----------------------------------------------------------------------
 */

#define BCR_APD01       0x10000000
#define CONFIG_SYS_BCR         (BCR_APD01|BCR_ETM|BCR_LETM)    /* 8260 mode */

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration                             4-31
 *-----------------------------------------------------------------------
 */
#if 0
#define CONFIG_SYS_SIUMCR	(SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_CS10PC01)
#else
#define CONFIG_SYS_SIUMCR	(SIUMCR_DPPC10|SIUMCR_APPC10)
#endif


/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control                             4-35
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 */
#if defined(CONFIG_WATCHDOG)
#define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
#else
#define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
			 SYPCR_SWRI|SYPCR_SWP)
#endif /* CONFIG_WATCHDOG */

/*-----------------------------------------------------------------------
 * TMCNTSC - Time Counter Status and Control                     4-40
 *-----------------------------------------------------------------------
 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 * and enable Time Counter
 */
#define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control                 4-42
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 * Periodic timer
 */
#define CONFIG_SYS_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)

/*-----------------------------------------------------------------------
 * SCCR - System Clock Control                                   9-8
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_SCCR        (SCCR_DFBRG00)

/*-----------------------------------------------------------------------
 * RCCR - RISC Controller Configuration                         13-7
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_RCCR        0

/*
 * Init Memory Controller:
 *
 * Bank Bus     Machine PortSz  Device
 * ---- ---     ------- ------  ------
 *  0   60x     GPCM    64 bit  FLASH
 *  1   60x     SDRAM   64 bit  SDRAM
 *
 */

	/* Initialize SDRAM on local bus
	 */
#define CONFIG_SYS_INIT_LOCAL_SDRAM


/* Minimum mask to separate preliminary
 * address ranges for CS[0:2]
 */
#define CONFIG_SYS_MIN_AM_MASK	0xC0000000

/*
 * we use the same values for 32 MB and 128 MB SDRAM
 * refresh rate = 7.73 uS (64 MHz Bus Clock)
 */
#define CONFIG_SYS_MPTPR       0x2000
#define CONFIG_SYS_PSRT        0x0E

#define CONFIG_SYS_MRS_OFFS	0x00000000


#if defined(CONFIG_BOOT_ROM)
/*
 * Bank 0 - Boot ROM (8 bit wide)
 */
#define CONFIG_SYS_BR0_PRELIM	((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\
			 BRx_PS_8			|\
			 BRx_MS_GPCM_P			|\
			 BRx_V)

#define CONFIG_SYS_OR0_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE)	|\
			 ORxG_CSNT			|\
			 ORxG_ACS_DIV1			|\
			 ORxG_SCY_3_CLK			|\
			 ORxG_EHTR			|\
			 ORxG_TRLX)

/*
 * Bank 1 - Flash (64 bit wide)
 */
#define CONFIG_SYS_BR1_PRELIM	((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)	|\
			 BRx_PS_64			|\
			 BRx_MS_GPCM_P			|\
			 BRx_V)

#define CONFIG_SYS_OR1_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE)	|\
			 ORxG_CSNT			|\
			 ORxG_ACS_DIV1			|\
			 ORxG_SCY_3_CLK			|\
			 ORxG_EHTR			|\
			 ORxG_TRLX)

#else	/* ! CONFIG_BOOT_ROM */

/*
 * Bank 0 - Flash (64 bit wide)
 */
#define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)  |\
			 BRx_PS_64                      |\
			 BRx_MS_GPCM_P                  |\
			 BRx_V)

#define CONFIG_SYS_OR0_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE)	|\
			 ORxG_CSNT                      |\
			 ORxG_ACS_DIV1                  |\
			 ORxG_SCY_3_CLK                 |\
			 ORxG_EHTR                      |\
			 ORxG_TRLX)

/*
 * Bank 1 - Disk-On-Chip
 */
#define CONFIG_SYS_BR1_PRELIM	((CONFIG_SYS_DOC_BASE & BRx_BA_MSK)	|\
			 BRx_PS_8			|\
			 BRx_MS_GPCM_P			|\
			 BRx_V)

#define CONFIG_SYS_OR1_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_DOC_SIZE)	|\
			 ORxG_CSNT			|\
			 ORxG_ACS_DIV1			|\
			 ORxG_SCY_3_CLK			|\
			 ORxG_EHTR			|\
			 ORxG_TRLX)

#endif /* CONFIG_BOOT_ROM */

/* Bank 2 - SDRAM
 */

#ifndef CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_BR2_PRELIM  ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)  |\
			 BRx_PS_64                      |\
			 BRx_MS_SDRAM_P                 |\
			 BRx_V)

	/* SDRAM initialization values for 8-column chips
	 */
#define CONFIG_SYS_OR2_8COL    (CONFIG_SYS_MIN_AM_MASK	        |\
			 ORxS_BPD_4                     |\
			 ORxS_ROWST_PBI0_A9             |\
			 ORxS_NUMR_12)

#define CONFIG_SYS_PSDMR_8COL  (PSDMR_SDAM_A13_IS_A5           |\
			 PSDMR_BSMA_A14_A16             |\
			 PSDMR_SDA10_PBI0_A10           |\
			 PSDMR_RFRC_7_CLK               |\
			 PSDMR_PRETOACT_2W              |\
			 PSDMR_ACTTORW_1W               |\
			 PSDMR_LDOTOPRE_1C              |\
			 PSDMR_WRC_1C                   |\
			 PSDMR_CL_2)

	/* SDRAM initialization values for 9-column chips
	 */
#define CONFIG_SYS_OR2_9COL    (CONFIG_SYS_MIN_AM_MASK                |\
			 ORxS_BPD_4                     |\
			 ORxS_ROWST_PBI0_A7             |\
			 ORxS_NUMR_13)

#define CONFIG_SYS_PSDMR_9COL  (PSDMR_SDAM_A14_IS_A5           |\
			 PSDMR_BSMA_A13_A15             |\
			 PSDMR_SDA10_PBI0_A9            |\
			 PSDMR_RFRC_7_CLK               |\
			 PSDMR_PRETOACT_2W              |\
			 PSDMR_ACTTORW_1W               |\
			 PSDMR_LDOTOPRE_1C              |\
			 PSDMR_WRC_1C                   |\
			 PSDMR_CL_2)

#define CONFIG_SYS_OR2_PRELIM   CONFIG_SYS_OR2_9COL
#define CONFIG_SYS_PSDMR        CONFIG_SYS_PSDMR_9COL

#endif /* CONFIG_SYS_RAMBOOT */

#endif	/* __CONFIG_H */
Commit	Line	Data
0f8c9768	1	/*
414eec35	2	* (C) Copyright 2001-2005
0f8c9768 WD	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
0f8c9768 WD	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
0f8c9768 WD	6	*/
	7
	8	/*
	9	* board/config.h - configuration options, board specific
	10	*/
	11
	12	#ifndef __CONFIG_H
	13	#define __CONFIG_H
	14
6d0f6bcf	15	#undef CONFIG_SYS_RAMBOOT
0f8c9768 WD	16
	17	/*
	18	* High Level Configuration Options
	19	* (easy to change)
	20	*/
	21
0f8c9768	22	#define CONFIG_PM826 1 /* ...on a PM8260 module */
9c4c5ae3	23	#define CONFIG_CPM2 1 /* Has a CPM2 */
0f8c9768	24
2ae18241 WD	25	#ifndef CONFIG_SYS_TEXT_BASE
	26	#define CONFIG_SYS_TEXT_BASE 0xFF000000 /* Standard: boot 64-bit flash */
	27	#endif
	28
aacf9a49 WD	29	#undef CONFIG_DB_CR826_J30x_ON /* J30x jumpers on D.B. carrier */
aacf9a49 WD	30
0f8c9768 WD	31	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
0f8c9768 WD	32
32bf3d14	33	#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
0f8c9768 WD	34
	35	#undef CONFIG_BOOTARGS
	36	#define CONFIG_BOOTCOMMAND \
53677ef1 WD	37	"bootp; " \
	38	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
	39	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
0f8c9768 WD	40	"bootm"
	41
	42	/* enable I2C and select the hardware/software driver */
ea818dbb HS	43	#define CONFIG_SYS_I2C
	44	#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
	45	#define CONFIG_SYS_I2C_SOFT_SPEED 50000
	46	#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
0f8c9768 WD	47	/*
	48	* Software (bit-bang) I2C driver configuration
	49	*/
	50	#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
	51	#define I2C_ACTIVE (iop->pdir \|= 0x00010000)
	52	#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
	53	#define I2C_READ ((iop->pdat & 0x00010000) != 0)
	54	#define I2C_SDA(bit) if(bit) iop->pdat \|= 0x00010000; \
	55	else iop->pdat &= ~0x00010000
	56	#define I2C_SCL(bit) if(bit) iop->pdat \|= 0x00020000; \
	57	else iop->pdat &= ~0x00020000
	58	#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
	59
	60
	61	#define CONFIG_RTC_PCF8563
6d0f6bcf	62	#define CONFIG_SYS_I2C_RTC_ADDR 0x51
0f8c9768 WD	63
	64	/*
	65	* select serial console configuration
	66	*
	67	* if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
	68	* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
	69	* for SCC).
	70	*
	71	* if CONFIG_CONS_NONE is defined, then the serial console routines must
	72	* defined elsewhere (for example, on the cogent platform, there are serial
	73	* ports on the motherboard which are used for the serial console - see
	74	* cogent/cma101/serial.[ch]).
	75	*/
	76	#define CONFIG_CONS_ON_SMC /* define if console on SMC */
	77	#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
	78	#undef CONFIG_CONS_NONE /* define if console on something else*/
	79	#define CONFIG_CONS_INDEX 2 /* which serial channel for console */
	80
	81	/*
	82	* select ethernet configuration
	83	*
aacf9a49 WD	84	* if CONFIG_ETHER_ON_SCC is selected, then
aacf9a49 WD	85	* - CONFIG_ETHER_INDEX must be set to the channel number (1-4)
aacf9a49 WD	86	*
	87	* if CONFIG_ETHER_ON_FCC is selected, then
	88	* - one or more CONFIG_ETHER_ON_FCCx (x=1,2,3) must also be selected
0f8c9768 WD	89	*
0f8c9768 WD	90	* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
639221c7	91	* defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
0f8c9768	92	*/
0f8c9768	93	#undef CONFIG_ETHER_NONE /* define if ether on something else */
0f8c9768	94
aacf9a49 WD	95	#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
	96	#define CONFIG_ETHER_INDEX 1 /* which SCC channel for ethernet */
	97
	98	#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
0f8c9768 WD	99	/*
	100	* - Rx-CLK is CLK11
	101	* - Tx-CLK is CLK10
aacf9a49 WD	102	*/
aacf9a49 WD	103	#define CONFIG_ETHER_ON_FCC1
6d0f6bcf	104	# define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1\|CMXFCR_RF1CS_MSK\|CMXFCR_TF1CS_MSK)
aacf9a49	105	#ifndef CONFIG_DB_CR826_J30x_ON
6d0f6bcf	106	# define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11\|CMXFCR_TF1CS_CLK10)
aacf9a49	107	#else
6d0f6bcf	108	# define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11\|CMXFCR_TF1CS_CLK12)
aacf9a49 WD	109	#endif
	110	/*
	111	* - Rx-CLK is CLK15
	112	* - Tx-CLK is CLK14
	113	*/
	114	#define CONFIG_ETHER_ON_FCC2
6d0f6bcf JCPV	115	# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2\|CMXFCR_RF2CS_MSK\|CMXFCR_TF2CS_MSK)
6d0f6bcf JCPV	116	# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13\|CMXFCR_TF2CS_CLK14)
aacf9a49	117	/*
0f8c9768 WD	118	* - RAM for BD/Buffers is on the 60x Bus (see 28-13)
	119	* - Enable Full Duplex in FSMR
	120	*/
6d0f6bcf JCPV	121	# define CONFIG_SYS_CPMFCR_RAMTYPE 0
6d0f6bcf JCPV	122	# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE\|FCC_PSMR_LPB)
0f8c9768	123
0f8c9768 WD	124	/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
	125	#define CONFIG_8260_CLKIN 64000000 /* in Hz */
	126
	127	#if defined(CONFIG_CONS_NONE) \|\| defined(CONFIG_CONS_USE_EXTC)
	128	#define CONFIG_BAUDRATE 230400
	129	#else
	130	#define CONFIG_BAUDRATE 9600
	131	#endif
	132
	133	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	134	#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
0f8c9768 WD	135
	136	#undef CONFIG_WATCHDOG /* watchdog disabled */
	137
18225e8d JL	138	/*
	139	* BOOTP options
	140	*/
	141	#define CONFIG_BOOTP_SUBNETMASK
	142	#define CONFIG_BOOTP_GATEWAY
	143	#define CONFIG_BOOTP_HOSTNAME
	144	#define CONFIG_BOOTP_BOOTPATH
	145	#define CONFIG_BOOTP_BOOTFILESIZE
0f8c9768	146
acf02697 JL	147
	148	/*
	149	* Command line configuration.
	150	*/
	151	#include <config_cmd_default.h>
	152
	153	#define CONFIG_CMD_BEDBUG
	154	#define CONFIG_CMD_DATE
	155	#define CONFIG_CMD_DHCP
acf02697 JL	156	#define CONFIG_CMD_EEPROM
	157	#define CONFIG_CMD_I2C
	158	#define CONFIG_CMD_NFS
	159	#define CONFIG_CMD_SNTP
	160
5d232d0e	161	#ifdef CONFIG_PCI
842033e6	162	#define CONFIG_PCI_INDIRECT_BRIDGE
acf02697 JL	163	#define CONFIG_CMD_PCI
	164	#endif
	165
0f8c9768 WD	166	/*
	167	* Miscellaneous configurable options
	168	*/
6d0f6bcf	169	#define CONFIG_SYS_LONGHELP /* undef to save memory */
acf02697	170	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	171	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
0f8c9768	172	#else
6d0f6bcf	173	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
0f8c9768	174	#endif
6d0f6bcf JCPV	175	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	176	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	177	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
0f8c9768	178
6d0f6bcf JCPV	179	#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
6d0f6bcf JCPV	180	#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
0f8c9768	181
6d0f6bcf	182	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
0f8c9768	183
6d0f6bcf	184	#define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */
0f8c9768 WD	185
	186	/*
	187	* For booting Linux, the board info and command line data
	188	* have to be in the first 8 MB of memory, since this is
	189	* the maximum mapped by the Linux kernel during initialization.
	190	*/
6d0f6bcf	191	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
0f8c9768 WD	192
	193	/*-----------------------------------------------------------------------
	194	* Flash and Boot ROM mapping
	195	*/
efa329cb	196	#ifdef CONFIG_FLASH_32MB
6d0f6bcf JCPV	197	#define CONFIG_SYS_FLASH0_BASE 0x40000000
6d0f6bcf JCPV	198	#define CONFIG_SYS_FLASH0_SIZE 0x02000000
efa329cb	199	#else
6d0f6bcf JCPV	200	#define CONFIG_SYS_FLASH0_BASE 0xFF000000
6d0f6bcf JCPV	201	#define CONFIG_SYS_FLASH0_SIZE 0x00800000
efa329cb	202	#endif
6d0f6bcf JCPV	203	#define CONFIG_SYS_BOOTROM_BASE 0xFF800000
	204	#define CONFIG_SYS_BOOTROM_SIZE 0x00080000
	205	#define CONFIG_SYS_DOC_BASE 0xFF800000
	206	#define CONFIG_SYS_DOC_SIZE 0x00100000
0f8c9768	207
0f8c9768 WD	208	/* Flash bank size (for preliminary settings)
0f8c9768 WD	209	*/
6d0f6bcf	210	#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
0f8c9768 WD	211
	212	/*-----------------------------------------------------------------------
	213	* FLASH organization
	214	*/
6d0f6bcf	215	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
efa329cb	216	#ifdef CONFIG_FLASH_32MB
6d0f6bcf	217	#define CONFIG_SYS_MAX_FLASH_SECT 135 /* max num of sects on one chip */
efa329cb	218	#else
6d0f6bcf	219	#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
efa329cb	220	#endif
6d0f6bcf JCPV	221	#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
6d0f6bcf JCPV	222	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
0f8c9768 WD	223
	224	#if 0
	225	/* Start port with environment in flash; switch to EEPROM later */
5a1aceb0	226	#define CONFIG_ENV_IS_IN_FLASH 1
6d0f6bcf	227	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x40000)
0e8d1586 JCPV	228	#define CONFIG_ENV_SIZE 0x40000
0e8d1586 JCPV	229	#define CONFIG_ENV_SECT_SIZE 0x40000
0f8c9768 WD	230	#else
0f8c9768 WD	231	/* Final version: environment in EEPROM */
bb1f8b4f	232	#define CONFIG_ENV_IS_IN_EEPROM 1
6d0f6bcf JCPV	233	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58
	234	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	235	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
	236	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
0e8d1586 JCPV	237	#define CONFIG_ENV_OFFSET 512
0e8d1586 JCPV	238	#define CONFIG_ENV_SIZE (2048 - 512)
0f8c9768 WD	239	#endif
	240
	241	/*-----------------------------------------------------------------------
	242	* Hard Reset Configuration Words
	243	*
6d0f6bcf	244	* if you change bits in the HRCW, you must also change the CONFIG_SYS_*
0f8c9768	245	* defines for the various registers affected by the HRCW e.g. changing
6d0f6bcf	246	* HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
0f8c9768 WD	247	*/
0f8c9768 WD	248	#if defined(CONFIG_BOOT_ROM)
6d0f6bcf	249	#define CONFIG_SYS_HRCW_MASTER (HRCW_BPS01 \| HRCW_CIP \| HRCW_ISB100 \| HRCW_BMS)
0f8c9768	250	#else
6d0f6bcf	251	#define CONFIG_SYS_HRCW_MASTER (HRCW_CIP \| HRCW_ISB100 \| HRCW_BMS)
0f8c9768 WD	252	#endif
	253
	254	/* no slaves so just fill with zeros */
6d0f6bcf JCPV	255	#define CONFIG_SYS_HRCW_SLAVE1 0
	256	#define CONFIG_SYS_HRCW_SLAVE2 0
	257	#define CONFIG_SYS_HRCW_SLAVE3 0
	258	#define CONFIG_SYS_HRCW_SLAVE4 0
	259	#define CONFIG_SYS_HRCW_SLAVE5 0
	260	#define CONFIG_SYS_HRCW_SLAVE6 0
	261	#define CONFIG_SYS_HRCW_SLAVE7 0
0f8c9768 WD	262
	263	/*-----------------------------------------------------------------------
	264	* Internal Memory Mapped Register
	265	*/
6d0f6bcf	266	#define CONFIG_SYS_IMMR 0xF0000000
0f8c9768 WD	267
	268	/*-----------------------------------------------------------------------
	269	* Definitions for initial stack pointer and data area (in DPRAM)
	270	*/
6d0f6bcf	271	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
553f0982	272	#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
25ddd1fb	273	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	274	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
0f8c9768 WD	275
	276	/*-----------------------------------------------------------------------
	277	* Start addresses for the final memory configuration
	278	* (Set up by the startup code)
6d0f6bcf	279	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
0f8c9768	280	*
6d0f6bcf	281	* 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE, local SDRAM
0f8c9768 WD	282	* is mapped at SDRAM_BASE2_PRELIM.
0f8c9768 WD	283	*/
6d0f6bcf JCPV	284	#define CONFIG_SYS_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	285	#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE
14d0a02a	286	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
6d0f6bcf JCPV	287	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
6d0f6bcf JCPV	288	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
0f8c9768	289
6d0f6bcf JCPV	290	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
6d0f6bcf JCPV	291	# define CONFIG_SYS_RAMBOOT
0f8c9768 WD	292	#endif
0f8c9768 WD	293
10f67017	294	#ifdef CONFIG_PCI
4d75a504 WD	295	#define CONFIG_PCI_PNP
4d75a504 WD	296	#define CONFIG_EEPRO100
6d0f6bcf	297	#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
10f67017	298	#endif
4d75a504	299
0f8c9768 WD	300	/*-----------------------------------------------------------------------
	301	* Cache Configuration
	302	*/
6d0f6bcf	303	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
acf02697	304	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	305	# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
0f8c9768 WD	306	#endif
	307
	308	/*-----------------------------------------------------------------------
	309	* HIDx - Hardware Implementation-dependent Registers 2-11
	310	*-----------------------------------------------------------------------
	311	* HID0 also contains cache control - initially enable both caches and
	312	* invalidate contents, then the final state leaves only the instruction
	313	* cache enabled. Note that Power-On and Hard reset invalidate the caches,
	314	* but Soft reset does not.
	315	*
	316	* HID1 has only read-only information - nothing to set.
	317	*/
6d0f6bcf	318	#define CONFIG_SYS_HID0_INIT (HID0_ICE\|HID0_DCE\|HID0_ICFI\|HID0_DCI\|\
8bde7f77	319	HID0_IFEM\|HID0_ABE)
6d0f6bcf JCPV	320	#define CONFIG_SYS_HID0_FINAL (HID0_ICE\|HID0_IFEM\|HID0_ABE)
6d0f6bcf JCPV	321	#define CONFIG_SYS_HID2 0
0f8c9768 WD	322
	323	/*-----------------------------------------------------------------------
	324	* RMR - Reset Mode Register 5-5
	325	*-----------------------------------------------------------------------
	326	* turn on Checkstop Reset Enable
	327	*/
6d0f6bcf	328	#define CONFIG_SYS_RMR RMR_CSRE
0f8c9768 WD	329
	330	/*-----------------------------------------------------------------------
	331	* BCR - Bus Configuration 4-25
	332	*-----------------------------------------------------------------------
	333	*/
	334
	335	#define BCR_APD01 0x10000000
6d0f6bcf	336	#define CONFIG_SYS_BCR (BCR_APD01\|BCR_ETM\|BCR_LETM) /* 8260 mode */
0f8c9768 WD	337
	338	/*-----------------------------------------------------------------------
	339	* SIUMCR - SIU Module Configuration 4-31
	340	*-----------------------------------------------------------------------
	341	*/
	342	#if 0
6d0f6bcf	343	#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC00\|SIUMCR_APPC10\|SIUMCR_CS10PC01)
0f8c9768	344	#else
6d0f6bcf	345	#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC10\|SIUMCR_APPC10)
0f8c9768 WD	346	#endif
	347
	348
	349	/*-----------------------------------------------------------------------
	350	* SYPCR - System Protection Control 4-35
	351	* SYPCR can only be written once after reset!
	352	*-----------------------------------------------------------------------
	353	* Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
	354	*/
	355	#if defined(CONFIG_WATCHDOG)
6d0f6bcf	356	#define CONFIG_SYS_SYPCR (SYPCR_SWTC\|SYPCR_BMT\|SYPCR_PBME\|SYPCR_LBME\|\
8bde7f77	357	SYPCR_SWRI\|SYPCR_SWP\|SYPCR_SWE)
0f8c9768	358	#else
6d0f6bcf	359	#define CONFIG_SYS_SYPCR (SYPCR_SWTC\|SYPCR_BMT\|SYPCR_PBME\|SYPCR_LBME\|\
8bde7f77	360	SYPCR_SWRI\|SYPCR_SWP)
0f8c9768 WD	361	#endif /* CONFIG_WATCHDOG */
	362
	363	/*-----------------------------------------------------------------------
	364	* TMCNTSC - Time Counter Status and Control 4-40
	365	*-----------------------------------------------------------------------
	366	* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
	367	* and enable Time Counter
	368	*/
6d0f6bcf	369	#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC\|TMCNTSC_ALR\|TMCNTSC_TCF\|TMCNTSC_TCE)
0f8c9768 WD	370
	371	/*-----------------------------------------------------------------------
	372	* PISCR - Periodic Interrupt Status and Control 4-42
	373	*-----------------------------------------------------------------------
	374	* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
	375	* Periodic timer
	376	*/
6d0f6bcf	377	#define CONFIG_SYS_PISCR (PISCR_PS\|PISCR_PTF\|PISCR_PTE)
0f8c9768 WD	378
	379	/*-----------------------------------------------------------------------
	380	* SCCR - System Clock Control 9-8
	381	*-----------------------------------------------------------------------
	382	*/
6d0f6bcf	383	#define CONFIG_SYS_SCCR (SCCR_DFBRG00)
0f8c9768 WD	384
	385	/*-----------------------------------------------------------------------
	386	* RCCR - RISC Controller Configuration 13-7
	387	*-----------------------------------------------------------------------
	388	*/
6d0f6bcf	389	#define CONFIG_SYS_RCCR 0
0f8c9768 WD	390
	391	/*
	392	* Init Memory Controller:
	393	*
	394	* Bank Bus Machine PortSz Device
	395	* ---- --- ------- ------ ------
	396	* 0 60x GPCM 64 bit FLASH
	397	* 1 60x SDRAM 64 bit SDRAM
0f8c9768 WD	398	*
	399	*/
	400
	401	/* Initialize SDRAM on local bus
	402	*/
6d0f6bcf	403	#define CONFIG_SYS_INIT_LOCAL_SDRAM
0f8c9768 WD	404
	405
	406	/* Minimum mask to separate preliminary
	407	* address ranges for CS[0:2]
	408	*/
6d0f6bcf	409	#define CONFIG_SYS_MIN_AM_MASK 0xC0000000
0f8c9768	410
efa329cb WD	411	/*
	412	* we use the same values for 32 MB and 128 MB SDRAM
	413	* refresh rate = 7.73 uS (64 MHz Bus Clock)
	414	*/
6d0f6bcf JCPV	415	#define CONFIG_SYS_MPTPR 0x2000
6d0f6bcf JCPV	416	#define CONFIG_SYS_PSRT 0x0E
0f8c9768	417
6d0f6bcf	418	#define CONFIG_SYS_MRS_OFFS 0x00000000
0f8c9768 WD	419
	420
	421	#if defined(CONFIG_BOOT_ROM)
	422	/*
	423	* Bank 0 - Boot ROM (8 bit wide)
	424	*/
6d0f6bcf	425	#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)\|\
0f8c9768 WD	426	BRx_PS_8 \|\
	427	BRx_MS_GPCM_P \|\
	428	BRx_V)
	429
6d0f6bcf	430	#define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE) \|\
0f8c9768 WD	431	ORxG_CSNT \|\
	432	ORxG_ACS_DIV1 \|\
	433	ORxG_SCY_3_CLK \|\
	434	ORxG_EHTR \|\
	435	ORxG_TRLX)
	436
	437	/*
	438	* Bank 1 - Flash (64 bit wide)
	439	*/
6d0f6bcf	440	#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) \|\
0f8c9768 WD	441	BRx_PS_64 \|\
	442	BRx_MS_GPCM_P \|\
	443	BRx_V)
	444
6d0f6bcf	445	#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE) \|\
0f8c9768 WD	446	ORxG_CSNT \|\
	447	ORxG_ACS_DIV1 \|\
	448	ORxG_SCY_3_CLK \|\
	449	ORxG_EHTR \|\
	450	ORxG_TRLX)
	451
	452	#else /* ! CONFIG_BOOT_ROM */
	453
	454	/*
	455	* Bank 0 - Flash (64 bit wide)
	456	*/
6d0f6bcf	457	#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) \|\
8bde7f77 WD	458	BRx_PS_64 \|\
	459	BRx_MS_GPCM_P \|\
	460	BRx_V)
0f8c9768	461
6d0f6bcf	462	#define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE) \|\
8bde7f77 WD	463	ORxG_CSNT \|\
	464	ORxG_ACS_DIV1 \|\
	465	ORxG_SCY_3_CLK \|\
	466	ORxG_EHTR \|\
	467	ORxG_TRLX)
0f8c9768 WD	468
	469	/*
	470	* Bank 1 - Disk-On-Chip
	471	*/
6d0f6bcf	472	#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_DOC_BASE & BRx_BA_MSK) \|\
0f8c9768 WD	473	BRx_PS_8 \|\
	474	BRx_MS_GPCM_P \|\
	475	BRx_V)
	476
6d0f6bcf	477	#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_DOC_SIZE) \|\
0f8c9768 WD	478	ORxG_CSNT \|\
	479	ORxG_ACS_DIV1 \|\
	480	ORxG_SCY_3_CLK \|\
	481	ORxG_EHTR \|\
	482	ORxG_TRLX)
	483
	484	#endif /* CONFIG_BOOT_ROM */
	485
	486	/* Bank 2 - SDRAM
	487	*/
efa329cb	488
6d0f6bcf JCPV	489	#ifndef CONFIG_SYS_RAMBOOT
6d0f6bcf JCPV	490	#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) \|\
8bde7f77 WD	491	BRx_PS_64 \|\
	492	BRx_MS_SDRAM_P \|\
	493	BRx_V)
0f8c9768 WD	494
	495	/* SDRAM initialization values for 8-column chips
	496	*/
6d0f6bcf	497	#define CONFIG_SYS_OR2_8COL (CONFIG_SYS_MIN_AM_MASK \|\
8bde7f77 WD	498	ORxS_BPD_4 \|\
	499	ORxS_ROWST_PBI0_A9 \|\
	500	ORxS_NUMR_12)
0f8c9768	501
6d0f6bcf	502	#define CONFIG_SYS_PSDMR_8COL (PSDMR_SDAM_A13_IS_A5 \|\
8bde7f77 WD	503	PSDMR_BSMA_A14_A16 \|\
	504	PSDMR_SDA10_PBI0_A10 \|\
	505	PSDMR_RFRC_7_CLK \|\
	506	PSDMR_PRETOACT_2W \|\
	507	PSDMR_ACTTORW_1W \|\
	508	PSDMR_LDOTOPRE_1C \|\
	509	PSDMR_WRC_1C \|\
	510	PSDMR_CL_2)
0f8c9768 WD	511
	512	/* SDRAM initialization values for 9-column chips
	513	*/
6d0f6bcf	514	#define CONFIG_SYS_OR2_9COL (CONFIG_SYS_MIN_AM_MASK \|\
8bde7f77 WD	515	ORxS_BPD_4 \|\
	516	ORxS_ROWST_PBI0_A7 \|\
	517	ORxS_NUMR_13)
0f8c9768	518
6d0f6bcf	519	#define CONFIG_SYS_PSDMR_9COL (PSDMR_SDAM_A14_IS_A5 \|\
8bde7f77 WD	520	PSDMR_BSMA_A13_A15 \|\
	521	PSDMR_SDA10_PBI0_A9 \|\
	522	PSDMR_RFRC_7_CLK \|\
	523	PSDMR_PRETOACT_2W \|\
	524	PSDMR_ACTTORW_1W \|\
	525	PSDMR_LDOTOPRE_1C \|\
	526	PSDMR_WRC_1C \|\
	527	PSDMR_CL_2)
0f8c9768	528
6d0f6bcf JCPV	529	#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2_9COL
6d0f6bcf JCPV	530	#define CONFIG_SYS_PSDMR CONFIG_SYS_PSDMR_9COL
0f8c9768	531
6d0f6bcf	532	#endif /* CONFIG_SYS_RAMBOOT */
0f8c9768 WD	533
0f8c9768 WD	534	#endif /* __CONFIG_H */