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0f8c9768 | 1 | /* |
414eec35 | 2 | * (C) Copyright 2001-2005 |
0f8c9768 WD |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * board/config.h - configuration options, board specific | |
26 | */ | |
27 | ||
28 | #ifndef __CONFIG_H | |
29 | #define __CONFIG_H | |
30 | ||
6d0f6bcf | 31 | #undef CONFIG_SYS_RAMBOOT |
0f8c9768 WD |
32 | |
33 | /* | |
34 | * High Level Configuration Options | |
35 | * (easy to change) | |
36 | */ | |
37 | ||
38 | #define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */ | |
39 | #define CONFIG_PM826 1 /* ...on a PM8260 module */ | |
9c4c5ae3 | 40 | #define CONFIG_CPM2 1 /* Has a CPM2 */ |
0f8c9768 | 41 | |
2ae18241 WD |
42 | #ifndef CONFIG_SYS_TEXT_BASE |
43 | #define CONFIG_SYS_TEXT_BASE 0xFF000000 /* Standard: boot 64-bit flash */ | |
44 | #endif | |
45 | ||
aacf9a49 WD |
46 | #undef CONFIG_DB_CR826_J30x_ON /* J30x jumpers on D.B. carrier */ |
47 | ||
0f8c9768 WD |
48 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
49 | ||
32bf3d14 | 50 | #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" |
0f8c9768 WD |
51 | |
52 | #undef CONFIG_BOOTARGS | |
53 | #define CONFIG_BOOTCOMMAND \ | |
53677ef1 WD |
54 | "bootp; " \ |
55 | "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ | |
56 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ | |
0f8c9768 WD |
57 | "bootm" |
58 | ||
59 | /* enable I2C and select the hardware/software driver */ | |
60 | #undef CONFIG_HARD_I2C | |
61 | #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ | |
6d0f6bcf JCPV |
62 | # define CONFIG_SYS_I2C_SPEED 50000 |
63 | # define CONFIG_SYS_I2C_SLAVE 0xFE | |
0f8c9768 WD |
64 | /* |
65 | * Software (bit-bang) I2C driver configuration | |
66 | */ | |
67 | #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ | |
68 | #define I2C_ACTIVE (iop->pdir |= 0x00010000) | |
69 | #define I2C_TRISTATE (iop->pdir &= ~0x00010000) | |
70 | #define I2C_READ ((iop->pdat & 0x00010000) != 0) | |
71 | #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ | |
72 | else iop->pdat &= ~0x00010000 | |
73 | #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ | |
74 | else iop->pdat &= ~0x00020000 | |
75 | #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ | |
76 | ||
77 | ||
78 | #define CONFIG_RTC_PCF8563 | |
6d0f6bcf | 79 | #define CONFIG_SYS_I2C_RTC_ADDR 0x51 |
0f8c9768 WD |
80 | |
81 | /* | |
82 | * select serial console configuration | |
83 | * | |
84 | * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then | |
85 | * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 | |
86 | * for SCC). | |
87 | * | |
88 | * if CONFIG_CONS_NONE is defined, then the serial console routines must | |
89 | * defined elsewhere (for example, on the cogent platform, there are serial | |
90 | * ports on the motherboard which are used for the serial console - see | |
91 | * cogent/cma101/serial.[ch]). | |
92 | */ | |
93 | #define CONFIG_CONS_ON_SMC /* define if console on SMC */ | |
94 | #undef CONFIG_CONS_ON_SCC /* define if console on SCC */ | |
95 | #undef CONFIG_CONS_NONE /* define if console on something else*/ | |
96 | #define CONFIG_CONS_INDEX 2 /* which serial channel for console */ | |
97 | ||
98 | /* | |
99 | * select ethernet configuration | |
100 | * | |
aacf9a49 WD |
101 | * if CONFIG_ETHER_ON_SCC is selected, then |
102 | * - CONFIG_ETHER_INDEX must be set to the channel number (1-4) | |
aacf9a49 WD |
103 | * |
104 | * if CONFIG_ETHER_ON_FCC is selected, then | |
105 | * - one or more CONFIG_ETHER_ON_FCCx (x=1,2,3) must also be selected | |
0f8c9768 WD |
106 | * |
107 | * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be | |
639221c7 | 108 | * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. |
0f8c9768 | 109 | */ |
0f8c9768 | 110 | #undef CONFIG_ETHER_NONE /* define if ether on something else */ |
0f8c9768 | 111 | |
aacf9a49 WD |
112 | #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ |
113 | #define CONFIG_ETHER_INDEX 1 /* which SCC channel for ethernet */ | |
114 | ||
115 | #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ | |
0f8c9768 WD |
116 | /* |
117 | * - Rx-CLK is CLK11 | |
118 | * - Tx-CLK is CLK10 | |
aacf9a49 WD |
119 | */ |
120 | #define CONFIG_ETHER_ON_FCC1 | |
6d0f6bcf | 121 | # define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK) |
aacf9a49 | 122 | #ifndef CONFIG_DB_CR826_J30x_ON |
6d0f6bcf | 123 | # define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK10) |
aacf9a49 | 124 | #else |
6d0f6bcf | 125 | # define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12) |
aacf9a49 WD |
126 | #endif |
127 | /* | |
128 | * - Rx-CLK is CLK15 | |
129 | * - Tx-CLK is CLK14 | |
130 | */ | |
131 | #define CONFIG_ETHER_ON_FCC2 | |
6d0f6bcf JCPV |
132 | # define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) |
133 | # define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) | |
aacf9a49 | 134 | /* |
0f8c9768 WD |
135 | * - RAM for BD/Buffers is on the 60x Bus (see 28-13) |
136 | * - Enable Full Duplex in FSMR | |
137 | */ | |
6d0f6bcf JCPV |
138 | # define CONFIG_SYS_CPMFCR_RAMTYPE 0 |
139 | # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) | |
0f8c9768 | 140 | |
0f8c9768 WD |
141 | /* system clock rate (CLKIN) - equal to the 60x and local bus speed */ |
142 | #define CONFIG_8260_CLKIN 64000000 /* in Hz */ | |
143 | ||
144 | #if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC) | |
145 | #define CONFIG_BAUDRATE 230400 | |
146 | #else | |
147 | #define CONFIG_BAUDRATE 9600 | |
148 | #endif | |
149 | ||
150 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 151 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
0f8c9768 WD |
152 | |
153 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
154 | ||
18225e8d JL |
155 | /* |
156 | * BOOTP options | |
157 | */ | |
158 | #define CONFIG_BOOTP_SUBNETMASK | |
159 | #define CONFIG_BOOTP_GATEWAY | |
160 | #define CONFIG_BOOTP_HOSTNAME | |
161 | #define CONFIG_BOOTP_BOOTPATH | |
162 | #define CONFIG_BOOTP_BOOTFILESIZE | |
0f8c9768 | 163 | |
acf02697 JL |
164 | |
165 | /* | |
166 | * Command line configuration. | |
167 | */ | |
168 | #include <config_cmd_default.h> | |
169 | ||
170 | #define CONFIG_CMD_BEDBUG | |
171 | #define CONFIG_CMD_DATE | |
172 | #define CONFIG_CMD_DHCP | |
acf02697 JL |
173 | #define CONFIG_CMD_EEPROM |
174 | #define CONFIG_CMD_I2C | |
175 | #define CONFIG_CMD_NFS | |
176 | #define CONFIG_CMD_SNTP | |
177 | ||
5d232d0e | 178 | #ifdef CONFIG_PCI |
acf02697 JL |
179 | #define CONFIG_CMD_PCI |
180 | #endif | |
181 | ||
0f8c9768 WD |
182 | /* |
183 | * Miscellaneous configurable options | |
184 | */ | |
6d0f6bcf JCPV |
185 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
186 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
acf02697 | 187 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 188 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
0f8c9768 | 189 | #else |
6d0f6bcf | 190 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
0f8c9768 | 191 | #endif |
6d0f6bcf JCPV |
192 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
193 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
194 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
0f8c9768 | 195 | |
6d0f6bcf JCPV |
196 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
197 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
0f8c9768 | 198 | |
6d0f6bcf | 199 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
0f8c9768 | 200 | |
6d0f6bcf | 201 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
0f8c9768 | 202 | |
6d0f6bcf | 203 | #define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */ |
0f8c9768 WD |
204 | |
205 | /* | |
206 | * For booting Linux, the board info and command line data | |
207 | * have to be in the first 8 MB of memory, since this is | |
208 | * the maximum mapped by the Linux kernel during initialization. | |
209 | */ | |
6d0f6bcf | 210 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
0f8c9768 WD |
211 | |
212 | /*----------------------------------------------------------------------- | |
213 | * Flash and Boot ROM mapping | |
214 | */ | |
efa329cb | 215 | #ifdef CONFIG_FLASH_32MB |
6d0f6bcf JCPV |
216 | #define CONFIG_SYS_FLASH0_BASE 0x40000000 |
217 | #define CONFIG_SYS_FLASH0_SIZE 0x02000000 | |
efa329cb | 218 | #else |
6d0f6bcf JCPV |
219 | #define CONFIG_SYS_FLASH0_BASE 0xFF000000 |
220 | #define CONFIG_SYS_FLASH0_SIZE 0x00800000 | |
efa329cb | 221 | #endif |
6d0f6bcf JCPV |
222 | #define CONFIG_SYS_BOOTROM_BASE 0xFF800000 |
223 | #define CONFIG_SYS_BOOTROM_SIZE 0x00080000 | |
224 | #define CONFIG_SYS_DOC_BASE 0xFF800000 | |
225 | #define CONFIG_SYS_DOC_SIZE 0x00100000 | |
0f8c9768 | 226 | |
0f8c9768 WD |
227 | /* Flash bank size (for preliminary settings) |
228 | */ | |
6d0f6bcf | 229 | #define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE |
0f8c9768 WD |
230 | |
231 | /*----------------------------------------------------------------------- | |
232 | * FLASH organization | |
233 | */ | |
6d0f6bcf | 234 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ |
efa329cb | 235 | #ifdef CONFIG_FLASH_32MB |
6d0f6bcf | 236 | #define CONFIG_SYS_MAX_FLASH_SECT 135 /* max num of sects on one chip */ |
efa329cb | 237 | #else |
6d0f6bcf | 238 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ |
efa329cb | 239 | #endif |
6d0f6bcf JCPV |
240 | #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ |
241 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ | |
0f8c9768 WD |
242 | |
243 | #if 0 | |
244 | /* Start port with environment in flash; switch to EEPROM later */ | |
5a1aceb0 | 245 | #define CONFIG_ENV_IS_IN_FLASH 1 |
6d0f6bcf | 246 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x40000) |
0e8d1586 JCPV |
247 | #define CONFIG_ENV_SIZE 0x40000 |
248 | #define CONFIG_ENV_SECT_SIZE 0x40000 | |
0f8c9768 WD |
249 | #else |
250 | /* Final version: environment in EEPROM */ | |
bb1f8b4f | 251 | #define CONFIG_ENV_IS_IN_EEPROM 1 |
6d0f6bcf JCPV |
252 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x58 |
253 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
254 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 | |
255 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ | |
0e8d1586 JCPV |
256 | #define CONFIG_ENV_OFFSET 512 |
257 | #define CONFIG_ENV_SIZE (2048 - 512) | |
0f8c9768 WD |
258 | #endif |
259 | ||
260 | /*----------------------------------------------------------------------- | |
261 | * Hard Reset Configuration Words | |
262 | * | |
6d0f6bcf | 263 | * if you change bits in the HRCW, you must also change the CONFIG_SYS_* |
0f8c9768 | 264 | * defines for the various registers affected by the HRCW e.g. changing |
6d0f6bcf | 265 | * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR. |
0f8c9768 WD |
266 | */ |
267 | #if defined(CONFIG_BOOT_ROM) | |
6d0f6bcf | 268 | #define CONFIG_SYS_HRCW_MASTER (HRCW_BPS01 | HRCW_CIP | HRCW_ISB100 | HRCW_BMS) |
0f8c9768 | 269 | #else |
6d0f6bcf | 270 | #define CONFIG_SYS_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS) |
0f8c9768 WD |
271 | #endif |
272 | ||
273 | /* no slaves so just fill with zeros */ | |
6d0f6bcf JCPV |
274 | #define CONFIG_SYS_HRCW_SLAVE1 0 |
275 | #define CONFIG_SYS_HRCW_SLAVE2 0 | |
276 | #define CONFIG_SYS_HRCW_SLAVE3 0 | |
277 | #define CONFIG_SYS_HRCW_SLAVE4 0 | |
278 | #define CONFIG_SYS_HRCW_SLAVE5 0 | |
279 | #define CONFIG_SYS_HRCW_SLAVE6 0 | |
280 | #define CONFIG_SYS_HRCW_SLAVE7 0 | |
0f8c9768 WD |
281 | |
282 | /*----------------------------------------------------------------------- | |
283 | * Internal Memory Mapped Register | |
284 | */ | |
6d0f6bcf | 285 | #define CONFIG_SYS_IMMR 0xF0000000 |
0f8c9768 WD |
286 | |
287 | /*----------------------------------------------------------------------- | |
288 | * Definitions for initial stack pointer and data area (in DPRAM) | |
289 | */ | |
6d0f6bcf | 290 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
553f0982 | 291 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */ |
25ddd1fb | 292 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 293 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
0f8c9768 WD |
294 | |
295 | /*----------------------------------------------------------------------- | |
296 | * Start addresses for the final memory configuration | |
297 | * (Set up by the startup code) | |
6d0f6bcf | 298 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
0f8c9768 | 299 | * |
6d0f6bcf | 300 | * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE, local SDRAM |
0f8c9768 WD |
301 | * is mapped at SDRAM_BASE2_PRELIM. |
302 | */ | |
6d0f6bcf JCPV |
303 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
304 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE | |
14d0a02a | 305 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
6d0f6bcf JCPV |
306 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
307 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ | |
0f8c9768 | 308 | |
6d0f6bcf JCPV |
309 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
310 | # define CONFIG_SYS_RAMBOOT | |
0f8c9768 WD |
311 | #endif |
312 | ||
10f67017 | 313 | #ifdef CONFIG_PCI |
4d75a504 WD |
314 | #define CONFIG_PCI_PNP |
315 | #define CONFIG_EEPRO100 | |
6d0f6bcf | 316 | #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ |
10f67017 | 317 | #endif |
4d75a504 | 318 | |
0f8c9768 WD |
319 | /*----------------------------------------------------------------------- |
320 | * Cache Configuration | |
321 | */ | |
6d0f6bcf | 322 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ |
acf02697 | 323 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 324 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
0f8c9768 WD |
325 | #endif |
326 | ||
327 | /*----------------------------------------------------------------------- | |
328 | * HIDx - Hardware Implementation-dependent Registers 2-11 | |
329 | *----------------------------------------------------------------------- | |
330 | * HID0 also contains cache control - initially enable both caches and | |
331 | * invalidate contents, then the final state leaves only the instruction | |
332 | * cache enabled. Note that Power-On and Hard reset invalidate the caches, | |
333 | * but Soft reset does not. | |
334 | * | |
335 | * HID1 has only read-only information - nothing to set. | |
336 | */ | |
6d0f6bcf | 337 | #define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ |
8bde7f77 | 338 | HID0_IFEM|HID0_ABE) |
6d0f6bcf JCPV |
339 | #define CONFIG_SYS_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE) |
340 | #define CONFIG_SYS_HID2 0 | |
0f8c9768 WD |
341 | |
342 | /*----------------------------------------------------------------------- | |
343 | * RMR - Reset Mode Register 5-5 | |
344 | *----------------------------------------------------------------------- | |
345 | * turn on Checkstop Reset Enable | |
346 | */ | |
6d0f6bcf | 347 | #define CONFIG_SYS_RMR RMR_CSRE |
0f8c9768 WD |
348 | |
349 | /*----------------------------------------------------------------------- | |
350 | * BCR - Bus Configuration 4-25 | |
351 | *----------------------------------------------------------------------- | |
352 | */ | |
353 | ||
354 | #define BCR_APD01 0x10000000 | |
6d0f6bcf | 355 | #define CONFIG_SYS_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */ |
0f8c9768 WD |
356 | |
357 | /*----------------------------------------------------------------------- | |
358 | * SIUMCR - SIU Module Configuration 4-31 | |
359 | *----------------------------------------------------------------------- | |
360 | */ | |
361 | #if 0 | |
6d0f6bcf | 362 | #define CONFIG_SYS_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_CS10PC01) |
0f8c9768 | 363 | #else |
6d0f6bcf | 364 | #define CONFIG_SYS_SIUMCR (SIUMCR_DPPC10|SIUMCR_APPC10) |
0f8c9768 WD |
365 | #endif |
366 | ||
367 | ||
368 | /*----------------------------------------------------------------------- | |
369 | * SYPCR - System Protection Control 4-35 | |
370 | * SYPCR can only be written once after reset! | |
371 | *----------------------------------------------------------------------- | |
372 | * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable | |
373 | */ | |
374 | #if defined(CONFIG_WATCHDOG) | |
6d0f6bcf | 375 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ |
8bde7f77 | 376 | SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) |
0f8c9768 | 377 | #else |
6d0f6bcf | 378 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ |
8bde7f77 | 379 | SYPCR_SWRI|SYPCR_SWP) |
0f8c9768 WD |
380 | #endif /* CONFIG_WATCHDOG */ |
381 | ||
382 | /*----------------------------------------------------------------------- | |
383 | * TMCNTSC - Time Counter Status and Control 4-40 | |
384 | *----------------------------------------------------------------------- | |
385 | * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, | |
386 | * and enable Time Counter | |
387 | */ | |
6d0f6bcf | 388 | #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) |
0f8c9768 WD |
389 | |
390 | /*----------------------------------------------------------------------- | |
391 | * PISCR - Periodic Interrupt Status and Control 4-42 | |
392 | *----------------------------------------------------------------------- | |
393 | * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable | |
394 | * Periodic timer | |
395 | */ | |
6d0f6bcf | 396 | #define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) |
0f8c9768 WD |
397 | |
398 | /*----------------------------------------------------------------------- | |
399 | * SCCR - System Clock Control 9-8 | |
400 | *----------------------------------------------------------------------- | |
401 | */ | |
6d0f6bcf | 402 | #define CONFIG_SYS_SCCR (SCCR_DFBRG00) |
0f8c9768 WD |
403 | |
404 | /*----------------------------------------------------------------------- | |
405 | * RCCR - RISC Controller Configuration 13-7 | |
406 | *----------------------------------------------------------------------- | |
407 | */ | |
6d0f6bcf | 408 | #define CONFIG_SYS_RCCR 0 |
0f8c9768 WD |
409 | |
410 | /* | |
411 | * Init Memory Controller: | |
412 | * | |
413 | * Bank Bus Machine PortSz Device | |
414 | * ---- --- ------- ------ ------ | |
415 | * 0 60x GPCM 64 bit FLASH | |
416 | * 1 60x SDRAM 64 bit SDRAM | |
0f8c9768 WD |
417 | * |
418 | */ | |
419 | ||
420 | /* Initialize SDRAM on local bus | |
421 | */ | |
6d0f6bcf | 422 | #define CONFIG_SYS_INIT_LOCAL_SDRAM |
0f8c9768 WD |
423 | |
424 | ||
425 | /* Minimum mask to separate preliminary | |
426 | * address ranges for CS[0:2] | |
427 | */ | |
6d0f6bcf | 428 | #define CONFIG_SYS_MIN_AM_MASK 0xC0000000 |
0f8c9768 | 429 | |
efa329cb WD |
430 | /* |
431 | * we use the same values for 32 MB and 128 MB SDRAM | |
432 | * refresh rate = 7.73 uS (64 MHz Bus Clock) | |
433 | */ | |
6d0f6bcf JCPV |
434 | #define CONFIG_SYS_MPTPR 0x2000 |
435 | #define CONFIG_SYS_PSRT 0x0E | |
0f8c9768 | 436 | |
6d0f6bcf | 437 | #define CONFIG_SYS_MRS_OFFS 0x00000000 |
0f8c9768 WD |
438 | |
439 | ||
440 | #if defined(CONFIG_BOOT_ROM) | |
441 | /* | |
442 | * Bank 0 - Boot ROM (8 bit wide) | |
443 | */ | |
6d0f6bcf | 444 | #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\ |
0f8c9768 WD |
445 | BRx_PS_8 |\ |
446 | BRx_MS_GPCM_P |\ | |
447 | BRx_V) | |
448 | ||
6d0f6bcf | 449 | #define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE) |\ |
0f8c9768 WD |
450 | ORxG_CSNT |\ |
451 | ORxG_ACS_DIV1 |\ | |
452 | ORxG_SCY_3_CLK |\ | |
453 | ORxG_EHTR |\ | |
454 | ORxG_TRLX) | |
455 | ||
456 | /* | |
457 | * Bank 1 - Flash (64 bit wide) | |
458 | */ | |
6d0f6bcf | 459 | #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ |
0f8c9768 WD |
460 | BRx_PS_64 |\ |
461 | BRx_MS_GPCM_P |\ | |
462 | BRx_V) | |
463 | ||
6d0f6bcf | 464 | #define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ |
0f8c9768 WD |
465 | ORxG_CSNT |\ |
466 | ORxG_ACS_DIV1 |\ | |
467 | ORxG_SCY_3_CLK |\ | |
468 | ORxG_EHTR |\ | |
469 | ORxG_TRLX) | |
470 | ||
471 | #else /* ! CONFIG_BOOT_ROM */ | |
472 | ||
473 | /* | |
474 | * Bank 0 - Flash (64 bit wide) | |
475 | */ | |
6d0f6bcf | 476 | #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ |
8bde7f77 WD |
477 | BRx_PS_64 |\ |
478 | BRx_MS_GPCM_P |\ | |
479 | BRx_V) | |
0f8c9768 | 480 | |
6d0f6bcf | 481 | #define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ |
8bde7f77 WD |
482 | ORxG_CSNT |\ |
483 | ORxG_ACS_DIV1 |\ | |
484 | ORxG_SCY_3_CLK |\ | |
485 | ORxG_EHTR |\ | |
486 | ORxG_TRLX) | |
0f8c9768 WD |
487 | |
488 | /* | |
489 | * Bank 1 - Disk-On-Chip | |
490 | */ | |
6d0f6bcf | 491 | #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_DOC_BASE & BRx_BA_MSK) |\ |
0f8c9768 WD |
492 | BRx_PS_8 |\ |
493 | BRx_MS_GPCM_P |\ | |
494 | BRx_V) | |
495 | ||
6d0f6bcf | 496 | #define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_DOC_SIZE) |\ |
0f8c9768 WD |
497 | ORxG_CSNT |\ |
498 | ORxG_ACS_DIV1 |\ | |
499 | ORxG_SCY_3_CLK |\ | |
500 | ORxG_EHTR |\ | |
501 | ORxG_TRLX) | |
502 | ||
503 | #endif /* CONFIG_BOOT_ROM */ | |
504 | ||
505 | /* Bank 2 - SDRAM | |
506 | */ | |
efa329cb | 507 | |
6d0f6bcf JCPV |
508 | #ifndef CONFIG_SYS_RAMBOOT |
509 | #define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\ | |
8bde7f77 WD |
510 | BRx_PS_64 |\ |
511 | BRx_MS_SDRAM_P |\ | |
512 | BRx_V) | |
0f8c9768 WD |
513 | |
514 | /* SDRAM initialization values for 8-column chips | |
515 | */ | |
6d0f6bcf | 516 | #define CONFIG_SYS_OR2_8COL (CONFIG_SYS_MIN_AM_MASK |\ |
8bde7f77 WD |
517 | ORxS_BPD_4 |\ |
518 | ORxS_ROWST_PBI0_A9 |\ | |
519 | ORxS_NUMR_12) | |
0f8c9768 | 520 | |
6d0f6bcf | 521 | #define CONFIG_SYS_PSDMR_8COL (PSDMR_SDAM_A13_IS_A5 |\ |
8bde7f77 WD |
522 | PSDMR_BSMA_A14_A16 |\ |
523 | PSDMR_SDA10_PBI0_A10 |\ | |
524 | PSDMR_RFRC_7_CLK |\ | |
525 | PSDMR_PRETOACT_2W |\ | |
526 | PSDMR_ACTTORW_1W |\ | |
527 | PSDMR_LDOTOPRE_1C |\ | |
528 | PSDMR_WRC_1C |\ | |
529 | PSDMR_CL_2) | |
0f8c9768 WD |
530 | |
531 | /* SDRAM initialization values for 9-column chips | |
532 | */ | |
6d0f6bcf | 533 | #define CONFIG_SYS_OR2_9COL (CONFIG_SYS_MIN_AM_MASK |\ |
8bde7f77 WD |
534 | ORxS_BPD_4 |\ |
535 | ORxS_ROWST_PBI0_A7 |\ | |
536 | ORxS_NUMR_13) | |
0f8c9768 | 537 | |
6d0f6bcf | 538 | #define CONFIG_SYS_PSDMR_9COL (PSDMR_SDAM_A14_IS_A5 |\ |
8bde7f77 WD |
539 | PSDMR_BSMA_A13_A15 |\ |
540 | PSDMR_SDA10_PBI0_A9 |\ | |
541 | PSDMR_RFRC_7_CLK |\ | |
542 | PSDMR_PRETOACT_2W |\ | |
543 | PSDMR_ACTTORW_1W |\ | |
544 | PSDMR_LDOTOPRE_1C |\ | |
545 | PSDMR_WRC_1C |\ | |
546 | PSDMR_CL_2) | |
0f8c9768 | 547 | |
6d0f6bcf JCPV |
548 | #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2_9COL |
549 | #define CONFIG_SYS_PSDMR CONFIG_SYS_PSDMR_9COL | |
0f8c9768 | 550 | |
6d0f6bcf | 551 | #endif /* CONFIG_SYS_RAMBOOT */ |
0f8c9768 WD |
552 | |
553 | #endif /* __CONFIG_H */ |