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b20d0032 WD |
1 | /* |
2 | * Copyright 2004 Freescale Semiconductor. | |
3 | * (C) Copyright 2002,2003 Motorola,Inc. | |
4 | * Xianghua Xiao <X.Xiao@motorola.com> | |
5 | * | |
6 | * See file CREDITS for list of people who contributed to this | |
7 | * project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | */ | |
24 | ||
25 | /* | |
26 | * MicroSys PM856 board configuration file | |
27 | * | |
28 | * Please refer to doc/README.mpc85xx for more info. | |
29 | * | |
30 | * Make sure you change the MAC address and other network params first, | |
31 | * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. | |
32 | */ | |
33 | ||
34 | #ifndef __CONFIG_H | |
35 | #define __CONFIG_H | |
36 | ||
37 | /* High Level Configuration Options */ | |
38 | #define CONFIG_BOOKE 1 /* BOOKE */ | |
39 | #define CONFIG_E500 1 /* BOOKE e500 family */ | |
40 | #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ | |
41 | #define CONFIG_MPC8560 1 /* MPC8560 specific */ | |
452e8e72 | 42 | #define CONFIG_CPM2 1 /* Has a CPM2 */ |
b20d0032 WD |
43 | #define CONFIG_PM856 1 /* PM856 board specific */ |
44 | ||
45 | #define CONFIG_PCI | |
53677ef1 | 46 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ |
b20d0032 | 47 | #define CONFIG_ENV_OVERWRITE |
b20d0032 | 48 | |
45f2166a | 49 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ |
b20d0032 WD |
50 | |
51 | /* | |
52 | * sysclk for MPC85xx | |
53 | * | |
54 | * Two valid values are: | |
55 | * 33000000 | |
56 | * 66000000 | |
57 | * | |
58 | * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz | |
59 | * is likely the desired value here, so that is now the default. | |
60 | * The board, however, can run at 66MHz. In any event, this value | |
61 | * must match the settings of some switches. Details can be found | |
62 | * in the README.mpc85xxads. | |
63 | */ | |
64 | ||
65 | #ifndef CONFIG_SYS_CLK_FREQ | |
66 | #define CONFIG_SYS_CLK_FREQ 66000000 | |
67 | #endif | |
68 | ||
69 | ||
70 | /* | |
71 | * These can be toggled for performance analysis, otherwise use default. | |
72 | */ | |
73 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
74 | #define CONFIG_BTB /* toggle branch predition */ | |
b20d0032 WD |
75 | |
76 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ | |
77 | ||
6d0f6bcf | 78 | #define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ |
b20d0032 | 79 | |
6d0f6bcf JCPV |
80 | #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ |
81 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ | |
82 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
b20d0032 WD |
83 | |
84 | ||
85 | /* | |
86 | * Base addresses -- Note these are effective addresses where the | |
87 | * actual resources get mapped (not physical addresses) | |
88 | */ | |
6d0f6bcf JCPV |
89 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ |
90 | #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ | |
91 | #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ | |
92 | #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ | |
b20d0032 | 93 | |
6bfa8f72 KG |
94 | /* DDR Setup */ |
95 | #define CONFIG_FSL_DDR1 | |
96 | #undef CONFIG_FSL_DDR_INTERACTIVE | |
97 | #undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ | |
98 | #undef CONFIG_DDR_SPD | |
99 | #define CONFIG_DDR_DLL /* possible DLL fix needed */ | |
100 | #define CONFIG_DDR_ECC /* only for ECC DDR module */ | |
b20d0032 | 101 | |
6bfa8f72 | 102 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef |
b20d0032 | 103 | |
6d0f6bcf JCPV |
104 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 |
105 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
6bfa8f72 KG |
106 | #define CONFIG_VERY_BIG_RAM |
107 | ||
108 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
109 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
110 | #define CONFIG_CHIP_SELECTS_PER_CTRL 2 | |
111 | ||
112 | /* I2C addresses of SPD EEPROMs */ | |
113 | #define SPD_EEPROM_ADDRESS 0x58 /* CTLR 0 DIMM 0 */ | |
114 | ||
115 | /* Manually set up DDR parameters */ | |
6d0f6bcf JCPV |
116 | #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256 MB */ |
117 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f /* 0-256MB */ | |
118 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80000102 | |
119 | #define CONFIG_SYS_DDR_TIMING_1 0x47444321 | |
120 | #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ | |
121 | #define CONFIG_SYS_DDR_CONTROL 0xc2008000 /* unbuffered,no DYN_PWR */ | |
122 | #define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ | |
123 | #define CONFIG_SYS_DDR_INTERVAL 0x045b0100 /* autocharge,no open page */ | |
b20d0032 WD |
124 | |
125 | /* | |
126 | * SDRAM on the Local Bus | |
127 | */ | |
6d0f6bcf JCPV |
128 | #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ |
129 | #define CONFIG_SYS_LBC_SDRAM_SIZE 0 /* LBC SDRAM is 0 MB */ | |
b20d0032 | 130 | |
6d0f6bcf JCPV |
131 | #define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */ |
132 | #define CONFIG_SYS_BR0_PRELIM 0xfe001801 /* port size 32bit */ | |
b20d0032 | 133 | |
6d0f6bcf JCPV |
134 | #define CONFIG_SYS_OR0_PRELIM 0xfe006f67 /* 32MB Flash */ |
135 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
136 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ | |
137 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
138 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
139 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
b20d0032 | 140 | |
6d0f6bcf | 141 | #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ |
b20d0032 | 142 | |
6d0f6bcf JCPV |
143 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
144 | #define CONFIG_SYS_RAMBOOT | |
b20d0032 | 145 | #else |
6d0f6bcf | 146 | #undef CONFIG_SYS_RAMBOOT |
b20d0032 WD |
147 | #endif |
148 | ||
00b1883a | 149 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf JCPV |
150 | #define CONFIG_SYS_FLASH_CFI |
151 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
b20d0032 WD |
152 | |
153 | #undef CONFIG_CLOCKS_IN_MHZ | |
154 | ||
155 | ||
156 | /* | |
157 | * Local Bus Definitions | |
158 | */ | |
159 | ||
6d0f6bcf JCPV |
160 | #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ |
161 | #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ | |
162 | #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ | |
163 | #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ | |
b20d0032 WD |
164 | |
165 | ||
6d0f6bcf JCPV |
166 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
167 | #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ | |
168 | #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ | |
b20d0032 | 169 | |
6d0f6bcf JCPV |
170 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ |
171 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
172 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
b20d0032 | 173 | |
6d0f6bcf JCPV |
174 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ |
175 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ | |
b20d0032 WD |
176 | |
177 | /* Serial Port */ | |
178 | #define CONFIG_CONS_ON_SCC /* define if console on SCC */ | |
179 | #undef CONFIG_CONS_NONE /* define if console on something else */ | |
180 | #define CONFIG_CONS_INDEX 1 /* which serial channel for console */ | |
181 | ||
6d0f6bcf | 182 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
b20d0032 WD |
183 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
184 | ||
185 | /* Use the HUSH parser */ | |
6d0f6bcf JCPV |
186 | #define CONFIG_SYS_HUSH_PARSER |
187 | #ifdef CONFIG_SYS_HUSH_PARSER | |
188 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
b20d0032 WD |
189 | #endif |
190 | ||
20476726 JL |
191 | /* |
192 | * I2C | |
193 | */ | |
194 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
195 | #define CONFIG_HARD_I2C /* I2C with hardware support*/ | |
b20d0032 | 196 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
6d0f6bcf JCPV |
197 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
198 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
199 | #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ | |
200 | #define CONFIG_SYS_I2C_OFFSET 0x3000 | |
b20d0032 WD |
201 | |
202 | /* | |
203 | * EEPROM configuration | |
204 | */ | |
6d0f6bcf JCPV |
205 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x58 |
206 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
207 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 | |
208 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 | |
b20d0032 WD |
209 | |
210 | /* | |
211 | * RTC configuration | |
212 | */ | |
213 | #define CONFIG_RTC_PCF8563 | |
6d0f6bcf | 214 | #define CONFIG_SYS_I2C_RTC_ADDR 0x51 |
b20d0032 WD |
215 | |
216 | /* RapidIO MMU */ | |
6d0f6bcf JCPV |
217 | #define CONFIG_SYS_RIO_MEM_BASE 0xc0000000 /* base address */ |
218 | #define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE | |
219 | #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ | |
b20d0032 WD |
220 | |
221 | /* | |
222 | * General PCI | |
223 | * Addresses are mapped 1-1. | |
224 | */ | |
6d0f6bcf JCPV |
225 | #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 |
226 | #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE | |
227 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ | |
228 | #define CONFIG_SYS_PCI1_IO_BASE 0xe2000000 | |
229 | #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE | |
230 | #define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */ | |
b20d0032 WD |
231 | |
232 | #if defined(CONFIG_PCI) | |
233 | ||
234 | #define CONFIG_NET_MULTI | |
53677ef1 | 235 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
b20d0032 WD |
236 | |
237 | #undef CONFIG_EEPRO100 | |
238 | #undef CONFIG_TULIP | |
239 | ||
240 | #if !defined(CONFIG_PCI_PNP) | |
241 | #define PCI_ENET0_IOADDR 0xe0000000 | |
242 | #define PCI_ENET0_MEMADDR 0xe0000000 | |
53677ef1 | 243 | #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ |
b20d0032 WD |
244 | #endif |
245 | ||
246 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
6d0f6bcf | 247 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ |
b20d0032 WD |
248 | |
249 | #endif /* CONFIG_PCI */ | |
250 | ||
251 | ||
252 | #if defined(CONFIG_TSEC_ENET) | |
253 | ||
254 | #ifndef CONFIG_NET_MULTI | |
53677ef1 | 255 | #define CONFIG_NET_MULTI 1 |
b20d0032 WD |
256 | #endif |
257 | ||
258 | #define CONFIG_MII 1 /* MII PHY management */ | |
255a3577 KP |
259 | #define CONFIG_TSEC1 1 |
260 | #define CONFIG_TSEC1_NAME "TSEC0" | |
261 | #define CONFIG_TSEC2 1 | |
262 | #define CONFIG_TSEC2_NAME "TSEC1" | |
b20d0032 WD |
263 | #define TSEC1_PHY_ADDR 0 |
264 | #define TSEC2_PHY_ADDR 1 | |
265 | #define TSEC1_PHYIDX 0 | |
266 | #define TSEC2_PHYIDX 0 | |
3a79013e AF |
267 | #define TSEC1_FLAGS TSEC_GIGABIT |
268 | #define TSEC2_FLAGS TSEC_GIGABIT | |
b20d0032 WD |
269 | |
270 | #endif /* CONFIG_TSEC_ENET */ | |
271 | ||
452e8e72 | 272 | #define CONFIG_ETHPRIME "TSEC0" |
b20d0032 WD |
273 | |
274 | #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ | |
275 | #undef CONFIG_ETHER_NONE /* define if ether on something else */ | |
276 | ||
277 | ||
278 | /* | |
279 | * - Rx-CLK is CLK15 | |
280 | * - Tx-CLK is CLK14 | |
281 | * - Select bus for bd/buffers | |
282 | * - Full duplex | |
283 | */ | |
284 | #define CONFIG_ETHER_ON_FCC3 | |
6d0f6bcf JCPV |
285 | #define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK) |
286 | #define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK14) | |
287 | #define CONFIG_SYS_CPMFCR_RAMTYPE 0 | |
288 | #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE) | |
b20d0032 WD |
289 | |
290 | /* | |
291 | * Environment | |
292 | */ | |
6d0f6bcf | 293 | #ifndef CONFIG_SYS_RAMBOOT |
5a1aceb0 | 294 | #define CONFIG_ENV_IS_IN_FLASH 1 |
6d0f6bcf | 295 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x80000) |
0e8d1586 JCPV |
296 | #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ |
297 | #define CONFIG_ENV_SIZE 0x2000 | |
b20d0032 | 298 | #else |
6d0f6bcf | 299 | #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ |
93f6d725 | 300 | #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
6d0f6bcf | 301 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
0e8d1586 | 302 | #define CONFIG_ENV_SIZE 0x2000 |
b20d0032 WD |
303 | #endif |
304 | ||
305 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 306 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
b20d0032 | 307 | |
2835e518 | 308 | |
a1aa0bb5 JL |
309 | /* |
310 | * BOOTP options | |
311 | */ | |
312 | #define CONFIG_BOOTP_BOOTFILESIZE | |
313 | #define CONFIG_BOOTP_BOOTPATH | |
314 | #define CONFIG_BOOTP_GATEWAY | |
315 | #define CONFIG_BOOTP_HOSTNAME | |
316 | ||
317 | ||
2835e518 JL |
318 | /* |
319 | * Command line configuration. | |
320 | */ | |
321 | #include <config_cmd_default.h> | |
322 | ||
323 | #define CONFIG_CMD_PING | |
324 | #define CONFIG_CMD_I2C | |
325 | #define CONFIG_CMD_DATE | |
326 | #define CONFIG_CMD_EEPROM | |
327 | ||
328 | #if defined(CONFIG_PCI) | |
329 | #define CONFIG_CMD_PCI | |
330 | #endif | |
331 | ||
6d0f6bcf | 332 | #if defined(CONFIG_SYS_RAMBOOT) |
bdab39d3 | 333 | #undef CONFIG_CMD_SAVEENV |
2835e518 | 334 | #undef CONFIG_CMD_LOADS |
b20d0032 WD |
335 | #endif |
336 | ||
b20d0032 WD |
337 | |
338 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
339 | ||
340 | /* | |
341 | * Miscellaneous configurable options | |
342 | */ | |
6d0f6bcf JCPV |
343 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
344 | #define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */ | |
345 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
b20d0032 | 346 | |
2835e518 | 347 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 348 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
b20d0032 | 349 | #else |
6d0f6bcf | 350 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
b20d0032 WD |
351 | #endif |
352 | ||
6d0f6bcf JCPV |
353 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
354 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
355 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
356 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ | |
b20d0032 WD |
357 | #define CONFIG_LOOPW |
358 | ||
359 | /* | |
360 | * For booting Linux, the board info and command line data | |
361 | * have to be in the first 8 MB of memory, since this is | |
362 | * the maximum mapped by the Linux kernel during initialization. | |
363 | */ | |
6d0f6bcf | 364 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ |
b20d0032 | 365 | |
b20d0032 WD |
366 | /* |
367 | * Internal Definitions | |
368 | * | |
369 | * Boot Flags | |
370 | */ | |
371 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
372 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
373 | ||
2835e518 | 374 | #if defined(CONFIG_CMD_KGDB) |
b20d0032 WD |
375 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
376 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
377 | #endif | |
378 | ||
379 | ||
380 | /* | |
381 | * Environment Configuration | |
382 | */ | |
383 | ||
384 | /* The mac addresses for all ethernet interface */ | |
385 | #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) | |
10327dc5 | 386 | #define CONFIG_HAS_ETH0 |
b20d0032 WD |
387 | #define CONFIG_ETHADDR 00:40:42:01:00:00 |
388 | #define CONFIG_HAS_ETH1 | |
389 | #define CONFIG_ETH1ADDR 00:40:42:01:00:01 | |
390 | #define CONFIG_HAS_ETH2 | |
391 | #define CONFIG_ETH2ADDR 00:40:42:01:00:02 | |
392 | #endif | |
393 | ||
394 | ||
395 | #define CONFIG_ROOTPATH /opt/eldk/ppc_85xx | |
396 | #define CONFIG_BOOTFILE pm856/uImage | |
397 | ||
398 | #define CONFIG_HOSTNAME pm856 | |
399 | #define CONFIG_IPADDR 192.168.0.103 | |
400 | #define CONFIG_SERVERIP 192.168.0.64 | |
401 | #define CONFIG_GATEWAYIP 192.168.0.1 | |
402 | #define CONFIG_NETMASK 255.255.255.0 | |
403 | ||
404 | #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ | |
405 | ||
406 | #define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ | |
407 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ | |
408 | ||
409 | #define CONFIG_BAUDRATE 9600 | |
410 | ||
411 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
412 | "netdev=eth0\0" \ | |
413 | "consoledev=ttyS0\0" \ | |
414 | "ramdiskaddr=400000\0" \ | |
415 | "ramdiskfile=pm856/uRamdisk\0" | |
416 | ||
417 | #define CONFIG_NFSBOOTCOMMAND \ | |
418 | "setenv bootargs root=/dev/nfs rw " \ | |
419 | "nfsroot=$serverip:$rootpath " \ | |
420 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
421 | "console=$consoledev,$baudrate $othbootargs;" \ | |
422 | "tftp $loadaddr $bootfile;" \ | |
423 | "bootm $loadaddr" | |
424 | ||
425 | #define CONFIG_RAMBOOTCOMMAND \ | |
426 | "setenv bootargs root=/dev/ram rw " \ | |
427 | "console=$consoledev,$baudrate $othbootargs;" \ | |
428 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
429 | "tftp $loadaddr $bootfile;" \ | |
430 | "bootm $loadaddr $ramdiskaddr" | |
431 | ||
432 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND | |
433 | ||
434 | #endif /* __CONFIG_H */ |