[people/ms/u-boot.git] / include / configs / PMC405DE.h

/*
 * (C) Copyright 2009
 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd.eu
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
#define CONFIG_PMC405DE		1	/* ...on a PMC405DE board	*/

#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
#define CONFIG_DISPLAY_BOARDINFO

#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
#define CONFIG_BOARD_TYPES	1	/* support board types		*/

#define CONFIG_SYS_CLK_FREQ	33330000 /* external frequency to pll	*/

#define CONFIG_BAUDRATE		115200

#undef  CONFIG_BOOTARGS
#undef  CONFIG_BOOTCOMMAND

#define CONFIG_PREBOOT			/* enable preboot variable	*/

#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change*/

#define CONFIG_HAS_ETH1

#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII		1	/* MII PHY management		*/
#define CONFIG_PHY_ADDR		1	/* PHY address			*/
#define CONFIG_PHY1_ADDR	2	/* 2nd PHY address		*/

#define CONFIG_SYS_RX_ETH_BUFFER	16 /* use 16 rx buffer on 405 emac */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME

/*
 * Command line configuration.
 */
#define CONFIG_CMD_BSP
#define CONFIG_CMD_CHIP_CONFIG
#define CONFIG_CMD_DATE
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_PCI

#undef  CONFIG_WATCHDOG			/* watchdog disabled */
#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0 */
#define CONFIG_PRAM		0

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP

#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */

#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device */
#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console info */

#define CONFIG_SYS_MEMTEST_START	0x0100000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x3000000 /* 1 ... 48 MB in DRAM */

#define CONFIG_CONS_INDEX	2	/* Use UART1			*/
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_serial_clock()

#undef  CONFIG_SYS_EXT_SERIAL_CLOCK
#define CONFIG_SYS_BASE_BAUD		691200

#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
#define CONFIG_SYS_EXTBDINFO	1	/* To use extended board_into (bd_t) */

#define CONFIG_CMDLINE_EDITING	1	/* add command line history     */
#define CONFIG_MX_CYCLIC	1	/* enable mdc/mwc commands      */
#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */

/*
 * PCI stuff
 */
#define PCI_HOST_ADAPTER	0	/* configure as pci adapter	*/
#define PCI_HOST_FORCE		1	/* configure as pci host	*/
#define PCI_HOST_AUTO		2	/* detected via arbiter enable	*/

#define CONFIG_PCI		/* include pci support			*/
#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
#define CONFIG_PCI_HOST	PCI_HOST_AUTO  /* select pci host function	*/
#define CONFIG_PCI_PNP		/* do (not) pci plug-and-play		*/

#define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup		*/

/*
 * PCI identification
 */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID		PCI_VENDOR_ID_ESDGMBH
#define CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH 0x040e /* Dev ID: Non-Monarch */
#define CONFIG_SYS_PCI_SUBSYS_ID_MONARCH 0x040f	/* Dev ID: Monarch */
#define CONFIG_SYS_PCI_CLASSCODE_NONMONARCH	PCI_CLASS_PROCESSOR_POWERPC
#define CONFIG_SYS_PCI_CLASSCODE_MONARCH	PCI_CLASS_BRIDGE_HOST

#define CONFIG_SYS_PCI_CLASSCODE CONFIG_SYS_PCI_CLASSCODE_MONARCH
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID CONFIG_SYS_PCI_SUBSYS_ID_MONARCH

#define CONFIG_SYS_PCI_PTM1LA  0x00000000      /* point to sdram */
#define CONFIG_SYS_PCI_PTM1MS  0xfc000001      /* 64MB, enable=1 */
#define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address */
#define CONFIG_SYS_PCI_PTM2LA  0xef000000      /* point to CPLD, GPIO */
#define CONFIG_SYS_PCI_PTM2MS  0xff000001      /* 16MB, enable=1 */
#define CONFIG_SYS_PCI_PTM2PCI 0x04000000      /* Host: use this pci address */

#define CONFIG_PCI_4xx_PTM_OVERWRITE	1 /* overwrite PTMx settings by env */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)
/*
 * FLASH organization
 */
#define CONFIG_SYS_FLASH_CFI		1	/* CFI compatible */
#define CONFIG_FLASH_CFI_DRIVER		1	/* Use common CFI driver */

#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }

#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max. no. memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max sectors per chip */

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* erase timeout (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* write timeout (in ms) */

#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* buffered writes (faster) */
#define CONFIG_SYS_FLASH_PROTECTION	1	/* hardware flash protection */

#define CONFIG_SYS_FLASH_EMPTY_INFO	1 /* 'E' for empty sector (flinfo) */
#define CONFIG_SYS_FLASH_QUIET_TEST	1 /* don't warn upon unknown flash */

/*
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH_BASE		0xfe000000
#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN		(~(CONFIG_SYS_TEXT_BASE) + 1)
#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)

/*
 * Environment in EEPROM setup
 */
#define CONFIG_ENV_IS_IN_EEPROM		1
#define CONFIG_ENV_OFFSET		0x100
#define CONFIG_ENV_SIZE			0x700

/*
 * I2C EEPROM (24W16) for environment
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_PPC4XX
#define CONFIG_SYS_I2C_PPC4XX_CH0
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F

#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM 24W16	*/
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address */
/* mask of address bits that overflow into the "EEPROM chip address" */
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has */
					/* 16 byte page write mode using*/
					/* last 4 bits of the address */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10 /* and takes up to 10 msec */
#define CONFIG_SYS_EEPROM_WREN		1

#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR	0x50
#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET	0x40
#define CONFIG_4xx_CONFIG_BLOCKSIZE		0x20

/*
 * RTC
 */
#define CONFIG_RTC_RX8025

/*
 * External Bus Controller (EBC) Setup
 * (max. 55MHZ EBC clock)
 */
/* Memory Bank 0 (NOR flash) BAS=0xFE0,BS=32MB,BU=R/W,BW=16bit */
#define CONFIG_SYS_EBC_PB0AP		0x03017200
#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_FLASH_BASE | 0xba000)

/* Memory Bank 1 (CPLD) BAS=0xEF0,BS=16MB,BU=R/W,BW=16bit */
#define CONFIG_SYS_CPLD_BASE		0xef000000
#define CONFIG_SYS_EBC_PB1AP		0x00800000
#define CONFIG_SYS_EBC_PB1CR		(CONFIG_SYS_CPLD_BASE | 0x18000)

/*
 * Definitions for initial stack pointer and data area (in data cache)
 */
/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
#define CONFIG_SYS_TEMP_STACK_OCM	  1

/* On Chip Memory location */
#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
/* inside SDRAM */
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR
/* End of used area in RAM */
#define CONFIG_SYS_INIT_RAM_SIZE		CONFIG_SYS_OCM_DATA_SIZE

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
					 GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*
 * GPIO Configuration
 */
#define CONFIG_SYS_4xx_GPIO_TABLE {                  /* GPIO    Alt1       */ \
{                                                                             \
/* GPIO Core 0 */                                                             \
{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO0   PerBLast   */ \
{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO1   TS1E       */ \
{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO2   TS2E       */ \
{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO3   TS1O       */ \
{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO4   TS2O       */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1 },      /* GPIO5   TS3        */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1 },      /* GPIO6   TS4        */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1 },      /* GPIO7   TS5        */ \
{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO8   TS6        */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1 },      /* GPIO9   TrcClk     */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10  PerCS1     */ \
{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO11  PerCS2     */ \
{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO12  PerCS3     */ \
{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO13  PerCS4     */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO14  PerAddr03  */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO15  PerAddr04  */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16  PerAddr05  */ \
{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17  IRQ0       */ \
{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18  IRQ1       */ \
{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19  IRQ2       */ \
{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO20  IRQ3       */ \
{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO21  IRQ4       */ \
{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO22  IRQ5       */ \
{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO23  IRQ6       */ \
{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24  UART0_DCD  */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO25  UART0_DSR  */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO26  UART0_RI   */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO27  UART0_DTR  */ \
{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28  UART1_Rx   */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29  UART1_Tx   */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO30  RejectPkt0 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO31  RejectPkt1 */ \
}                                                                             \
}

#define CONFIG_SYS_GPIO_HWREV_MASK	(0xf0000000 >> 1)	/* GPIO1..4 */
#define CONFIG_SYS_GPIO_HWREV_SHIFT	27
#define CONFIG_SYS_GPIO_LEDRUN_N	(0x80000000 >> 5)	/* GPIO5 */
#define CONFIG_SYS_GPIO_LEDA_N		(0x80000000 >> 6)	/* GPIO6 */
#define CONFIG_SYS_GPIO_LEDB_N		(0x80000000 >> 7)	/* GPIO7 */
#define CONFIG_SYS_GPIO_SELFRST_N	(0x80000000 >> 8)	/* GPIO8 */
#define CONFIG_SYS_GPIO_EEPROM_WP	(0x80000000 >> 9)	/* GPIO9 */
#define CONFIG_SYS_GPIO_MONARCH_N	(0x80000000 >> 11)	/* GPIO11 */
#define CONFIG_SYS_GPIO_EREADY		(0x80000000 >> 12)	/* GPIO12 */
#define CONFIG_SYS_GPIO_M66EN		(0x80000000 >> 13)	/* GPIO13 */

/*
 * Default speed selection (cpu_plb_opb_ebc) in mhz.
 * This value will be set if iic boot eprom is disabled.
 */
#undef CONFIG_SYS_FCPU333MHZ
#define CONFIG_SYS_FCPU266MHZ
#undef CONFIG_SYS_FCPU133MHZ

#if defined(CONFIG_SYS_FCPU333MHZ)
/*
 * CPU: 333MHz
 * PLB/SDRAM/MAL: 111MHz
 * OPB: 55MHz
 * EBC: 55MHz
 * PCI: 55MHz (111MHz on M66EN=1)
 */
#define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_3 |		\
			PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 |	\
			PLL_MALDIV_1 | PLL_PCIDIV_2)
#define PLLMR1_DEFAULT (PLL_FBKDIV_10  |			\
			PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |		\
			PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
#endif

#if defined(CONFIG_SYS_FCPU266MHZ)
/*
 * CPU: 266MHz
 * PLB/SDRAM/MAL: 133MHz
 * OPB: 66MHz
 * EBC: 44MHz
 * PCI: 44MHz (66MHz on M66EN=1)
 */
#define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_2 |		\
			PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |	\
			PLL_MALDIV_1 | PLL_PCIDIV_3)
#define PLLMR1_DEFAULT (PLL_FBKDIV_8  |  \
			PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |		\
			PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
#endif

#if defined(CONFIG_SYS_FCPU133MHZ)
/*
 * CPU: 133MHz
 * PLB/SDRAM/MAL: 133MHz
 * OPB: 66MHz
 * EBC: 44MHz
 * PCI: 44MHz (66MHz on M66EN=1)
 */
#define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_1 |		\
			PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |	\
			PLL_MALDIV_1 | PLL_PCIDIV_3)
#define PLLMR1_DEFAULT (PLL_FBKDIV_4  |  \
			PLL_FWDDIVA_6 | PLL_FWDDIVB_6 |		\
			PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
#endif

#endif /* __CONFIG_H */
Commit	Line	Data
99d8b23b MF	1	/*
	2	* (C) Copyright 2009
	3	* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd.eu
	4	*
3765b3e7	5	* SPDX-License-Identifier: GPL-2.0+
99d8b23b MF	6	*/
	7
	8	#ifndef __CONFIG_H
	9	#define __CONFIG_H
	10
	11	#define CONFIG_405EP 1 /* This is a PPC405 CPU */
99d8b23b MF	12	#define CONFIG_PMC405DE 1 /* ...on a PMC405DE board */
99d8b23b MF	13
2ae18241	14	#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
34830356	15	#define CONFIG_DISPLAY_BOARDINFO
2ae18241	16
99d8b23b MF	17	#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
	18	#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
	19	#define CONFIG_BOARD_TYPES 1 /* support board types */
	20
	21	#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
	22
	23	#define CONFIG_BAUDRATE 115200
99d8b23b MF	24
	25	#undef CONFIG_BOOTARGS
	26	#undef CONFIG_BOOTCOMMAND
	27
	28	#define CONFIG_PREBOOT /* enable preboot variable */
	29
	30	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change*/
	31
99d8b23b MF	32	#define CONFIG_HAS_ETH1
	33
	34	#define CONFIG_PPC4xx_EMAC
	35	#define CONFIG_MII 1 /* MII PHY management */
	36	#define CONFIG_PHY_ADDR 1 /* PHY address */
	37	#define CONFIG_PHY1_ADDR 2 /* 2nd PHY address */
	38
	39	#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
	40
	41	/*
	42	* BOOTP options
	43	*/
	44	#define CONFIG_BOOTP_SUBNETMASK
	45	#define CONFIG_BOOTP_GATEWAY
	46	#define CONFIG_BOOTP_HOSTNAME
	47	#define CONFIG_BOOTP_BOOTPATH
	48	#define CONFIG_BOOTP_DNS
	49	#define CONFIG_BOOTP_DNS2
	50	#define CONFIG_BOOTP_SEND_HOSTNAME
	51
	52	/*
	53	* Command line configuration.
	54	*/
99d8b23b MF	55	#define CONFIG_CMD_BSP
	56	#define CONFIG_CMD_CHIP_CONFIG
	57	#define CONFIG_CMD_DATE
99d8b23b	58	#define CONFIG_CMD_EEPROM
99d8b23b	59	#define CONFIG_CMD_IRQ
99d8b23b	60	#define CONFIG_CMD_PCI
99d8b23b	61
99d8b23b MF	62	#undef CONFIG_WATCHDOG /* watchdog disabled */
	63	#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
	64	#define CONFIG_PRAM 0
	65
	66	/*
	67	* Miscellaneous configurable options
	68	*/
	69	#define CONFIG_SYS_LONGHELP
99d8b23b MF	70
	71	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	72	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	73	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	74	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
	75
	76	#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
	77	#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console info */
	78
	79	#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
	80	#define CONFIG_SYS_MEMTEST_END 0x3000000 /* 1 ... 48 MB in DRAM */
	81
550650dd	82	#define CONFIG_CONS_INDEX 2 /* Use UART1 */
550650dd SR	83	#define CONFIG_SYS_NS16550_SERIAL
	84	#define CONFIG_SYS_NS16550_REG_SIZE 1
	85	#define CONFIG_SYS_NS16550_CLK get_serial_clock()
	86
99d8b23b MF	87	#undef CONFIG_SYS_EXT_SERIAL_CLOCK
99d8b23b MF	88	#define CONFIG_SYS_BASE_BAUD 691200
99d8b23b	89
99d8b23b MF	90	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
	91	#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
	92
99d8b23b	93	#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
99d8b23b	94	#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
99d8b23b MF	95	#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
99d8b23b MF	96
99d8b23b MF	97	/*
	98	* PCI stuff
	99	*/
	100	#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
	101	#define PCI_HOST_FORCE 1 /* configure as pci host */
	102	#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
	103
	104	#define CONFIG_PCI /* include pci support */
842033e6	105	#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
99d8b23b MF	106	#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
	107	#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */
	108
	109	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
	110
	111	/*
	112	* PCI identification
	113	*/
	114	#define CONFIG_SYS_PCI_SUBSYS_VENDORID PCI_VENDOR_ID_ESDGMBH
	115	#define CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH 0x040e /* Dev ID: Non-Monarch */
	116	#define CONFIG_SYS_PCI_SUBSYS_ID_MONARCH 0x040f /* Dev ID: Monarch */
	117	#define CONFIG_SYS_PCI_CLASSCODE_NONMONARCH PCI_CLASS_PROCESSOR_POWERPC
	118	#define CONFIG_SYS_PCI_CLASSCODE_MONARCH PCI_CLASS_BRIDGE_HOST
	119
	120	#define CONFIG_SYS_PCI_CLASSCODE CONFIG_SYS_PCI_CLASSCODE_MONARCH
	121	#define CONFIG_SYS_PCI_SUBSYS_DEVICEID CONFIG_SYS_PCI_SUBSYS_ID_MONARCH
	122
	123	#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
	124	#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable=1 */
	125	#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
	126	#define CONFIG_SYS_PCI_PTM2LA 0xef000000 /* point to CPLD, GPIO */
	127	#define CONFIG_SYS_PCI_PTM2MS 0xff000001 /* 16MB, enable=1 */
	128	#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
	129
82379b55 MF	130	#define CONFIG_PCI_4xx_PTM_OVERWRITE 1 /* overwrite PTMx settings by env */
82379b55 MF	131
99d8b23b MF	132	/*
	133	* For booting Linux, the board info and command line data
	134	* have to be in the first 8 MB of memory, since this is
	135	* the maximum mapped by the Linux kernel during initialization.
	136	*/
	137	#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
	138	/*
	139	* FLASH organization
	140	*/
	141	#define CONFIG_SYS_FLASH_CFI 1 /* CFI compatible */
	142	#define CONFIG_FLASH_CFI_DRIVER 1 /* Use common CFI driver */
	143
	144	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
	145
	146	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max. no. memory banks */
	147	#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per chip */
	148
	149	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* erase timeout (in ms) */
	150	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* write timeout (in ms) */
	151
	152	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* buffered writes (faster) */
	153	#define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware flash protection */
	154
	155	#define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* 'E' for empty sector (flinfo) */
	156	#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
	157
99d8b23b MF	158	/*
	159	* Start addresses for the final memory configuration
	160	* (Set up by the startup code)
	161	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
	162	*/
	163	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	164	#define CONFIG_SYS_FLASH_BASE 0xfe000000
14d0a02a WD	165	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
14d0a02a WD	166	#define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1)
99d8b23b MF	167	#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
	168
	169	/*
	170	* Environment in EEPROM setup
	171	*/
	172	#define CONFIG_ENV_IS_IN_EEPROM 1
	173	#define CONFIG_ENV_OFFSET 0x100
	174	#define CONFIG_ENV_SIZE 0x700
	175
	176	/*
	177	* I2C EEPROM (24W16) for environment
	178	*/
880540de DE	179	#define CONFIG_SYS_I2C
	180	#define CONFIG_SYS_I2C_PPC4XX
	181	#define CONFIG_SYS_I2C_PPC4XX_CH0
	182	#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
	183	#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
99d8b23b MF	184
	185	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM 24W16 */
	186	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
	187	/* mask of address bits that overflow into the "EEPROM chip address" */
	188	#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
	189	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
	190	/* 16 byte page write mode using*/
	191	/* last 4 bits of the address */
	192	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
	193	#define CONFIG_SYS_EEPROM_WREN 1
	194
	195	#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x50
	196	#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0x40
	197	#define CONFIG_4xx_CONFIG_BLOCKSIZE 0x20
	198
	199	/*
	200	* RTC
	201	*/
	202	#define CONFIG_RTC_RX8025
	203
	204	/*
	205	* External Bus Controller (EBC) Setup
	206	* (max. 55MHZ EBC clock)
	207	*/
	208	/* Memory Bank 0 (NOR flash) BAS=0xFE0,BS=32MB,BU=R/W,BW=16bit */
	209	#define CONFIG_SYS_EBC_PB0AP 0x03017200
	210	#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH_BASE \| 0xba000)
	211
	212	/* Memory Bank 1 (CPLD) BAS=0xEF0,BS=16MB,BU=R/W,BW=16bit */
	213	#define CONFIG_SYS_CPLD_BASE 0xef000000
	214	#define CONFIG_SYS_EBC_PB1AP 0x00800000
	215	#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_CPLD_BASE \| 0x18000)
	216
	217	/*
	218	* Definitions for initial stack pointer and data area (in data cache)
	219	*/
	220	/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
	221	#define CONFIG_SYS_TEMP_STACK_OCM 1
	222
	223	/* On Chip Memory location */
	224	#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
	225	#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
	226	/* inside SDRAM */
	227	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR
	228	/* End of used area in RAM */
553f0982	229	#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE
99d8b23b	230
553f0982	231	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
25ddd1fb	232	GENERATED_GBL_DATA_SIZE)
99d8b23b MF	233	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
	234
	235	/*
	236	* GPIO Configuration
	237	*/
	238	#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alt1 */ \
	239	{ \
	240	/* GPIO Core 0 */ \
	241	{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
	242	{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
	243	{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
	244	{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
	245	{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
	246	{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \
	247	{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO6 TS4 */ \
	248	{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO7 TS5 */ \
	249	{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
	250	{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO9 TrcClk */ \
	251	{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
	252	{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
	253	{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
	254	{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
	255	{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
	256	{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
	257	{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
	258	{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
	259	{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
	260	{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
	261	{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
	262	{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
	263	{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
	264	{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
	265	{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
	266	{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
	267	{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
	268	{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
	269	{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
	270	{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
	271	{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
	272	{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
	273	} \
	274	}
	275
	276	#define CONFIG_SYS_GPIO_HWREV_MASK (0xf0000000 >> 1) /* GPIO1..4 */
	277	#define CONFIG_SYS_GPIO_HWREV_SHIFT 27
	278	#define CONFIG_SYS_GPIO_LEDRUN_N (0x80000000 >> 5) /* GPIO5 */
	279	#define CONFIG_SYS_GPIO_LEDA_N (0x80000000 >> 6) /* GPIO6 */
	280	#define CONFIG_SYS_GPIO_LEDB_N (0x80000000 >> 7) /* GPIO7 */
	281	#define CONFIG_SYS_GPIO_SELFRST_N (0x80000000 >> 8) /* GPIO8 */
	282	#define CONFIG_SYS_GPIO_EEPROM_WP (0x80000000 >> 9) /* GPIO9 */
	283	#define CONFIG_SYS_GPIO_MONARCH_N (0x80000000 >> 11) /* GPIO11 */
	284	#define CONFIG_SYS_GPIO_EREADY (0x80000000 >> 12) /* GPIO12 */
	285	#define CONFIG_SYS_GPIO_M66EN (0x80000000 >> 13) /* GPIO13 */
	286
	287	/*
	288	* Default speed selection (cpu_plb_opb_ebc) in mhz.
	289	* This value will be set if iic boot eprom is disabled.
	290	*/
	291	#undef CONFIG_SYS_FCPU333MHZ
	292	#define CONFIG_SYS_FCPU266MHZ
	293	#undef CONFIG_SYS_FCPU133MHZ
	294
	295	#if defined(CONFIG_SYS_FCPU333MHZ)
	296	/*
297	* CPU: 333MHz
298	* PLB/SDRAM/MAL: 111MHz
299	* OPB: 55MHz
300	* EBC: 55MHz
301	* PCI: 55MHz (111MHz on M66EN=1)
302	*/
303	#define PLLMR0_DEFAULT (PLL_CPUDIV_1 \| PLL_PLBDIV_3 \| \
304	PLL_OPBDIV_2 \| PLL_EXTBUSDIV_2 \| \
305	PLL_MALDIV_1 \| PLL_PCIDIV_2)
306	#define PLLMR1_DEFAULT (PLL_FBKDIV_10 \| \
307	PLL_FWDDIVA_3 \| PLL_FWDDIVB_3 \| \
308	PLL_TUNE_15_M_40 \| PLL_TUNE_VCO_HI)
309	#endif
310
311	#if defined(CONFIG_SYS_FCPU266MHZ)
312	/*
313	* CPU: 266MHz
314	* PLB/SDRAM/MAL: 133MHz
315	* OPB: 66MHz
316	* EBC: 44MHz
317	* PCI: 44MHz (66MHz on M66EN=1)
318	*/
319	#define PLLMR0_DEFAULT (PLL_CPUDIV_1 \| PLL_PLBDIV_2 \| \
320	PLL_OPBDIV_2 \| PLL_EXTBUSDIV_3 \| \
321	PLL_MALDIV_1 \| PLL_PCIDIV_3)
322	#define PLLMR1_DEFAULT (PLL_FBKDIV_8 \| \
323	PLL_FWDDIVA_3 \| PLL_FWDDIVB_3 \| \
324	PLL_TUNE_15_M_40 \| PLL_TUNE_VCO_LOW)
325	#endif
326
327	#if defined(CONFIG_SYS_FCPU133MHZ)
328	/*
329	* CPU: 133MHz
330	* PLB/SDRAM/MAL: 133MHz
331	* OPB: 66MHz
332	* EBC: 44MHz
333	* PCI: 44MHz (66MHz on M66EN=1)
334	*/
335	#define PLLMR0_DEFAULT (PLL_CPUDIV_1 \| PLL_PLBDIV_1 \| \
336	PLL_OPBDIV_2 \| PLL_EXTBUSDIV_3 \| \
337	PLL_MALDIV_1 \| PLL_PCIDIV_3)
338	#define PLLMR1_DEFAULT (PLL_FBKDIV_4 \| \
339	PLL_FWDDIVA_6 \| PLL_FWDDIVB_6 \| \
340	PLL_TUNE_15_M_40 \| PLL_TUNE_VCO_LOW)
341	#endif
342
343	#endif /* __CONFIG_H */