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99d8b23b MF |
1 | /* |
2 | * (C) Copyright 2009 | |
3 | * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd.eu | |
4 | * | |
3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
99d8b23b MF |
6 | */ |
7 | ||
8 | #ifndef __CONFIG_H | |
9 | #define __CONFIG_H | |
10 | ||
11 | #define CONFIG_405EP 1 /* This is a PPC405 CPU */ | |
99d8b23b MF |
12 | #define CONFIG_PMC405DE 1 /* ...on a PMC405DE board */ |
13 | ||
2ae18241 WD |
14 | #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 |
15 | ||
99d8b23b MF |
16 | #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ |
17 | #define CONFIG_BOARD_TYPES 1 /* support board types */ | |
18 | ||
19 | #define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ | |
20 | ||
99d8b23b MF |
21 | #undef CONFIG_BOOTARGS |
22 | #undef CONFIG_BOOTCOMMAND | |
23 | ||
24 | #define CONFIG_PREBOOT /* enable preboot variable */ | |
25 | ||
26 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change*/ | |
27 | ||
99d8b23b MF |
28 | #define CONFIG_HAS_ETH1 |
29 | ||
30 | #define CONFIG_PPC4xx_EMAC | |
31 | #define CONFIG_MII 1 /* MII PHY management */ | |
32 | #define CONFIG_PHY_ADDR 1 /* PHY address */ | |
33 | #define CONFIG_PHY1_ADDR 2 /* 2nd PHY address */ | |
34 | ||
35 | #define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ | |
36 | ||
37 | /* | |
38 | * BOOTP options | |
39 | */ | |
40 | #define CONFIG_BOOTP_SUBNETMASK | |
41 | #define CONFIG_BOOTP_GATEWAY | |
42 | #define CONFIG_BOOTP_HOSTNAME | |
43 | #define CONFIG_BOOTP_BOOTPATH | |
44 | #define CONFIG_BOOTP_DNS | |
45 | #define CONFIG_BOOTP_DNS2 | |
46 | #define CONFIG_BOOTP_SEND_HOSTNAME | |
47 | ||
48 | /* | |
49 | * Command line configuration. | |
50 | */ | |
99d8b23b | 51 | #define CONFIG_CMD_PCI |
99d8b23b | 52 | |
99d8b23b MF |
53 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
54 | #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ | |
55 | #define CONFIG_PRAM 0 | |
56 | ||
57 | /* | |
58 | * Miscellaneous configurable options | |
59 | */ | |
60 | #define CONFIG_SYS_LONGHELP | |
99d8b23b MF |
61 | |
62 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
63 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
64 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
65 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ | |
66 | ||
67 | #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ | |
99d8b23b MF |
68 | |
69 | #define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */ | |
70 | #define CONFIG_SYS_MEMTEST_END 0x3000000 /* 1 ... 48 MB in DRAM */ | |
71 | ||
550650dd | 72 | #define CONFIG_CONS_INDEX 2 /* Use UART1 */ |
550650dd SR |
73 | #define CONFIG_SYS_NS16550_SERIAL |
74 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
75 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() | |
76 | ||
99d8b23b MF |
77 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK |
78 | #define CONFIG_SYS_BASE_BAUD 691200 | |
99d8b23b | 79 | |
99d8b23b MF |
80 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
81 | #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ | |
82 | ||
99d8b23b | 83 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
99d8b23b | 84 | #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ |
99d8b23b | 85 | |
99d8b23b MF |
86 | /* |
87 | * PCI stuff | |
88 | */ | |
89 | #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ | |
90 | #define PCI_HOST_FORCE 1 /* configure as pci host */ | |
91 | #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ | |
92 | ||
842033e6 | 93 | #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ |
99d8b23b | 94 | #define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ |
99d8b23b MF |
95 | |
96 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
97 | ||
98 | /* | |
99 | * PCI identification | |
100 | */ | |
101 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID PCI_VENDOR_ID_ESDGMBH | |
102 | #define CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH 0x040e /* Dev ID: Non-Monarch */ | |
103 | #define CONFIG_SYS_PCI_SUBSYS_ID_MONARCH 0x040f /* Dev ID: Monarch */ | |
104 | #define CONFIG_SYS_PCI_CLASSCODE_NONMONARCH PCI_CLASS_PROCESSOR_POWERPC | |
105 | #define CONFIG_SYS_PCI_CLASSCODE_MONARCH PCI_CLASS_BRIDGE_HOST | |
106 | ||
107 | #define CONFIG_SYS_PCI_CLASSCODE CONFIG_SYS_PCI_CLASSCODE_MONARCH | |
108 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID CONFIG_SYS_PCI_SUBSYS_ID_MONARCH | |
109 | ||
110 | #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ | |
111 | #define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable=1 */ | |
112 | #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ | |
113 | #define CONFIG_SYS_PCI_PTM2LA 0xef000000 /* point to CPLD, GPIO */ | |
114 | #define CONFIG_SYS_PCI_PTM2MS 0xff000001 /* 16MB, enable=1 */ | |
115 | #define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ | |
116 | ||
82379b55 MF |
117 | #define CONFIG_PCI_4xx_PTM_OVERWRITE 1 /* overwrite PTMx settings by env */ |
118 | ||
99d8b23b MF |
119 | /* |
120 | * For booting Linux, the board info and command line data | |
121 | * have to be in the first 8 MB of memory, since this is | |
122 | * the maximum mapped by the Linux kernel during initialization. | |
123 | */ | |
124 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) | |
125 | /* | |
126 | * FLASH organization | |
127 | */ | |
128 | #define CONFIG_SYS_FLASH_CFI 1 /* CFI compatible */ | |
129 | #define CONFIG_FLASH_CFI_DRIVER 1 /* Use common CFI driver */ | |
130 | ||
131 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } | |
132 | ||
133 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max. no. memory banks */ | |
134 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per chip */ | |
135 | ||
136 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* erase timeout (in ms) */ | |
137 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* write timeout (in ms) */ | |
138 | ||
139 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* buffered writes (faster) */ | |
140 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware flash protection */ | |
141 | ||
142 | #define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* 'E' for empty sector (flinfo) */ | |
143 | #define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ | |
144 | ||
99d8b23b MF |
145 | /* |
146 | * Start addresses for the final memory configuration | |
147 | * (Set up by the startup code) | |
148 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 | |
149 | */ | |
150 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 | |
151 | #define CONFIG_SYS_FLASH_BASE 0xfe000000 | |
14d0a02a WD |
152 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
153 | #define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1) | |
99d8b23b MF |
154 | #define CONFIG_SYS_MALLOC_LEN (256 * 1024) |
155 | ||
156 | /* | |
157 | * Environment in EEPROM setup | |
158 | */ | |
159 | #define CONFIG_ENV_IS_IN_EEPROM 1 | |
160 | #define CONFIG_ENV_OFFSET 0x100 | |
161 | #define CONFIG_ENV_SIZE 0x700 | |
162 | ||
163 | /* | |
164 | * I2C EEPROM (24W16) for environment | |
165 | */ | |
880540de DE |
166 | #define CONFIG_SYS_I2C |
167 | #define CONFIG_SYS_I2C_PPC4XX | |
168 | #define CONFIG_SYS_I2C_PPC4XX_CH0 | |
169 | #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 | |
170 | #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F | |
99d8b23b MF |
171 | |
172 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM 24W16 */ | |
173 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ | |
174 | /* mask of address bits that overflow into the "EEPROM chip address" */ | |
175 | #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 | |
176 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ | |
177 | /* 16 byte page write mode using*/ | |
178 | /* last 4 bits of the address */ | |
179 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ | |
180 | #define CONFIG_SYS_EEPROM_WREN 1 | |
181 | ||
182 | #define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x50 | |
183 | #define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0x40 | |
184 | #define CONFIG_4xx_CONFIG_BLOCKSIZE 0x20 | |
185 | ||
186 | /* | |
187 | * RTC | |
188 | */ | |
189 | #define CONFIG_RTC_RX8025 | |
190 | ||
191 | /* | |
192 | * External Bus Controller (EBC) Setup | |
193 | * (max. 55MHZ EBC clock) | |
194 | */ | |
195 | /* Memory Bank 0 (NOR flash) BAS=0xFE0,BS=32MB,BU=R/W,BW=16bit */ | |
196 | #define CONFIG_SYS_EBC_PB0AP 0x03017200 | |
197 | #define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH_BASE | 0xba000) | |
198 | ||
199 | /* Memory Bank 1 (CPLD) BAS=0xEF0,BS=16MB,BU=R/W,BW=16bit */ | |
200 | #define CONFIG_SYS_CPLD_BASE 0xef000000 | |
201 | #define CONFIG_SYS_EBC_PB1AP 0x00800000 | |
202 | #define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_CPLD_BASE | 0x18000) | |
203 | ||
204 | /* | |
205 | * Definitions for initial stack pointer and data area (in data cache) | |
206 | */ | |
207 | /* use on chip memory ( OCM ) for temperary stack until sdram is tested */ | |
208 | #define CONFIG_SYS_TEMP_STACK_OCM 1 | |
209 | ||
210 | /* On Chip Memory location */ | |
211 | #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 | |
212 | #define CONFIG_SYS_OCM_DATA_SIZE 0x1000 | |
213 | /* inside SDRAM */ | |
214 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR | |
215 | /* End of used area in RAM */ | |
553f0982 | 216 | #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE |
99d8b23b | 217 | |
553f0982 | 218 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ |
25ddd1fb | 219 | GENERATED_GBL_DATA_SIZE) |
99d8b23b MF |
220 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
221 | ||
222 | /* | |
223 | * GPIO Configuration | |
224 | */ | |
225 | #define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alt1 */ \ | |
226 | { \ | |
227 | /* GPIO Core 0 */ \ | |
228 | { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \ | |
229 | { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \ | |
230 | { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \ | |
231 | { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \ | |
232 | { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \ | |
233 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \ | |
234 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO6 TS4 */ \ | |
235 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO7 TS5 */ \ | |
236 | { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \ | |
237 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO9 TrcClk */ \ | |
238 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \ | |
239 | { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \ | |
240 | { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \ | |
241 | { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \ | |
242 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \ | |
243 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \ | |
244 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \ | |
245 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \ | |
246 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \ | |
247 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \ | |
248 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \ | |
249 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \ | |
250 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \ | |
251 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \ | |
252 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \ | |
253 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \ | |
254 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \ | |
255 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \ | |
256 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \ | |
257 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \ | |
258 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \ | |
259 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \ | |
260 | } \ | |
261 | } | |
262 | ||
263 | #define CONFIG_SYS_GPIO_HWREV_MASK (0xf0000000 >> 1) /* GPIO1..4 */ | |
264 | #define CONFIG_SYS_GPIO_HWREV_SHIFT 27 | |
265 | #define CONFIG_SYS_GPIO_LEDRUN_N (0x80000000 >> 5) /* GPIO5 */ | |
266 | #define CONFIG_SYS_GPIO_LEDA_N (0x80000000 >> 6) /* GPIO6 */ | |
267 | #define CONFIG_SYS_GPIO_LEDB_N (0x80000000 >> 7) /* GPIO7 */ | |
268 | #define CONFIG_SYS_GPIO_SELFRST_N (0x80000000 >> 8) /* GPIO8 */ | |
269 | #define CONFIG_SYS_GPIO_EEPROM_WP (0x80000000 >> 9) /* GPIO9 */ | |
270 | #define CONFIG_SYS_GPIO_MONARCH_N (0x80000000 >> 11) /* GPIO11 */ | |
271 | #define CONFIG_SYS_GPIO_EREADY (0x80000000 >> 12) /* GPIO12 */ | |
272 | #define CONFIG_SYS_GPIO_M66EN (0x80000000 >> 13) /* GPIO13 */ | |
273 | ||
274 | /* | |
275 | * Default speed selection (cpu_plb_opb_ebc) in mhz. | |
276 | * This value will be set if iic boot eprom is disabled. | |
277 | */ | |
278 | #undef CONFIG_SYS_FCPU333MHZ | |
279 | #define CONFIG_SYS_FCPU266MHZ | |
280 | #undef CONFIG_SYS_FCPU133MHZ | |
281 | ||
282 | #if defined(CONFIG_SYS_FCPU333MHZ) | |
283 | /* | |
284 | * CPU: 333MHz | |
285 | * PLB/SDRAM/MAL: 111MHz | |
286 | * OPB: 55MHz | |
287 | * EBC: 55MHz | |
288 | * PCI: 55MHz (111MHz on M66EN=1) | |
289 | */ | |
290 | #define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ | |
291 | PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ | |
292 | PLL_MALDIV_1 | PLL_PCIDIV_2) | |
293 | #define PLLMR1_DEFAULT (PLL_FBKDIV_10 | \ | |
294 | PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ | |
295 | PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) | |
296 | #endif | |
297 | ||
298 | #if defined(CONFIG_SYS_FCPU266MHZ) | |
299 | /* | |
300 | * CPU: 266MHz | |
301 | * PLB/SDRAM/MAL: 133MHz | |
302 | * OPB: 66MHz | |
303 | * EBC: 44MHz | |
304 | * PCI: 44MHz (66MHz on M66EN=1) | |
305 | */ | |
306 | #define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ | |
307 | PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ | |
308 | PLL_MALDIV_1 | PLL_PCIDIV_3) | |
309 | #define PLLMR1_DEFAULT (PLL_FBKDIV_8 | \ | |
310 | PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ | |
311 | PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) | |
312 | #endif | |
313 | ||
314 | #if defined(CONFIG_SYS_FCPU133MHZ) | |
315 | /* | |
316 | * CPU: 133MHz | |
317 | * PLB/SDRAM/MAL: 133MHz | |
318 | * OPB: 66MHz | |
319 | * EBC: 44MHz | |
320 | * PCI: 44MHz (66MHz on M66EN=1) | |
321 | */ | |
322 | #define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \ | |
323 | PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ | |
324 | PLL_MALDIV_1 | PLL_PCIDIV_3) | |
325 | #define PLLMR1_DEFAULT (PLL_FBKDIV_4 | \ | |
326 | PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \ | |
327 | PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) | |
328 | #endif | |
329 | ||
330 | #endif /* __CONFIG_H */ |