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99d8b23b MF |
1 | /* |
2 | * (C) Copyright 2009 | |
3 | * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd.eu | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #ifndef __CONFIG_H | |
25 | #define __CONFIG_H | |
26 | ||
27 | #define CONFIG_405EP 1 /* This is a PPC405 CPU */ | |
28 | #define CONFIG_4xx 1 /* ...member of PPC4xx family */ | |
29 | #define CONFIG_PMC405DE 1 /* ...on a PMC405DE board */ | |
30 | ||
31 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ | |
32 | #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ | |
33 | #define CONFIG_BOARD_TYPES 1 /* support board types */ | |
34 | ||
35 | #define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ | |
36 | ||
37 | #define CONFIG_BAUDRATE 115200 | |
38 | #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ | |
39 | ||
40 | #undef CONFIG_BOOTARGS | |
41 | #undef CONFIG_BOOTCOMMAND | |
42 | ||
43 | #define CONFIG_PREBOOT /* enable preboot variable */ | |
44 | ||
45 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change*/ | |
46 | ||
47 | #define CONFIG_NET_MULTI 1 | |
48 | #define CONFIG_HAS_ETH1 | |
49 | ||
50 | #define CONFIG_PPC4xx_EMAC | |
51 | #define CONFIG_MII 1 /* MII PHY management */ | |
52 | #define CONFIG_PHY_ADDR 1 /* PHY address */ | |
53 | #define CONFIG_PHY1_ADDR 2 /* 2nd PHY address */ | |
54 | ||
55 | #define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ | |
56 | ||
57 | /* | |
58 | * BOOTP options | |
59 | */ | |
60 | #define CONFIG_BOOTP_SUBNETMASK | |
61 | #define CONFIG_BOOTP_GATEWAY | |
62 | #define CONFIG_BOOTP_HOSTNAME | |
63 | #define CONFIG_BOOTP_BOOTPATH | |
64 | #define CONFIG_BOOTP_DNS | |
65 | #define CONFIG_BOOTP_DNS2 | |
66 | #define CONFIG_BOOTP_SEND_HOSTNAME | |
67 | ||
68 | /* | |
69 | * Command line configuration. | |
70 | */ | |
71 | #include <config_cmd_default.h> | |
72 | ||
73 | #define CONFIG_CMD_BSP | |
74 | #define CONFIG_CMD_CHIP_CONFIG | |
75 | #define CONFIG_CMD_DATE | |
76 | #define CONFIG_CMD_DHCP | |
77 | #define CONFIG_CMD_EEPROM | |
78 | #define CONFIG_CMD_ELF | |
79 | #define CONFIG_CMD_I2C | |
80 | #define CONFIG_CMD_IRQ | |
81 | #define CONFIG_CMD_MII | |
82 | #define CONFIG_CMD_NFS | |
83 | #define CONFIG_CMD_PCI | |
84 | #define CONFIG_CMD_PING | |
85 | ||
86 | #define CONFIG_OF_LIBFDT | |
87 | #define CONFIG_OF_BOARD_SETUP | |
88 | ||
89 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
90 | #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ | |
91 | #define CONFIG_PRAM 0 | |
92 | ||
93 | /* | |
94 | * Miscellaneous configurable options | |
95 | */ | |
96 | #define CONFIG_SYS_LONGHELP | |
97 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
98 | ||
99 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
100 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
101 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
102 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ | |
103 | ||
104 | #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ | |
105 | #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console info */ | |
106 | ||
107 | #define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */ | |
108 | #define CONFIG_SYS_MEMTEST_END 0x3000000 /* 1 ... 48 MB in DRAM */ | |
109 | ||
550650dd SR |
110 | #define CONFIG_CONS_INDEX 2 /* Use UART1 */ |
111 | #define CONFIG_SYS_NS16550 | |
112 | #define CONFIG_SYS_NS16550_SERIAL | |
113 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
114 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() | |
115 | ||
99d8b23b MF |
116 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK |
117 | #define CONFIG_SYS_BASE_BAUD 691200 | |
99d8b23b MF |
118 | |
119 | /* The following table includes the supported baudrates */ | |
120 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
121 | { 9600, 19200, 38400, 57600, 115200 } | |
122 | ||
123 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ | |
124 | #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ | |
125 | ||
126 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
127 | ||
128 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ | |
129 | #define CONFIG_LOOPW 1 /* enable loopw command */ | |
130 | #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ | |
131 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ | |
132 | #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ | |
133 | ||
134 | #define CONFIG_AUTOBOOT_KEYED 1 | |
135 | #define CONFIG_AUTOBOOT_PROMPT \ | |
136 | "Press SPACE to abort autoboot in %d seconds\n", bootdelay | |
137 | #undef CONFIG_AUTOBOOT_DELAY_STR | |
138 | #define CONFIG_AUTOBOOT_STOP_STR " " | |
139 | ||
140 | /* | |
141 | * PCI stuff | |
142 | */ | |
143 | #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ | |
144 | #define PCI_HOST_FORCE 1 /* configure as pci host */ | |
145 | #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ | |
146 | ||
147 | #define CONFIG_PCI /* include pci support */ | |
148 | #define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ | |
149 | #define CONFIG_PCI_PNP /* do (not) pci plug-and-play */ | |
150 | ||
151 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
152 | ||
153 | /* | |
154 | * PCI identification | |
155 | */ | |
156 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID PCI_VENDOR_ID_ESDGMBH | |
157 | #define CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH 0x040e /* Dev ID: Non-Monarch */ | |
158 | #define CONFIG_SYS_PCI_SUBSYS_ID_MONARCH 0x040f /* Dev ID: Monarch */ | |
159 | #define CONFIG_SYS_PCI_CLASSCODE_NONMONARCH PCI_CLASS_PROCESSOR_POWERPC | |
160 | #define CONFIG_SYS_PCI_CLASSCODE_MONARCH PCI_CLASS_BRIDGE_HOST | |
161 | ||
162 | #define CONFIG_SYS_PCI_CLASSCODE CONFIG_SYS_PCI_CLASSCODE_MONARCH | |
163 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID CONFIG_SYS_PCI_SUBSYS_ID_MONARCH | |
164 | ||
165 | #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ | |
166 | #define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable=1 */ | |
167 | #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ | |
168 | #define CONFIG_SYS_PCI_PTM2LA 0xef000000 /* point to CPLD, GPIO */ | |
169 | #define CONFIG_SYS_PCI_PTM2MS 0xff000001 /* 16MB, enable=1 */ | |
170 | #define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ | |
171 | ||
82379b55 MF |
172 | #define CONFIG_PCI_4xx_PTM_OVERWRITE 1 /* overwrite PTMx settings by env */ |
173 | ||
99d8b23b MF |
174 | /* |
175 | * For booting Linux, the board info and command line data | |
176 | * have to be in the first 8 MB of memory, since this is | |
177 | * the maximum mapped by the Linux kernel during initialization. | |
178 | */ | |
179 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) | |
180 | /* | |
181 | * FLASH organization | |
182 | */ | |
183 | #define CONFIG_SYS_FLASH_CFI 1 /* CFI compatible */ | |
184 | #define CONFIG_FLASH_CFI_DRIVER 1 /* Use common CFI driver */ | |
185 | ||
186 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } | |
187 | ||
188 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max. no. memory banks */ | |
189 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per chip */ | |
190 | ||
191 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* erase timeout (in ms) */ | |
192 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* write timeout (in ms) */ | |
193 | ||
194 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* buffered writes (faster) */ | |
195 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware flash protection */ | |
196 | ||
197 | #define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* 'E' for empty sector (flinfo) */ | |
198 | #define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ | |
199 | ||
200 | ||
201 | /* | |
202 | * Start addresses for the final memory configuration | |
203 | * (Set up by the startup code) | |
204 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 | |
205 | */ | |
206 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 | |
207 | #define CONFIG_SYS_FLASH_BASE 0xfe000000 | |
14d0a02a WD |
208 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
209 | #define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1) | |
99d8b23b MF |
210 | #define CONFIG_SYS_MALLOC_LEN (256 * 1024) |
211 | ||
212 | /* | |
213 | * Environment in EEPROM setup | |
214 | */ | |
215 | #define CONFIG_ENV_IS_IN_EEPROM 1 | |
216 | #define CONFIG_ENV_OFFSET 0x100 | |
217 | #define CONFIG_ENV_SIZE 0x700 | |
218 | ||
219 | /* | |
220 | * I2C EEPROM (24W16) for environment | |
221 | */ | |
222 | #define CONFIG_HARD_I2C /* I2c with hardware support */ | |
d0b0dcaa | 223 | #define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ |
99d8b23b MF |
224 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
225 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
226 | ||
227 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM 24W16 */ | |
228 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ | |
229 | /* mask of address bits that overflow into the "EEPROM chip address" */ | |
230 | #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 | |
231 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ | |
232 | /* 16 byte page write mode using*/ | |
233 | /* last 4 bits of the address */ | |
234 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ | |
235 | #define CONFIG_SYS_EEPROM_WREN 1 | |
236 | ||
237 | #define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x50 | |
238 | #define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0x40 | |
239 | #define CONFIG_4xx_CONFIG_BLOCKSIZE 0x20 | |
240 | ||
241 | /* | |
242 | * RTC | |
243 | */ | |
244 | #define CONFIG_RTC_RX8025 | |
245 | ||
246 | /* | |
247 | * External Bus Controller (EBC) Setup | |
248 | * (max. 55MHZ EBC clock) | |
249 | */ | |
250 | /* Memory Bank 0 (NOR flash) BAS=0xFE0,BS=32MB,BU=R/W,BW=16bit */ | |
251 | #define CONFIG_SYS_EBC_PB0AP 0x03017200 | |
252 | #define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH_BASE | 0xba000) | |
253 | ||
254 | /* Memory Bank 1 (CPLD) BAS=0xEF0,BS=16MB,BU=R/W,BW=16bit */ | |
255 | #define CONFIG_SYS_CPLD_BASE 0xef000000 | |
256 | #define CONFIG_SYS_EBC_PB1AP 0x00800000 | |
257 | #define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_CPLD_BASE | 0x18000) | |
258 | ||
259 | /* | |
260 | * Definitions for initial stack pointer and data area (in data cache) | |
261 | */ | |
262 | /* use on chip memory ( OCM ) for temperary stack until sdram is tested */ | |
263 | #define CONFIG_SYS_TEMP_STACK_OCM 1 | |
264 | ||
265 | /* On Chip Memory location */ | |
266 | #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 | |
267 | #define CONFIG_SYS_OCM_DATA_SIZE 0x1000 | |
268 | /* inside SDRAM */ | |
269 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR | |
270 | /* End of used area in RAM */ | |
271 | #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE | |
272 | ||
273 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes res. for initial data */ | |
274 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \ | |
275 | CONFIG_SYS_GBL_DATA_SIZE) | |
276 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
277 | ||
278 | /* | |
279 | * GPIO Configuration | |
280 | */ | |
281 | #define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alt1 */ \ | |
282 | { \ | |
283 | /* GPIO Core 0 */ \ | |
284 | { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \ | |
285 | { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \ | |
286 | { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \ | |
287 | { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \ | |
288 | { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \ | |
289 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \ | |
290 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO6 TS4 */ \ | |
291 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO7 TS5 */ \ | |
292 | { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \ | |
293 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO9 TrcClk */ \ | |
294 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \ | |
295 | { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \ | |
296 | { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \ | |
297 | { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \ | |
298 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \ | |
299 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \ | |
300 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \ | |
301 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \ | |
302 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \ | |
303 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \ | |
304 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \ | |
305 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \ | |
306 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \ | |
307 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \ | |
308 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \ | |
309 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \ | |
310 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \ | |
311 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \ | |
312 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \ | |
313 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \ | |
314 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \ | |
315 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \ | |
316 | } \ | |
317 | } | |
318 | ||
319 | #define CONFIG_SYS_GPIO_HWREV_MASK (0xf0000000 >> 1) /* GPIO1..4 */ | |
320 | #define CONFIG_SYS_GPIO_HWREV_SHIFT 27 | |
321 | #define CONFIG_SYS_GPIO_LEDRUN_N (0x80000000 >> 5) /* GPIO5 */ | |
322 | #define CONFIG_SYS_GPIO_LEDA_N (0x80000000 >> 6) /* GPIO6 */ | |
323 | #define CONFIG_SYS_GPIO_LEDB_N (0x80000000 >> 7) /* GPIO7 */ | |
324 | #define CONFIG_SYS_GPIO_SELFRST_N (0x80000000 >> 8) /* GPIO8 */ | |
325 | #define CONFIG_SYS_GPIO_EEPROM_WP (0x80000000 >> 9) /* GPIO9 */ | |
326 | #define CONFIG_SYS_GPIO_MONARCH_N (0x80000000 >> 11) /* GPIO11 */ | |
327 | #define CONFIG_SYS_GPIO_EREADY (0x80000000 >> 12) /* GPIO12 */ | |
328 | #define CONFIG_SYS_GPIO_M66EN (0x80000000 >> 13) /* GPIO13 */ | |
329 | ||
330 | /* | |
331 | * Default speed selection (cpu_plb_opb_ebc) in mhz. | |
332 | * This value will be set if iic boot eprom is disabled. | |
333 | */ | |
334 | #undef CONFIG_SYS_FCPU333MHZ | |
335 | #define CONFIG_SYS_FCPU266MHZ | |
336 | #undef CONFIG_SYS_FCPU133MHZ | |
337 | ||
338 | #if defined(CONFIG_SYS_FCPU333MHZ) | |
339 | /* | |
340 | * CPU: 333MHz | |
341 | * PLB/SDRAM/MAL: 111MHz | |
342 | * OPB: 55MHz | |
343 | * EBC: 55MHz | |
344 | * PCI: 55MHz (111MHz on M66EN=1) | |
345 | */ | |
346 | #define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ | |
347 | PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ | |
348 | PLL_MALDIV_1 | PLL_PCIDIV_2) | |
349 | #define PLLMR1_DEFAULT (PLL_FBKDIV_10 | \ | |
350 | PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ | |
351 | PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) | |
352 | #endif | |
353 | ||
354 | #if defined(CONFIG_SYS_FCPU266MHZ) | |
355 | /* | |
356 | * CPU: 266MHz | |
357 | * PLB/SDRAM/MAL: 133MHz | |
358 | * OPB: 66MHz | |
359 | * EBC: 44MHz | |
360 | * PCI: 44MHz (66MHz on M66EN=1) | |
361 | */ | |
362 | #define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ | |
363 | PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ | |
364 | PLL_MALDIV_1 | PLL_PCIDIV_3) | |
365 | #define PLLMR1_DEFAULT (PLL_FBKDIV_8 | \ | |
366 | PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ | |
367 | PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) | |
368 | #endif | |
369 | ||
370 | #if defined(CONFIG_SYS_FCPU133MHZ) | |
371 | /* | |
372 | * CPU: 133MHz | |
373 | * PLB/SDRAM/MAL: 133MHz | |
374 | * OPB: 66MHz | |
375 | * EBC: 44MHz | |
376 | * PCI: 44MHz (66MHz on M66EN=1) | |
377 | */ | |
378 | #define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \ | |
379 | PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ | |
380 | PLL_MALDIV_1 | PLL_PCIDIV_3) | |
381 | #define PLLMR1_DEFAULT (PLL_FBKDIV_4 | \ | |
382 | PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \ | |
383 | PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) | |
384 | #endif | |
385 | ||
386 | #endif /* __CONFIG_H */ |