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* Patch by Robert Schwebel, 15 Dec 2003:
[people/ms/u-boot.git] / include / configs / PPChameleonEVB.h
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12f34241 1/*
fbe4b5cb
WD		 2 * (C) Copyright 2003
3 * DAVE Srl
12f34241 4 *
fbe4b5cb
WD		 5 * http://www.dave-tech.it
6 * http://www.wawnet.biz
7 * mailto:info@wawnet.biz
8 *
9 * Credits: Stefan Roese, Wolfgang Denk
12f34241
WD		 10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27/*
28 * board/config.h - configuration options, board specific
29 */
30
31#ifndef __CONFIG_H
32#define __CONFIG_H
33
42d1f039 34#define CONFIG_PPCHAMELEON_MODULE_BA 0 /* Basic Model */
fbe4b5cb
WD		 35#define CONFIG_PPCHAMELEON_MODULE_ME 1 /* Medium Model */
36#define CONFIG_PPCHAMELEON_MODULE_HI 2 /* High-End Model */
37#ifndef CONFIG_PPCHAMELEON_MODULE_MODEL
38#define CONFIG_PPCHAMELEON_MODULE_MODEL CONFIG_PPCHAMELEON_MODULE_BA
39#endif
40
12f34241
WD		 41/*
42 * Debug stuff
43 */
4d816774 44#undef __DEBUG_START_FROM_SRAM__
12f34241
WD		 45#define __DISABLE_MACHINE_EXCEPTION__
46
47#ifdef __DEBUG_START_FROM_SRAM__
48#define CFG_DUMMY_FLASH_SIZE 1024*1024*4
49#endif
50
51/*
52 * High Level Configuration Options
53 * (easy to change)
54 */
55
56#define CONFIG_405EP 1 /* This is a PPC405 CPU */
57#define CONFIG_4xx 1 /* ...member of PPC4xx family */
58#define CONFIG_PPCHAMELEONEVB 1 /* ...on a PPChameleonEVB board */
59
60#define CONFIG_BOARD_PRE_INIT 1 /* call board_pre_init() */
61#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
62
63#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
64
12f34241 65#define CONFIG_BAUDRATE 115200
4d816774 66#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
12f34241 67
12f34241 68#undef CONFIG_BOOTARGS
12f34241 69
200f8c7a
WD		 70/* Ethernet stuff */
71#define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */
72#define CONFIG_ETHADDR 00:50:c2:1e:af:fe
73#define CONFIG_ETH1ADDR 00:50:c2:1e:af:fd
12f34241
WD		 74
75#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
76#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
77
78
12f34241 79#undef CONFIG_EXT_PHY
4d816774 80
12f34241
WD		 81#define CONFIG_MII 1 /* MII PHY management */
82#ifndef CONFIG_EXT_PHY
83#define CONFIG_PHY_ADDR 1 /* PHY address */
84#else
85#define CONFIG_PHY_ADDR 2 /* PHY address */
86#endif
87#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
88
12f34241 89#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
12f34241 90 CFG_CMD_DATE | \
12f34241 91 CFG_CMD_ELF | \
4d816774 92 CFG_CMD_EEPROM | \
12f34241 93 CFG_CMD_I2C | \
4d816774
WD		 94 CFG_CMD_IRQ | \
95 CFG_CMD_MII | \
96 CFG_CMD_NAND )
12f34241
WD		 97
98#define CONFIG_MAC_PARTITION
99#define CONFIG_DOS_PARTITION
100
101/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
102#include <cmd_confdefs.h>
103
104#undef CONFIG_WATCHDOG /* watchdog disabled */
105
106#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
107#define CFG_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
108
109#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
110
111/*
112 * Miscellaneous configurable options
113 */
114#define CFG_LONGHELP /* undef to save memory */
4d816774 115#define CFG_PROMPT "=> " /* Monitor Command Prompt */
12f34241
WD		 116
117#undef CFG_HUSH_PARSER /* use "hush" command parser */
118#ifdef CFG_HUSH_PARSER
119#define CFG_PROMPT_HUSH_PS2 "> "
120#endif
121
122#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
123#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
124#else
125#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
126#endif
127#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
128#define CFG_MAXARGS 16 /* max number of command args */
129#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
130
131#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
132
133#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
134
135#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
136#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
137
138#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
139#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
140#define CFG_BASE_BAUD 691200
141
142/* The following table includes the supported baudrates */
143#define CFG_BAUDRATE_TABLE \
42d1f039
WD		 144 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
145 57600, 115200, 230400, 460800, 921600 }
12f34241
WD		 146
147#define CFG_LOAD_ADDR 0x100000 /* default load address */
148#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
149
150#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
151
152#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
153
154/*-----------------------------------------------------------------------
155 * NAND-FLASH stuff
156 *-----------------------------------------------------------------------
157 */
158#define CFG_NAND0_BASE 0xFF400000
159#define CFG_NAND1_BASE 0xFF000000
160
161#define CFG_MAX_NAND_DEVICE 2 /* Max number of NAND devices */
162#define SECTORSIZE 512
fbe4b5cb 163#define NAND_NO_RB
12f34241
WD		 164
165#define ADDR_COLUMN 1
166#define ADDR_PAGE 2
167#define ADDR_COLUMN_PAGE 3
168
169#define NAND_ChipID_UNKNOWN 0x00
170#define NAND_MAX_FLOORS 1
171#define NAND_MAX_CHIPS 1
172
173#define CFG_NAND0_CE (0x80000000 >> 1) /* our CE is GPIO1 */
174#define CFG_NAND0_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
175#define CFG_NAND0_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
176#define CFG_NAND0_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
177
178#define CFG_NAND1_CE (0x80000000 >> 14) /* our CE is GPIO14 */
179#define CFG_NAND1_CLE (0x80000000 >> 15) /* our CLE is GPIO15 */
180#define CFG_NAND1_ALE (0x80000000 >> 16) /* our ALE is GPIO16 */
181#define CFG_NAND1_RDY (0x80000000 >> 31) /* our RDY is GPIO31 */
182
183
184#define NAND_DISABLE_CE(nand) do \
185{ \
186 switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \
42d1f039
WD		 187 { \
188 case CFG_NAND0_BASE: \
189 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CE); \
190 break; \
191 case CFG_NAND1_BASE: \
192 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CE); \
193 break; \
194 } \
12f34241
WD		 195} while(0)
196
197#define NAND_ENABLE_CE(nand) do \
198{ \
199 switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \
42d1f039
WD		 200 { \
201 case CFG_NAND0_BASE: \
202 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CE); \
203 break; \
204 case CFG_NAND1_BASE: \
205 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CE); \
206 break; \
207 } \
12f34241
WD		 208} while(0)
209
210
12f34241
WD		 211#define NAND_CTL_CLRALE(nandptr) do \
212{ \
213 switch((unsigned long)nandptr) \
42d1f039
WD		 214 { \
215 case CFG_NAND0_BASE: \
216 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_ALE); \
217 break; \
218 case CFG_NAND1_BASE: \
219 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_ALE); \
220 break; \
221 } \
12f34241
WD		 222} while(0)
223
224#define NAND_CTL_SETALE(nandptr) do \
225{ \
226 switch((unsigned long)nandptr) \
42d1f039
WD		 227 { \
228 case CFG_NAND0_BASE: \
229 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_ALE); \
230 break; \
231 case CFG_NAND1_BASE: \
232 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_ALE); \
233 break; \
234 } \
12f34241
WD		 235} while(0)
236
237#define NAND_CTL_CLRCLE(nandptr) do \
238{ \
239 switch((unsigned long)nandptr) \
42d1f039
WD		 240 { \
241 case CFG_NAND0_BASE: \
242 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CLE); \
243 break; \
244 case CFG_NAND1_BASE: \
245 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CLE); \
246 break; \
247 } \
12f34241
WD		 248} while(0)
249
250#define NAND_CTL_SETCLE(nandptr) do { \
251 switch((unsigned long)nandptr) { \
42d1f039
WD		 252 case CFG_NAND0_BASE: \
253 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CLE); \
254 break; \
255 case CFG_NAND1_BASE: \
256 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CLE); \
257 break; \
258 } \
12f34241
WD		 259} while(0)
260
fbe4b5cb
WD		 261#ifdef NAND_NO_RB
262/* constant delay (see also tR in the datasheet) */
12f34241 263#define NAND_WAIT_READY(nand) do { \
fbe4b5cb 264 udelay(12); \
12f34241 265} while (0)
fbe4b5cb
WD		 266#else
267/* use the R/B pin */
268/* TBD */
269#endif
12f34241
WD		 270
271#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
272#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
273#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
274#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
275
276/*-----------------------------------------------------------------------
277 * PCI stuff
278 *-----------------------------------------------------------------------
279 */
280#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
281#define PCI_HOST_FORCE 1 /* configure as pci host */
282#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
283
284#define CONFIG_PCI /* include pci support */
4654af27 285#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
12f34241 286#undef CONFIG_PCI_PNP /* do pci plug-and-play */
42d1f039 287 /* resource configuration */
12f34241
WD		 288
289#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
290
291#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
292#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
293#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
294#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
295#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
296#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
297#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
298#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
299#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
300
301/*-----------------------------------------------------------------------
302 * Start addresses for the final memory configuration
303 * (Set up by the startup code)
304 * Please note that CFG_SDRAM_BASE _must_ start at 0
305 */
306#define CFG_SDRAM_BASE 0x00000000
307#define CFG_FLASH_BASE 0xFFFC0000
308#define CFG_MONITOR_BASE CFG_FLASH_BASE
309#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
310#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
311
312/*
313 * For booting Linux, the board info and command line data
314 * have to be in the first 8 MB of memory, since this is
315 * the maximum mapped by the Linux kernel during initialization.
316 */
317#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
318/*-----------------------------------------------------------------------
319 * FLASH organization
320 */
321#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
322#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
323
324#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
325#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
326
327#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
328#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
329#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
330/*
331 * The following defines are added for buggy IOP480 byte interface.
332 * All other boards should use the standard values (CPCI405 etc.)
333 */
334#define CFG_FLASH_READ0 0x0000 /* 0 is standard */
335#define CFG_FLASH_READ1 0x0001 /* 1 is standard */
336#define CFG_FLASH_READ2 0x0002 /* 2 is standard */
337
338#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
339
340#if 0 /* test-only */
341#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
342#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
343#endif
344
345/*-----------------------------------------------------------------------
346 * Environment Variable setup
347 */
348#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
349#define CFG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
350#define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
42d1f039 351 /* total size of a CAT24WC16 is 2048 bytes */
12f34241
WD		 352
353#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
354#define CFG_NVRAM_SIZE 242 /* NVRAM size */
355
356/*-----------------------------------------------------------------------
357 * I2C EEPROM (CAT24WC16) for environment
358 */
359#define CONFIG_HARD_I2C /* I2c with hardware support */
360#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
361#define CFG_I2C_SLAVE 0x7F
362
363#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
364#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
365/* mask of address bits that overflow into the "EEPROM chip address" */
366/*#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07*/
367#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
368 /* 16 byte page write mode using*/
369 /* last 4 bits of the address */
370#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
371#define CFG_EEPROM_PAGE_WRITE_ENABLE
372
373/*-----------------------------------------------------------------------
374 * Cache Configuration
375 */
376#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
42d1f039 377 /* have only 8kB, 16kB is save here */
12f34241
WD		 378#define CFG_CACHELINE_SIZE 32 /* ... */
379#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
380#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
381#endif
382
383/*
384 * Init Memory Controller:
385 *
386 * BR0/1 and OR0/1 (FLASH)
387 */
388
389#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
390
391/*-----------------------------------------------------------------------
392 * External Bus Controller (EBC) Setup
393 */
394
395/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
396#define CFG_EBC_PB0AP 0x92015480
397#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
398
399/* Memory Bank 1 (External SRAM) initialization */
400/* Since this must replace NOR Flash, we use the same settings for CS0 */
401#define CFG_EBC_PB1AP 0x92015480
402#define CFG_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */
403
404/* Memory Bank 2 (Flash Bank 1, NAND-FLASH) initialization */
405#define CFG_EBC_PB2AP 0x92015480
406#define CFG_EBC_PB2CR 0xFF458000 /* BAS=0xFF4,BS=4MB,BU=R/W,BW=8bit */
407
408/* Memory Bank 3 (Flash Bank 2, NAND-FLASH) initialization */
409#define CFG_EBC_PB3AP 0x92015480
410#define CFG_EBC_PB3CR 0xFF058000 /* BAS=0xFF0,BS=4MB,BU=R/W,BW=8bit */
411
412
413#if 0 /* Roese */
414/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */
415#define CFG_EBC_PB1AP 0x92015480
416#define CFG_EBC_PB1CR 0xFF858000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */
417
418/* Memory Bank 2 (CAN0, 1) initialization */
419#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
420#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
421
422/* Memory Bank 3 (CompactFlash IDE) initialization */
423#define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
424#define CFG_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
425
426/* Memory Bank 4 (NVRAM/RTC) initialization */
427#define CFG_EBC_PB4AP 0x01005280 /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1 */
428#define CFG_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
429#endif
430
431/*-----------------------------------------------------------------------
432 * FPGA stuff
433 */
434/* FPGA internal regs */
435#define CFG_FPGA_MODE 0x00
436#define CFG_FPGA_STATUS 0x02
437#define CFG_FPGA_TS 0x04
438#define CFG_FPGA_TS_LOW 0x06
439#define CFG_FPGA_TS_CAP0 0x10
440#define CFG_FPGA_TS_CAP0_LOW 0x12
441#define CFG_FPGA_TS_CAP1 0x14
442#define CFG_FPGA_TS_CAP1_LOW 0x16
443#define CFG_FPGA_TS_CAP2 0x18
444#define CFG_FPGA_TS_CAP2_LOW 0x1a
445#define CFG_FPGA_TS_CAP3 0x1c
446#define CFG_FPGA_TS_CAP3_LOW 0x1e
447
448/* FPGA Mode Reg */
449#define CFG_FPGA_MODE_CF_RESET 0x0001
450#define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100
451#define CFG_FPGA_MODE_TS_IRQ_CLEAR 0x1000
452#define CFG_FPGA_MODE_TS_CLEAR 0x2000
453
454/* FPGA Status Reg */
455#define CFG_FPGA_STATUS_DIP0 0x0001
456#define CFG_FPGA_STATUS_DIP1 0x0002
457#define CFG_FPGA_STATUS_DIP2 0x0004
458#define CFG_FPGA_STATUS_FLASH 0x0008
459#define CFG_FPGA_STATUS_TS_IRQ 0x1000
460
461#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
462#define CFG_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/
463
464/* FPGA program pin configuration */
465#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
466#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
467#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
468#define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
469#define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
470
471/*-----------------------------------------------------------------------
472 * Definitions for initial stack pointer and data area (in data cache)
473 */
474#if 0 /* test-only */
475#define CFG_INIT_DCACHE_CS 4 /* use cs # 4 for data cache memory */
476
477#define CFG_INIT_RAM_ADDR 0x40000000 /* use data cache */
478#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
479#else
480/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
481#define CFG_TEMP_STACK_OCM 1
482
483/* On Chip Memory location */
484#define CFG_OCM_DATA_ADDR 0xF8000000
485#define CFG_OCM_DATA_SIZE 0x1000
486#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
487#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
488#endif
489
490#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
491#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
492#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
493
494/*-----------------------------------------------------------------------
495 * Definitions for GPIO setup (PPC405EP specific)
496 *
497 * GPIO0[0] - External Bus Controller BLAST output
498 * GPIO0[1-9] - Instruction trace outputs -> GPIO
499 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
500 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
501 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
502 * GPIO0[24-27] - UART0 control signal inputs/outputs
503 * GPIO0[28-29] - UART1 data signal input/output
504 * GPIO0[30] - EMAC0 input
505 * GPIO0[31] - EMAC1 reject packet as output
506 */
507#define CFG_GPIO0_OSRH 0x40000550
508#define CFG_GPIO0_OSRL 0x00000110
509#define CFG_GPIO0_ISR1H 0x00000000
510/*#define CFG_GPIO0_ISR1L 0x15555445*/
511#define CFG_GPIO0_ISR1L 0x15555444
512#define CFG_GPIO0_TSRH 0x00000000
513#define CFG_GPIO0_TSRL 0x00000000
514#define CFG_GPIO0_TCR 0xF7FF8014
515
516/*
517 * Internal Definitions
518 *
519 * Boot Flags
520 */
521#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
522#define BOOTFLAG_WARM 0x02 /* Software reboot */
523
524#if 1 /* test-only */
525#define CONFIG_NO_SERIAL_EEPROM
526/*#undef CONFIG_NO_SERIAL_EEPROM*/
200f8c7a 527/*--------------------------------------------------------------------*/
12f34241
WD		 528#ifdef CONFIG_NO_SERIAL_EEPROM
529
530
531/*
200f8c7a 532!-----------------------------------------------------------------------
12f34241
WD		 533! Defines for entry options.
534! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that
535! are plugged in the board will be utilized as non-ECC DIMMs.
200f8c7a 536!-----------------------------------------------------------------------
12f34241
WD		 537*/
538#undef AUTO_MEMORY_CONFIG
539#define DIMM_READ_ADDR 0xAB
540#define DIMM_WRITE_ADDR 0xAA
541
542
543#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */
544#define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */
545#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */
546#define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register*/
547#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */
548#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */
549#define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */
550#define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */
551#define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */
552#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */
553
554/* Defines for CPC0_PLLMR1 Register fields */
555#define PLL_ACTIVE 0x80000000
556#define CPC0_PLLMR1_SSCS 0x80000000
557#define PLL_RESET 0x40000000
558#define CPC0_PLLMR1_PLLR 0x40000000
559 /* Feedback multiplier */
560#define PLL_FBKDIV 0x00F00000
561#define CPC0_PLLMR1_FBDV 0x00F00000
562#define PLL_FBKDIV_16 0x00000000
563#define PLL_FBKDIV_1 0x00100000
564#define PLL_FBKDIV_2 0x00200000
565#define PLL_FBKDIV_3 0x00300000
566#define PLL_FBKDIV_4 0x00400000
567#define PLL_FBKDIV_5 0x00500000
568#define PLL_FBKDIV_6 0x00600000
569#define PLL_FBKDIV_7 0x00700000
570#define PLL_FBKDIV_8 0x00800000
571#define PLL_FBKDIV_9 0x00900000
572#define PLL_FBKDIV_10 0x00A00000
573#define PLL_FBKDIV_11 0x00B00000
574#define PLL_FBKDIV_12 0x00C00000
575#define PLL_FBKDIV_13 0x00D00000
576#define PLL_FBKDIV_14 0x00E00000
577#define PLL_FBKDIV_15 0x00F00000
578 /* Forward A divisor */
579#define PLL_FWDDIVA 0x00070000
580#define CPC0_PLLMR1_FWDVA 0x00070000
581#define PLL_FWDDIVA_8 0x00000000
582#define PLL_FWDDIVA_7 0x00010000
583#define PLL_FWDDIVA_6 0x00020000
584#define PLL_FWDDIVA_5 0x00030000
585#define PLL_FWDDIVA_4 0x00040000
586#define PLL_FWDDIVA_3 0x00050000
587#define PLL_FWDDIVA_2 0x00060000
588#define PLL_FWDDIVA_1 0x00070000
589 /* Forward B divisor */
590#define PLL_FWDDIVB 0x00007000
591#define CPC0_PLLMR1_FWDVB 0x00007000
592#define PLL_FWDDIVB_8 0x00000000
593#define PLL_FWDDIVB_7 0x00001000
594#define PLL_FWDDIVB_6 0x00002000
595#define PLL_FWDDIVB_5 0x00003000
596#define PLL_FWDDIVB_4 0x00004000
597#define PLL_FWDDIVB_3 0x00005000
598#define PLL_FWDDIVB_2 0x00006000
599#define PLL_FWDDIVB_1 0x00007000
600 /* PLL tune bits */
601#define PLL_TUNE_MASK 0x000003FF
602#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */
603#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */
604#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */
605#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */
606#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */
607#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */
608#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */
609
610/* Defines for CPC0_PLLMR0 Register fields */
611 /* CPU divisor */
612#define PLL_CPUDIV 0x00300000
613#define CPC0_PLLMR0_CCDV 0x00300000
614#define PLL_CPUDIV_1 0x00000000
615#define PLL_CPUDIV_2 0x00100000
616#define PLL_CPUDIV_3 0x00200000
617#define PLL_CPUDIV_4 0x00300000
618 /* PLB divisor */
619#define PLL_PLBDIV 0x00030000
620#define CPC0_PLLMR0_CBDV 0x00030000
621#define PLL_PLBDIV_1 0x00000000
622#define PLL_PLBDIV_2 0x00010000
623#define PLL_PLBDIV_3 0x00020000
624#define PLL_PLBDIV_4 0x00030000
625 /* OPB divisor */
626#define PLL_OPBDIV 0x00003000
627#define CPC0_PLLMR0_OPDV 0x00003000
628#define PLL_OPBDIV_1 0x00000000
629#define PLL_OPBDIV_2 0x00001000
630#define PLL_OPBDIV_3 0x00002000
631#define PLL_OPBDIV_4 0x00003000
632 /* EBC divisor */
633#define PLL_EXTBUSDIV 0x00000300
634#define CPC0_PLLMR0_EPDV 0x00000300
635#define PLL_EXTBUSDIV_2 0x00000000
636#define PLL_EXTBUSDIV_3 0x00000100
637#define PLL_EXTBUSDIV_4 0x00000200
638#define PLL_EXTBUSDIV_5 0x00000300
639 /* MAL divisor */
640#define PLL_MALDIV 0x00000030
641#define CPC0_PLLMR0_MPDV 0x00000030
642#define PLL_MALDIV_1 0x00000000
643#define PLL_MALDIV_2 0x00000010
644#define PLL_MALDIV_3 0x00000020
645#define PLL_MALDIV_4 0x00000030
646 /* PCI divisor */
647#define PLL_PCIDIV 0x00000003
648#define CPC0_PLLMR0_PPFD 0x00000003
649#define PLL_PCIDIV_1 0x00000000
650#define PLL_PCIDIV_2 0x00000001
651#define PLL_PCIDIV_3 0x00000002
652#define PLL_PCIDIV_4 0x00000003
653
654/*
200f8c7a 655!-----------------------------------------------------------------------
12f34241
WD		 656! PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
657! assuming a 33.3MHz input clock to the 405EP.
200f8c7a 658!-----------------------------------------------------------------------
12f34241
WD		 659*/
660#define PLLMR0_133_66_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
42d1f039
WD		 661 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
662 PLL_MALDIV_1 | PLL_PCIDIV_4)
12f34241 663#define PLLMR1_133_66_66_33 (PLL_FBKDIV_4 | \
42d1f039
WD		 664 PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
665 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
12f34241 666#define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
42d1f039
WD		 667 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
668 PLL_MALDIV_1 | PLL_PCIDIV_4)
12f34241 669#define PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \
42d1f039
WD		 670 PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
671 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
12f34241 672#define PLLMR0_266_133_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
42d1f039
WD		 673 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
674 PLL_MALDIV_1 | PLL_PCIDIV_4)
12f34241 675#define PLLMR1_266_133_66_33 (PLL_FBKDIV_8 | \
42d1f039
WD		 676 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
677 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
12f34241
WD		 678#if 0 /* test-only */
679#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
680#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
681#endif
682#if 0 /* test-only */
683#define PLLMR0_DEFAULT PLLMR0_200_100_50_33
684#define PLLMR1_DEFAULT PLLMR1_200_100_50_33
685#endif
686#if 1 /* test-only */
687#define PLLMR0_DEFAULT PLLMR0_133_66_66_33
688#define PLLMR1_DEFAULT PLLMR1_133_66_66_33
689#endif
690
691#endif
692#endif
693
5bb226e8
WD		 694#define CFG_OPB_FREQ 50000000
695
12f34241 696#endif /* __CONFIG_H */
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