[people/ms/u-boot.git] / include / configs / R360MPI.h

/*
 * (C) Copyright 2000-2005
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC823		1	/* This is a MPC823 CPU		*/
#define CONFIG_R360MPI		1

#define	CONFIG_SYS_TEXT_BASE	0x40000000

#define CONFIG_LCD
#define CONFIG_MPC8XX_LCD
#undef  CONFIG_EDT32F10
#define CONFIG_SHARP_LQ057Q3DC02

#define	CONFIG_SPLASH_SCREEN

#define MPC8XX_FACT             1		/* Multiply by 1	*/
#define MPC8XX_XIN              50000000	/* 50 MHz in		*/
#define CONFIG_8xx_GCLK_FREQ    50000000 /* define if can't use get_gclk_freq */

#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
#undef	CONFIG_8xx_CONS_SMC2
#undef	CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE		115200	/* console baudrate in bps	*/
#if 0
#define CONFIG_BOOTDELAY	0	/* immediate boot		*/
#else
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
#endif

#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */

#define CONFIG_PREBOOT	"echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"

#undef	CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND							\
	"bootp; "								\
	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
	"bootm"

#undef	CONFIG_SCC1_ENET
#define	CONFIG_SCC2_ENET

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/

#define	CONFIG_MISC_INIT_R		/* have misc_init_r() function	*/

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

#define	CONFIG_CAN_DRIVER		/* CAN Driver support enabled	*/

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE

#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION

#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/

#define CONFIG_HARD_I2C		1	/* To I2C with hardware support */
#undef CONFIG_SYS_I2C_SOFT		/* To I2C with software support */
#define CONFIG_SYS_I2C_SPEED		4700	/* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE		0x7F

#if defined(CONFIG_SYS_I2C_SOFT)
#define CONFIG_SYS_SYS_I2C_SOFT_SPEED	4700 /* I2C speed and slave address */
#define CONFIG_SYS_SYS_I2C_SOFT_SLAVE	0x7F
/*
 * Software (bit-bang) I2C driver configuration
 */
#define PB_SCL			0x00000020	/* PB 26 */
#define PB_SDA			0x00000010	/* PB 27 */

#define I2C_INIT		(immr->im_cpm.cp_pbdir |=  PB_SCL)
#define I2C_ACTIVE		(immr->im_cpm.cp_pbdir |=  PB_SDA)
#define I2C_TRISTATE		(immr->im_cpm.cp_pbdir &= ~PB_SDA)
#define I2C_READ		((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
#define I2C_SDA(bit)		if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
				else    immr->im_cpm.cp_pbdat &= ~PB_SDA
#define I2C_SCL(bit)		if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
				else    immr->im_cpm.cp_pbdat &= ~PB_SCL
#define I2C_DELAY		udelay(50)
#endif /* #define(CONFIG_SYS_I2C_SOFT) */

#define CONFIG_SYS_I2C_LCD_ADDR	0x8	/* LCD Control */
#define CONFIG_SYS_I2C_KEY_ADDR	0x9	/* Keyboard coprocessor */
#define CONFIG_SYS_I2C_TEM_ADDR	0x49	/* Temperature Sensors */


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_BMP
#define CONFIG_CMD_BSP
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IDE
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PCMCIA
#define CONFIG_CMD_SNTP


/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_DEVICE_NULLDEV	1	/* we need the null device	*/
#define CONFIG_SYS_CONSOLE_IS_IN_ENV	1	/* must set console from env	*/

#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#if defined(CONFIG_CMD_KGDB)
#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/

/*
 * JFFS2 partitions
 */
/* No command line, one static partition
 * use all the space starting at offset 3MB*/
#undef CONFIG_CMD_MTDPARTS
#define CONFIG_JFFS2_DEV		"nor0"
#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
#define CONFIG_JFFS2_PART_OFFSET	0x00300000

/* mtdparts command line support */
/*
#define CONFIG_CMD_MTDPARTS
#define MTDIDS_DEFAULT		"nor0=r360-0"
#define MTDPARTS_DEFAULT	"mtdparts=r360-0:-@3m(user)"
*/

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CONFIG_SYS_IMMR		0xFF000000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define	CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH_BASE		0x40000000
#if defined(DEBUG)
#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#else
#define	CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
#endif
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define	CONFIG_ENV_IS_IN_FLASH	1
#define	CONFIG_ENV_OFFSET		0x40000	/* Offset of Environment		*/
#define	CONFIG_ENV_SECT_SIZE	0x20000	/* Total Size of Environment sector	*/
#define	CONFIG_ENV_SIZE		0x4000	/* Used Size of Environment sector	*/
#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
#endif

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#if defined(CONFIG_WATCHDOG)
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
#else
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				11-6
 *-----------------------------------------------------------------------
 * PCMCIA config., multi-function pin tri-state
 */
#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control				11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)

/*-----------------------------------------------------------------------
 * RTCSC - Real-Time Clock Status and Control Register		11-27
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)

/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
 *-----------------------------------------------------------------------
 * Reset PLL lock status sticky bit, timer expired status bit and timer
 * interrupt status bit
 *
 * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
 */
#ifdef	CONFIG_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
#define CONFIG_SYS_PLPRCR							\
		( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
#else			/* up to 50 MHz we use a 1:1 clock */
#define CONFIG_SYS_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
#endif	/* CONFIG_80MHz */

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
#define SCCR_MASK	SCCR_EBDF11
#define CONFIG_SYS_SCCR	(SCCR_TBS     | \
			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
			 SCCR_DFALCD00)

/*-----------------------------------------------------------------------
 * PCMCIA stuff
 *-----------------------------------------------------------------------
 *
 */
#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )

/*-----------------------------------------------------------------------
 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 *-----------------------------------------------------------------------
 */

#if 1
#define CONFIG_IDE_PREINIT	1	/* Use preinit IDE hook */
#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/

#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/

#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/

#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000

#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR

/* Offset for data I/O			*/
#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)

/* Offset for normal register accesses	*/
#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)

/* Offset for alternate registers	*/
#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
#endif

/*-----------------------------------------------------------------------
 *
 *-----------------------------------------------------------------------
 *
 */
#define CONFIG_SYS_DER	0

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */

#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/

/* used to re-map FLASH both when starting from SRAM or FLASH:
 * restrict access enough to keep SRAM working (if any)
 * but not too much to meddle with FLASH accesses
 */
#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
#define CONFIG_SYS_PRELIM_OR_AM	0xFF000000	/* OR addr mask */

/*
 * FLASH timing:
 */
#define CONFIG_SYS_OR_TIMING_FLASH	(OR_ACS_DIV1 | OR_SCY_7_CLK | OR_BI)

#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )


/*
 * BR2 and OR2 (SDRAM)
 *
 */
#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/

#define CONFIG_SYS_PRELIM_OR2_AM	0xF8000000	/* OR addr mask */

/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
#define CONFIG_SYS_OR_TIMING_SDRAM	(OR_ACS_DIV1  | OR_CSNT_SAM | \
				 OR_SCY_0_CLK | OR_G5LS)

#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR2_AM | CONFIG_SYS_OR_TIMING_SDRAM )
#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )

/*
 * BR3 and OR3 (CAN Controller)
 */
#ifdef CONFIG_CAN_DRIVER
#define CONFIG_SYS_CAN_BASE		0xC0000000	/* CAN base address   */
#define CONFIG_SYS_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask */
#define CONFIG_SYS_OR3_CAN		(CONFIG_SYS_CAN_OR_AM | OR_G5LA |OR_BI)
#define CONFIG_SYS_BR3_CAN		((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
				 BR_PS_8 | BR_MS_UPMB | BR_V)
#endif	/* CONFIG_CAN_DRIVER */


/*
 * Memory Periodic Timer Prescaler
 *
 * The Divider for PTA (refresh timer) configuration is based on an
 * example SDRAM configuration (64 MBit, one bank). The adjustment to
 * the number of chip selects (NCS) and the actually needed refresh
 * rate is done by setting MPTPR.
 *
 * PTA is calculated from
 *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
 *
 *	gclk	  CPU clock (not bus clock!)
 *	Trefresh  Refresh cycle * 4 (four word bursts used)
 *
 * 4096  Rows from SDRAM example configuration
 * 1000  factor s -> ms
 *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
 *    4  Number of refresh cycles per period
 *   64  Refresh cycle in ms per number of rows
 * --------------------------------------------
 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
 *
 * 50 MHz => 50.000.000 / Divider =  98
 * 66 Mhz => 66.000.000 / Divider = 129
 * 80 Mhz => 80.000.000 / Divider = 156
 */
#if   defined(CONFIG_80MHz)
#define CONFIG_SYS_MAMR_PTA		156
#elif defined(CONFIG_66MHz)
#define CONFIG_SYS_MAMR_PTA		129
#else		/*   50 MHz */
#define CONFIG_SYS_MAMR_PTA		 98
#endif	/*CONFIG_??MHz */

/*
 * For 16 MBit, refresh rates could be 31.3 us
 * (= 64 ms / 2K = 125 / quad bursts).
 * For a simpler initialization, 15.6 us is used instead.
 *
 * #define CONFIG_SYS_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
 * #define CONFIG_SYS_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
 */
#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/

/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/

/*
 * MAMR settings for SDRAM
 */

/* 8 column SDRAM */
#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
/* 9 column SDRAM */
#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)

#endif	/* __CONFIG_H */
Commit	Line	Data
ce23b153	1	/*
414eec35	2	* (C) Copyright 2000-2005
ce23b153 WD	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
ce23b153 WD	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
ce23b153 WD	6	*/
	7
	8	/*
	9	* board/config.h - configuration options, board specific
	10	*/
	11
	12	#ifndef __CONFIG_H
	13	#define __CONFIG_H
	14
	15	/*
	16	* High Level Configuration Options
	17	* (easy to change)
	18	*/
	19
	20	#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
	21	#define CONFIG_R360MPI 1
	22
2ae18241 WD	23	#define CONFIG_SYS_TEXT_BASE 0x40000000
2ae18241 WD	24
ce23b153	25	#define CONFIG_LCD
59155f4c	26	#define CONFIG_MPC8XX_LCD
ce23b153 WD	27	#undef CONFIG_EDT32F10
	28	#define CONFIG_SHARP_LQ057Q3DC02
	29
d791b1dc WD	30	#define CONFIG_SPLASH_SCREEN
d791b1dc WD	31
ce23b153 WD	32	#define MPC8XX_FACT 1 /* Multiply by 1 */
	33	#define MPC8XX_XIN 50000000 /* 50 MHz in */
	34	#define CONFIG_8xx_GCLK_FREQ 50000000 /* define if can't use get_gclk_freq */
	35
	36	#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
	37	#undef CONFIG_8xx_CONS_SMC2
	38	#undef CONFIG_8xx_CONS_NONE
4a6fd34b	39	#define CONFIG_BAUDRATE 115200 /* console baudrate in bps */
ce23b153	40	#if 0
cb4dbb7b	41	#define CONFIG_BOOTDELAY 0 /* immediate boot */
ce23b153 WD	42	#else
	43	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	44	#endif
	45
	46	#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
	47
32bf3d14	48	#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
ce23b153 WD	49
	50	#undef CONFIG_BOOTARGS
	51	#define CONFIG_BOOTCOMMAND \
53677ef1 WD	52	"bootp; " \
	53	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
	54	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
ce23b153 WD	55	"bootm"
	56
	57	#undef CONFIG_SCC1_ENET
	58	#define CONFIG_SCC2_ENET
	59
	60	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	61	#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
ce23b153 WD	62
	63	#define CONFIG_MISC_INIT_R /* have misc_init_r() function */
	64
	65	#undef CONFIG_WATCHDOG /* watchdog disabled */
	66
4a6fd34b	67	#define CONFIG_CAN_DRIVER /* CAN Driver support enabled */
ce23b153	68
18225e8d JL	69	/*
	70	* BOOTP options
	71	*/
	72	#define CONFIG_BOOTP_SUBNETMASK
	73	#define CONFIG_BOOTP_GATEWAY
	74	#define CONFIG_BOOTP_HOSTNAME
	75	#define CONFIG_BOOTP_BOOTPATH
	76	#define CONFIG_BOOTP_BOOTFILESIZE
ce23b153 WD	77
	78	#define CONFIG_MAC_PARTITION
	79	#define CONFIG_DOS_PARTITION
	80
	81	#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
	82
	83	#define CONFIG_HARD_I2C 1 /* To I2C with hardware support */
ea818dbb	84	#undef CONFIG_SYS_I2C_SOFT /* To I2C with software support */
6d0f6bcf JCPV	85	#define CONFIG_SYS_I2C_SPEED 4700 /* I2C speed and slave address */
6d0f6bcf JCPV	86	#define CONFIG_SYS_I2C_SLAVE 0x7F
ce23b153	87
ea818dbb HS	88	#if defined(CONFIG_SYS_I2C_SOFT)
	89	#define CONFIG_SYS_SYS_I2C_SOFT_SPEED 4700 /* I2C speed and slave address */
	90	#define CONFIG_SYS_SYS_I2C_SOFT_SLAVE 0x7F
ce23b153 WD	91	/*
	92	* Software (bit-bang) I2C driver configuration
	93	*/
	94	#define PB_SCL 0x00000020 /* PB 26 */
	95	#define PB_SDA 0x00000010 /* PB 27 */
	96
	97	#define I2C_INIT (immr->im_cpm.cp_pbdir \|= PB_SCL)
	98	#define I2C_ACTIVE (immr->im_cpm.cp_pbdir \|= PB_SDA)
	99	#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
	100	#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
	101	#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat \|= PB_SDA; \
	102	else immr->im_cpm.cp_pbdat &= ~PB_SDA
	103	#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat \|= PB_SCL; \
	104	else immr->im_cpm.cp_pbdat &= ~PB_SCL
	105	#define I2C_DELAY udelay(50)
ea818dbb	106	#endif /* #define(CONFIG_SYS_I2C_SOFT) */
ce23b153	107
6d0f6bcf JCPV	108	#define CONFIG_SYS_I2C_LCD_ADDR 0x8 /* LCD Control */
	109	#define CONFIG_SYS_I2C_KEY_ADDR 0x9 /* Keyboard coprocessor */
	110	#define CONFIG_SYS_I2C_TEM_ADDR 0x49 /* Temperature Sensors */
ce23b153	111
e9a0f8f1 JL	112
	113	/*
	114	* Command line configuration.
	115	*/
	116	#include <config_cmd_default.h>
	117
	118	#define CONFIG_CMD_BMP
	119	#define CONFIG_CMD_BSP
	120	#define CONFIG_CMD_DATE
	121	#define CONFIG_CMD_DHCP
	122	#define CONFIG_CMD_I2C
	123	#define CONFIG_CMD_IDE
	124	#define CONFIG_CMD_JFFS2
	125	#define CONFIG_CMD_NFS
	126	#define CONFIG_CMD_PCMCIA
	127	#define CONFIG_CMD_SNTP
	128
ce23b153 WD	129
	130	/*
	131	* Miscellaneous configurable options
	132	*/
6d0f6bcf JCPV	133	#define CONFIG_SYS_DEVICE_NULLDEV 1 /* we need the null device */
6d0f6bcf JCPV	134	#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 /* must set console from env */
cb4dbb7b	135
6d0f6bcf	136	#define CONFIG_SYS_LONGHELP /* undef to save memory */
e9a0f8f1	137	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	138	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
ce23b153	139	#else
6d0f6bcf	140	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
ce23b153	141	#endif
6d0f6bcf JCPV	142	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	143	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	144	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
ce23b153	145
6d0f6bcf JCPV	146	#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
6d0f6bcf JCPV	147	#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
ce23b153	148
6d0f6bcf	149	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
ce23b153	150
700a0c64 WD	151	/*
	152	* JFFS2 partitions
	153	*/
	154	/* No command line, one static partition
	155	* use all the space starting at offset 3MB*/
68d7d651	156	#undef CONFIG_CMD_MTDPARTS
700a0c64 WD	157	#define CONFIG_JFFS2_DEV "nor0"
	158	#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
	159	#define CONFIG_JFFS2_PART_OFFSET 0x00300000
	160
	161	/* mtdparts command line support */
	162	/*
68d7d651	163	#define CONFIG_CMD_MTDPARTS
700a0c64 WD	164	#define MTDIDS_DEFAULT "nor0=r360-0"
	165	#define MTDPARTS_DEFAULT "mtdparts=r360-0:-@3m(user)"
	166	*/
cb4dbb7b	167
ce23b153 WD	168	/*
	169	* Low Level Configuration Settings
	170	* (address mappings, register initial values, etc.)
	171	* You should know what you are doing if you make changes here.
	172	*/
	173	/*-----------------------------------------------------------------------
	174	* Internal Memory Mapped Register
	175	*/
6d0f6bcf	176	#define CONFIG_SYS_IMMR 0xFF000000
ce23b153 WD	177
	178	/*-----------------------------------------------------------------------
	179	* Definitions for initial stack pointer and data area (in DPRAM)
	180	*/
6d0f6bcf	181	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
553f0982	182	#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
25ddd1fb	183	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	184	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
ce23b153 WD	185
	186	/*-----------------------------------------------------------------------
	187	* Start addresses for the final memory configuration
	188	* (Set up by the startup code)
6d0f6bcf	189	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
ce23b153	190	*/
6d0f6bcf JCPV	191	#define CONFIG_SYS_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	192	#define CONFIG_SYS_FLASH_BASE 0x40000000
ce23b153	193	#if defined(DEBUG)
6d0f6bcf	194	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
ce23b153	195	#else
6d0f6bcf	196	#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
ce23b153	197	#endif
6d0f6bcf JCPV	198	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
6d0f6bcf JCPV	199	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
ce23b153 WD	200
	201	/*
	202	* For booting Linux, the board info and command line data
	203	* have to be in the first 8 MB of memory, since this is
	204	* the maximum mapped by the Linux kernel during initialization.
	205	*/
6d0f6bcf	206	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
ce23b153 WD	207
	208	/*-----------------------------------------------------------------------
	209	* FLASH organization
	210	*/
6d0f6bcf JCPV	211	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
6d0f6bcf JCPV	212	#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
ce23b153	213
6d0f6bcf JCPV	214	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	215	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
ce23b153	216
5a1aceb0	217	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	218	#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment */
	219	#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment sector */
	220	#define CONFIG_ENV_SIZE 0x4000 /* Used Size of Environment sector */
6d0f6bcf	221	#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
ce23b153 WD	222
	223	/*-----------------------------------------------------------------------
	224	* Cache Configuration
	225	*/
6d0f6bcf	226	#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
e9a0f8f1	227	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	228	#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
ce23b153 WD	229	#endif
	230
	231	/*-----------------------------------------------------------------------
	232	* SYPCR - System Protection Control 11-9
	233	* SYPCR can only be written once after reset!
	234	*-----------------------------------------------------------------------
	235	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
	236	*/
	237	#if defined(CONFIG_WATCHDOG)
6d0f6bcf	238	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
ce23b153 WD	239	SYPCR_SWE \| SYPCR_SWRI\| SYPCR_SWP)
ce23b153 WD	240	#else
6d0f6bcf	241	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| SYPCR_SWP)
ce23b153 WD	242	#endif
	243
	244	/*-----------------------------------------------------------------------
	245	* SIUMCR - SIU Module Configuration 11-6
	246	*-----------------------------------------------------------------------
	247	* PCMCIA config., multi-function pin tri-state
	248	*/
6d0f6bcf	249	#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 \| SIUMCR_DBPC00 \| SIUMCR_MLRC01)
ce23b153 WD	250
	251	/*-----------------------------------------------------------------------
	252	* TBSCR - Time Base Status and Control 11-26
	253	*-----------------------------------------------------------------------
	254	* Clear Reference Interrupt Status, Timebase freezing enabled
	255	*/
6d0f6bcf	256	#define CONFIG_SYS_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBE)
ce23b153 WD	257
	258	/*-----------------------------------------------------------------------
	259	* RTCSC - Real-Time Clock Status and Control Register 11-27
	260	*-----------------------------------------------------------------------
	261	*/
6d0f6bcf	262	#define CONFIG_SYS_RTCSC (RTCSC_SEC \| RTCSC_ALR \| RTCSC_RTF\| RTCSC_RTE)
ce23b153 WD	263
	264	/*-----------------------------------------------------------------------
	265	* PISCR - Periodic Interrupt Status and Control 11-31
	266	*-----------------------------------------------------------------------
	267	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
	268	*/
6d0f6bcf	269	#define CONFIG_SYS_PISCR (PISCR_PS \| PISCR_PITF)
ce23b153 WD	270
	271	/*-----------------------------------------------------------------------
	272	* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
	273	*-----------------------------------------------------------------------
	274	* Reset PLL lock status sticky bit, timer expired status bit and timer
	275	* interrupt status bit
	276	*
	277	* If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
	278	*/
	279	#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
6d0f6bcf	280	#define CONFIG_SYS_PLPRCR \
ce23b153 WD	281	( (5-1)<<PLPRCR_MF_SHIFT \| PLPRCR_TEXPS \| PLPRCR_TMIST )
ce23b153 WD	282	#else /* up to 50 MHz we use a 1:1 clock */
6d0f6bcf	283	#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS \| PLPRCR_TEXPS \| PLPRCR_TMIST)
ce23b153 WD	284	#endif /* CONFIG_80MHz */
	285
	286	/*-----------------------------------------------------------------------
	287	* SCCR - System Clock and reset Control Register 15-27
	288	*-----------------------------------------------------------------------
	289	* Set clock output, timebase and RTC source and divider,
	290	* power management and some other internal clocks
	291	*/
	292	#define SCCR_MASK SCCR_EBDF11
6d0f6bcf	293	#define CONFIG_SYS_SCCR (SCCR_TBS \| \
ce23b153 WD	294	SCCR_COM00 \| SCCR_DFSYNC00 \| SCCR_DFBRG00 \| \
	295	SCCR_DFNL000 \| SCCR_DFNH000 \| SCCR_DFLCD000 \| \
	296	SCCR_DFALCD00)
	297
	298	/*-----------------------------------------------------------------------
	299	* PCMCIA stuff
	300	*-----------------------------------------------------------------------
	301	*
	302	*/
6d0f6bcf JCPV	303	#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
	304	#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
	305	#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
	306	#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
	307	#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
	308	#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
	309	#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
	310	#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
ce23b153 WD	311
	312	/*-----------------------------------------------------------------------
	313	* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
	314	*-----------------------------------------------------------------------
	315	*/
	316
	317	#if 1
8d1165e1	318	#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
ce23b153 WD	319	#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
	320
	321	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
	322	#undef CONFIG_IDE_LED /* LED for ide not supported */
	323	#undef CONFIG_IDE_RESET /* reset for ide not supported */
	324
6d0f6bcf JCPV	325	#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
6d0f6bcf JCPV	326	#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
ce23b153	327
6d0f6bcf	328	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
ce23b153	329
6d0f6bcf	330	#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
ce23b153 WD	331
ce23b153 WD	332	/* Offset for data I/O */
6d0f6bcf	333	#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
ce23b153 WD	334
ce23b153 WD	335	/* Offset for normal register accesses */
6d0f6bcf	336	#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
ce23b153 WD	337
ce23b153 WD	338	/* Offset for alternate registers */
6d0f6bcf	339	#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
ce23b153 WD	340	#endif
	341
	342	/*-----------------------------------------------------------------------
	343	*
	344	*-----------------------------------------------------------------------
	345	*
	346	*/
6d0f6bcf	347	#define CONFIG_SYS_DER 0
ce23b153 WD	348
	349	/*
	350	* Init Memory Controller:
	351	*
	352	* BR0/1 and OR0/1 (FLASH)
	353	*/
	354
	355	#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
	356
	357	/* used to re-map FLASH both when starting from SRAM or FLASH:
	358	* restrict access enough to keep SRAM working (if any)
	359	* but not too much to meddle with FLASH accesses
	360	*/
6d0f6bcf JCPV	361	#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
6d0f6bcf JCPV	362	#define CONFIG_SYS_PRELIM_OR_AM 0xFF000000 /* OR addr mask */
ce23b153 WD	363
	364	/*
	365	* FLASH timing:
	366	*/
6d0f6bcf	367	#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 \| OR_SCY_7_CLK \| OR_BI)
ce23b153	368
6d0f6bcf JCPV	369	#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM \| CONFIG_SYS_OR_TIMING_FLASH)
	370	#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \| CONFIG_SYS_OR_TIMING_FLASH)
	371	#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) \| BR_PS_16 \| BR_V )
ce23b153 WD	372
	373
	374	/*
4a6fd34b	375	* BR2 and OR2 (SDRAM)
ce23b153 WD	376	*
ce23b153 WD	377	*/
4a6fd34b	378	#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
ce23b153 WD	379	#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
ce23b153 WD	380
6d0f6bcf	381	#define CONFIG_SYS_PRELIM_OR2_AM 0xF8000000 /* OR addr mask */
ce23b153 WD	382
ce23b153 WD	383	/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
6d0f6bcf	384	#define CONFIG_SYS_OR_TIMING_SDRAM (OR_ACS_DIV1 \| OR_CSNT_SAM \| \
ce23b153 WD	385	OR_SCY_0_CLK \| OR_G5LS)
ce23b153 WD	386
6d0f6bcf JCPV	387	#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR2_AM \| CONFIG_SYS_OR_TIMING_SDRAM )
6d0f6bcf JCPV	388	#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) \| BR_MS_UPMA \| BR_V )
4a6fd34b WD	389
	390	/*
	391	* BR3 and OR3 (CAN Controller)
	392	*/
	393	#ifdef CONFIG_CAN_DRIVER
6d0f6bcf JCPV	394	#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN base address */
	395	#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
	396	#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM \| OR_G5LA \|OR_BI)
	397	#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) \| \
4a6fd34b WD	398	BR_PS_8 \| BR_MS_UPMB \| BR_V)
4a6fd34b WD	399	#endif /* CONFIG_CAN_DRIVER */
ce23b153 WD	400
	401
	402	/*
	403	* Memory Periodic Timer Prescaler
	404	*
	405	* The Divider for PTA (refresh timer) configuration is based on an
	406	* example SDRAM configuration (64 MBit, one bank). The adjustment to
	407	* the number of chip selects (NCS) and the actually needed refresh
	408	* rate is done by setting MPTPR.
	409	*
	410	* PTA is calculated from
	411	* PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
	412	*
	413	* gclk CPU clock (not bus clock!)
	414	* Trefresh Refresh cycle * 4 (four word bursts used)
	415	*
	416	* 4096 Rows from SDRAM example configuration
	417	* 1000 factor s -> ms
	418	* 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
	419	* 4 Number of refresh cycles per period
	420	* 64 Refresh cycle in ms per number of rows
	421	* --------------------------------------------
	422	* Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
	423	*
	424	* 50 MHz => 50.000.000 / Divider = 98
	425	* 66 Mhz => 66.000.000 / Divider = 129
	426	* 80 Mhz => 80.000.000 / Divider = 156
	427	*/
	428	#if defined(CONFIG_80MHz)
6d0f6bcf	429	#define CONFIG_SYS_MAMR_PTA 156
ce23b153	430	#elif defined(CONFIG_66MHz)
6d0f6bcf	431	#define CONFIG_SYS_MAMR_PTA 129
ce23b153	432	#else /* 50 MHz */
6d0f6bcf	433	#define CONFIG_SYS_MAMR_PTA 98
ce23b153 WD	434	#endif /CONFIG_??MHz /
	435
	436	/*
	437	* For 16 MBit, refresh rates could be 31.3 us
	438	* (= 64 ms / 2K = 125 / quad bursts).
	439	* For a simpler initialization, 15.6 us is used instead.
	440	*
6d0f6bcf JCPV	441	* #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
6d0f6bcf JCPV	442	* #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
ce23b153	443	*/
6d0f6bcf JCPV	444	#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
6d0f6bcf JCPV	445	#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
ce23b153 WD	446
ce23b153 WD	447	/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
6d0f6bcf JCPV	448	#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
6d0f6bcf JCPV	449	#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
ce23b153 WD	450
	451	/*
	452	* MAMR settings for SDRAM
	453	*/
	454
	455	/* 8 column SDRAM */
6d0f6bcf	456	#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
ce23b153 WD	457	MAMR_AMA_TYPE_0 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A11 \| \
	458	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
	459	/* 9 column SDRAM */
6d0f6bcf	460	#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
ce23b153 WD	461	MAMR_AMA_TYPE_1 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A10 \| \
	462	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
	463
ce23b153	464	#endif /* __CONFIG_H */