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ce23b153 | 1 | /* |
414eec35 | 2 | * (C) Copyright 2000-2005 |
ce23b153 WD |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * board/config.h - configuration options, board specific | |
26 | */ | |
27 | ||
28 | #ifndef __CONFIG_H | |
29 | #define __CONFIG_H | |
30 | ||
31 | /* | |
32 | * High Level Configuration Options | |
33 | * (easy to change) | |
34 | */ | |
35 | ||
36 | #define CONFIG_MPC823 1 /* This is a MPC823 CPU */ | |
37 | #define CONFIG_R360MPI 1 | |
38 | ||
2ae18241 WD |
39 | #define CONFIG_SYS_TEXT_BASE 0x40000000 |
40 | ||
ce23b153 WD |
41 | #define CONFIG_LCD |
42 | #undef CONFIG_EDT32F10 | |
43 | #define CONFIG_SHARP_LQ057Q3DC02 | |
44 | ||
d791b1dc WD |
45 | #define CONFIG_SPLASH_SCREEN |
46 | ||
ce23b153 WD |
47 | #define MPC8XX_FACT 1 /* Multiply by 1 */ |
48 | #define MPC8XX_XIN 50000000 /* 50 MHz in */ | |
49 | #define CONFIG_8xx_GCLK_FREQ 50000000 /* define if can't use get_gclk_freq */ | |
50 | ||
51 | #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ | |
52 | #undef CONFIG_8xx_CONS_SMC2 | |
53 | #undef CONFIG_8xx_CONS_NONE | |
4a6fd34b | 54 | #define CONFIG_BAUDRATE 115200 /* console baudrate in bps */ |
ce23b153 | 55 | #if 0 |
cb4dbb7b | 56 | #define CONFIG_BOOTDELAY 0 /* immediate boot */ |
ce23b153 WD |
57 | #else |
58 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
59 | #endif | |
60 | ||
61 | #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ | |
62 | ||
32bf3d14 | 63 | #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" |
ce23b153 WD |
64 | |
65 | #undef CONFIG_BOOTARGS | |
66 | #define CONFIG_BOOTCOMMAND \ | |
53677ef1 WD |
67 | "bootp; " \ |
68 | "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ | |
69 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ | |
ce23b153 WD |
70 | "bootm" |
71 | ||
72 | #undef CONFIG_SCC1_ENET | |
73 | #define CONFIG_SCC2_ENET | |
74 | ||
75 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 76 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
ce23b153 WD |
77 | |
78 | #define CONFIG_MISC_INIT_R /* have misc_init_r() function */ | |
79 | ||
80 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
81 | ||
4a6fd34b | 82 | #define CONFIG_CAN_DRIVER /* CAN Driver support enabled */ |
ce23b153 | 83 | |
18225e8d JL |
84 | /* |
85 | * BOOTP options | |
86 | */ | |
87 | #define CONFIG_BOOTP_SUBNETMASK | |
88 | #define CONFIG_BOOTP_GATEWAY | |
89 | #define CONFIG_BOOTP_HOSTNAME | |
90 | #define CONFIG_BOOTP_BOOTPATH | |
91 | #define CONFIG_BOOTP_BOOTFILESIZE | |
ce23b153 WD |
92 | |
93 | #define CONFIG_MAC_PARTITION | |
94 | #define CONFIG_DOS_PARTITION | |
95 | ||
96 | #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ | |
97 | ||
98 | #define CONFIG_HARD_I2C 1 /* To I2C with hardware support */ | |
99 | #undef CONFIG_SORT_I2C /* To I2C with software support */ | |
6d0f6bcf JCPV |
100 | #define CONFIG_SYS_I2C_SPEED 4700 /* I2C speed and slave address */ |
101 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
ce23b153 WD |
102 | |
103 | /* | |
104 | * Software (bit-bang) I2C driver configuration | |
105 | */ | |
106 | #define PB_SCL 0x00000020 /* PB 26 */ | |
107 | #define PB_SDA 0x00000010 /* PB 27 */ | |
108 | ||
109 | #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) | |
110 | #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) | |
111 | #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) | |
112 | #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) | |
113 | #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ | |
114 | else immr->im_cpm.cp_pbdat &= ~PB_SDA | |
115 | #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ | |
116 | else immr->im_cpm.cp_pbdat &= ~PB_SCL | |
117 | #define I2C_DELAY udelay(50) | |
118 | ||
6d0f6bcf JCPV |
119 | #define CONFIG_SYS_I2C_LCD_ADDR 0x8 /* LCD Control */ |
120 | #define CONFIG_SYS_I2C_KEY_ADDR 0x9 /* Keyboard coprocessor */ | |
121 | #define CONFIG_SYS_I2C_TEM_ADDR 0x49 /* Temperature Sensors */ | |
ce23b153 | 122 | |
e9a0f8f1 JL |
123 | |
124 | /* | |
125 | * Command line configuration. | |
126 | */ | |
127 | #include <config_cmd_default.h> | |
128 | ||
129 | #define CONFIG_CMD_BMP | |
130 | #define CONFIG_CMD_BSP | |
131 | #define CONFIG_CMD_DATE | |
132 | #define CONFIG_CMD_DHCP | |
133 | #define CONFIG_CMD_I2C | |
134 | #define CONFIG_CMD_IDE | |
135 | #define CONFIG_CMD_JFFS2 | |
136 | #define CONFIG_CMD_NFS | |
137 | #define CONFIG_CMD_PCMCIA | |
138 | #define CONFIG_CMD_SNTP | |
139 | ||
ce23b153 WD |
140 | |
141 | /* | |
142 | * Miscellaneous configurable options | |
143 | */ | |
6d0f6bcf JCPV |
144 | #define CONFIG_SYS_DEVICE_NULLDEV 1 /* we need the null device */ |
145 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 /* must set console from env */ | |
cb4dbb7b | 146 | |
6d0f6bcf JCPV |
147 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
148 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
e9a0f8f1 | 149 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 150 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
ce23b153 | 151 | #else |
6d0f6bcf | 152 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
ce23b153 | 153 | #endif |
6d0f6bcf JCPV |
154 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
155 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
156 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
ce23b153 | 157 | |
6d0f6bcf JCPV |
158 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
159 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
ce23b153 | 160 | |
6d0f6bcf | 161 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
ce23b153 | 162 | |
6d0f6bcf | 163 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
ce23b153 | 164 | |
6d0f6bcf | 165 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
ce23b153 | 166 | |
700a0c64 WD |
167 | /* |
168 | * JFFS2 partitions | |
169 | */ | |
170 | /* No command line, one static partition | |
171 | * use all the space starting at offset 3MB*/ | |
68d7d651 | 172 | #undef CONFIG_CMD_MTDPARTS |
700a0c64 WD |
173 | #define CONFIG_JFFS2_DEV "nor0" |
174 | #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF | |
175 | #define CONFIG_JFFS2_PART_OFFSET 0x00300000 | |
176 | ||
177 | /* mtdparts command line support */ | |
178 | /* | |
68d7d651 | 179 | #define CONFIG_CMD_MTDPARTS |
700a0c64 WD |
180 | #define MTDIDS_DEFAULT "nor0=r360-0" |
181 | #define MTDPARTS_DEFAULT "mtdparts=r360-0:-@3m(user)" | |
182 | */ | |
cb4dbb7b | 183 | |
ce23b153 WD |
184 | /* |
185 | * Low Level Configuration Settings | |
186 | * (address mappings, register initial values, etc.) | |
187 | * You should know what you are doing if you make changes here. | |
188 | */ | |
189 | /*----------------------------------------------------------------------- | |
190 | * Internal Memory Mapped Register | |
191 | */ | |
6d0f6bcf | 192 | #define CONFIG_SYS_IMMR 0xFF000000 |
ce23b153 WD |
193 | |
194 | /*----------------------------------------------------------------------- | |
195 | * Definitions for initial stack pointer and data area (in DPRAM) | |
196 | */ | |
6d0f6bcf | 197 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
553f0982 | 198 | #define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ |
25ddd1fb | 199 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 200 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
ce23b153 WD |
201 | |
202 | /*----------------------------------------------------------------------- | |
203 | * Start addresses for the final memory configuration | |
204 | * (Set up by the startup code) | |
6d0f6bcf | 205 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
ce23b153 | 206 | */ |
6d0f6bcf JCPV |
207 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
208 | #define CONFIG_SYS_FLASH_BASE 0x40000000 | |
ce23b153 | 209 | #if defined(DEBUG) |
6d0f6bcf | 210 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
ce23b153 | 211 | #else |
6d0f6bcf | 212 | #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ |
ce23b153 | 213 | #endif |
6d0f6bcf JCPV |
214 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
215 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
ce23b153 WD |
216 | |
217 | /* | |
218 | * For booting Linux, the board info and command line data | |
219 | * have to be in the first 8 MB of memory, since this is | |
220 | * the maximum mapped by the Linux kernel during initialization. | |
221 | */ | |
6d0f6bcf | 222 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
ce23b153 WD |
223 | |
224 | /*----------------------------------------------------------------------- | |
225 | * FLASH organization | |
226 | */ | |
6d0f6bcf JCPV |
227 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
228 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ | |
ce23b153 | 229 | |
6d0f6bcf JCPV |
230 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
231 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
ce23b153 | 232 | |
5a1aceb0 | 233 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
234 | #define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment */ |
235 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment sector */ | |
236 | #define CONFIG_ENV_SIZE 0x4000 /* Used Size of Environment sector */ | |
6d0f6bcf | 237 | #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ |
ce23b153 WD |
238 | |
239 | /*----------------------------------------------------------------------- | |
240 | * Cache Configuration | |
241 | */ | |
6d0f6bcf | 242 | #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
e9a0f8f1 | 243 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 244 | #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
ce23b153 WD |
245 | #endif |
246 | ||
247 | /*----------------------------------------------------------------------- | |
248 | * SYPCR - System Protection Control 11-9 | |
249 | * SYPCR can only be written once after reset! | |
250 | *----------------------------------------------------------------------- | |
251 | * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze | |
252 | */ | |
253 | #if defined(CONFIG_WATCHDOG) | |
6d0f6bcf | 254 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
ce23b153 WD |
255 | SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
256 | #else | |
6d0f6bcf | 257 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
ce23b153 WD |
258 | #endif |
259 | ||
260 | /*----------------------------------------------------------------------- | |
261 | * SIUMCR - SIU Module Configuration 11-6 | |
262 | *----------------------------------------------------------------------- | |
263 | * PCMCIA config., multi-function pin tri-state | |
264 | */ | |
6d0f6bcf | 265 | #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
ce23b153 WD |
266 | |
267 | /*----------------------------------------------------------------------- | |
268 | * TBSCR - Time Base Status and Control 11-26 | |
269 | *----------------------------------------------------------------------- | |
270 | * Clear Reference Interrupt Status, Timebase freezing enabled | |
271 | */ | |
6d0f6bcf | 272 | #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) |
ce23b153 WD |
273 | |
274 | /*----------------------------------------------------------------------- | |
275 | * RTCSC - Real-Time Clock Status and Control Register 11-27 | |
276 | *----------------------------------------------------------------------- | |
277 | */ | |
6d0f6bcf | 278 | #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) |
ce23b153 WD |
279 | |
280 | /*----------------------------------------------------------------------- | |
281 | * PISCR - Periodic Interrupt Status and Control 11-31 | |
282 | *----------------------------------------------------------------------- | |
283 | * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled | |
284 | */ | |
6d0f6bcf | 285 | #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) |
ce23b153 WD |
286 | |
287 | /*----------------------------------------------------------------------- | |
288 | * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 | |
289 | *----------------------------------------------------------------------- | |
290 | * Reset PLL lock status sticky bit, timer expired status bit and timer | |
291 | * interrupt status bit | |
292 | * | |
293 | * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! | |
294 | */ | |
295 | #ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */ | |
6d0f6bcf | 296 | #define CONFIG_SYS_PLPRCR \ |
ce23b153 WD |
297 | ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST ) |
298 | #else /* up to 50 MHz we use a 1:1 clock */ | |
6d0f6bcf | 299 | #define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) |
ce23b153 WD |
300 | #endif /* CONFIG_80MHz */ |
301 | ||
302 | /*----------------------------------------------------------------------- | |
303 | * SCCR - System Clock and reset Control Register 15-27 | |
304 | *----------------------------------------------------------------------- | |
305 | * Set clock output, timebase and RTC source and divider, | |
306 | * power management and some other internal clocks | |
307 | */ | |
308 | #define SCCR_MASK SCCR_EBDF11 | |
6d0f6bcf | 309 | #define CONFIG_SYS_SCCR (SCCR_TBS | \ |
ce23b153 WD |
310 | SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ |
311 | SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ | |
312 | SCCR_DFALCD00) | |
313 | ||
314 | /*----------------------------------------------------------------------- | |
315 | * PCMCIA stuff | |
316 | *----------------------------------------------------------------------- | |
317 | * | |
318 | */ | |
6d0f6bcf JCPV |
319 | #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) |
320 | #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) | |
321 | #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) | |
322 | #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) | |
323 | #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) | |
324 | #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) | |
325 | #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) | |
326 | #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) | |
ce23b153 WD |
327 | |
328 | /*----------------------------------------------------------------------- | |
329 | * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) | |
330 | *----------------------------------------------------------------------- | |
331 | */ | |
332 | ||
333 | #if 1 | |
334 | #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ | |
335 | ||
336 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ | |
337 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
338 | #undef CONFIG_IDE_RESET /* reset for ide not supported */ | |
339 | ||
6d0f6bcf JCPV |
340 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
341 | #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ | |
ce23b153 | 342 | |
6d0f6bcf | 343 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
ce23b153 | 344 | |
6d0f6bcf | 345 | #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR |
ce23b153 WD |
346 | |
347 | /* Offset for data I/O */ | |
6d0f6bcf | 348 | #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
ce23b153 WD |
349 | |
350 | /* Offset for normal register accesses */ | |
6d0f6bcf | 351 | #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
ce23b153 WD |
352 | |
353 | /* Offset for alternate registers */ | |
6d0f6bcf | 354 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 |
ce23b153 WD |
355 | #endif |
356 | ||
357 | /*----------------------------------------------------------------------- | |
358 | * | |
359 | *----------------------------------------------------------------------- | |
360 | * | |
361 | */ | |
6d0f6bcf | 362 | #define CONFIG_SYS_DER 0 |
ce23b153 WD |
363 | |
364 | /* | |
365 | * Init Memory Controller: | |
366 | * | |
367 | * BR0/1 and OR0/1 (FLASH) | |
368 | */ | |
369 | ||
370 | #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ | |
371 | ||
372 | /* used to re-map FLASH both when starting from SRAM or FLASH: | |
373 | * restrict access enough to keep SRAM working (if any) | |
374 | * but not too much to meddle with FLASH accesses | |
375 | */ | |
6d0f6bcf JCPV |
376 | #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ |
377 | #define CONFIG_SYS_PRELIM_OR_AM 0xFF000000 /* OR addr mask */ | |
ce23b153 WD |
378 | |
379 | /* | |
380 | * FLASH timing: | |
381 | */ | |
6d0f6bcf | 382 | #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_SCY_7_CLK | OR_BI) |
ce23b153 | 383 | |
6d0f6bcf JCPV |
384 | #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
385 | #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) | |
386 | #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) | |
ce23b153 WD |
387 | |
388 | ||
389 | /* | |
4a6fd34b | 390 | * BR2 and OR2 (SDRAM) |
ce23b153 WD |
391 | * |
392 | */ | |
4a6fd34b | 393 | #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ |
ce23b153 WD |
394 | #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ |
395 | ||
6d0f6bcf | 396 | #define CONFIG_SYS_PRELIM_OR2_AM 0xF8000000 /* OR addr mask */ |
ce23b153 WD |
397 | |
398 | /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ | |
6d0f6bcf | 399 | #define CONFIG_SYS_OR_TIMING_SDRAM (OR_ACS_DIV1 | OR_CSNT_SAM | \ |
ce23b153 WD |
400 | OR_SCY_0_CLK | OR_G5LS) |
401 | ||
6d0f6bcf JCPV |
402 | #define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR2_AM | CONFIG_SYS_OR_TIMING_SDRAM ) |
403 | #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) | |
4a6fd34b WD |
404 | |
405 | /* | |
406 | * BR3 and OR3 (CAN Controller) | |
407 | */ | |
408 | #ifdef CONFIG_CAN_DRIVER | |
6d0f6bcf JCPV |
409 | #define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN base address */ |
410 | #define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ | |
411 | #define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA |OR_BI) | |
412 | #define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ | |
4a6fd34b WD |
413 | BR_PS_8 | BR_MS_UPMB | BR_V) |
414 | #endif /* CONFIG_CAN_DRIVER */ | |
ce23b153 WD |
415 | |
416 | ||
417 | /* | |
418 | * Memory Periodic Timer Prescaler | |
419 | * | |
420 | * The Divider for PTA (refresh timer) configuration is based on an | |
421 | * example SDRAM configuration (64 MBit, one bank). The adjustment to | |
422 | * the number of chip selects (NCS) and the actually needed refresh | |
423 | * rate is done by setting MPTPR. | |
424 | * | |
425 | * PTA is calculated from | |
426 | * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) | |
427 | * | |
428 | * gclk CPU clock (not bus clock!) | |
429 | * Trefresh Refresh cycle * 4 (four word bursts used) | |
430 | * | |
431 | * 4096 Rows from SDRAM example configuration | |
432 | * 1000 factor s -> ms | |
433 | * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration | |
434 | * 4 Number of refresh cycles per period | |
435 | * 64 Refresh cycle in ms per number of rows | |
436 | * -------------------------------------------- | |
437 | * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 | |
438 | * | |
439 | * 50 MHz => 50.000.000 / Divider = 98 | |
440 | * 66 Mhz => 66.000.000 / Divider = 129 | |
441 | * 80 Mhz => 80.000.000 / Divider = 156 | |
442 | */ | |
443 | #if defined(CONFIG_80MHz) | |
6d0f6bcf | 444 | #define CONFIG_SYS_MAMR_PTA 156 |
ce23b153 | 445 | #elif defined(CONFIG_66MHz) |
6d0f6bcf | 446 | #define CONFIG_SYS_MAMR_PTA 129 |
ce23b153 | 447 | #else /* 50 MHz */ |
6d0f6bcf | 448 | #define CONFIG_SYS_MAMR_PTA 98 |
ce23b153 WD |
449 | #endif /*CONFIG_??MHz */ |
450 | ||
451 | /* | |
452 | * For 16 MBit, refresh rates could be 31.3 us | |
453 | * (= 64 ms / 2K = 125 / quad bursts). | |
454 | * For a simpler initialization, 15.6 us is used instead. | |
455 | * | |
6d0f6bcf JCPV |
456 | * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks |
457 | * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank | |
ce23b153 | 458 | */ |
6d0f6bcf JCPV |
459 | #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ |
460 | #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ | |
ce23b153 WD |
461 | |
462 | /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ | |
6d0f6bcf JCPV |
463 | #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ |
464 | #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ | |
ce23b153 WD |
465 | |
466 | /* | |
467 | * MAMR settings for SDRAM | |
468 | */ | |
469 | ||
470 | /* 8 column SDRAM */ | |
6d0f6bcf | 471 | #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
ce23b153 WD |
472 | MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ |
473 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
474 | /* 9 column SDRAM */ | |
6d0f6bcf | 475 | #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
ce23b153 WD |
476 | MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ |
477 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
478 | ||
ce23b153 | 479 | #endif /* __CONFIG_H */ |