[people/ms/u-boot.git] / include / configs / RBC823.h

/*
 * (C) Copyright 2000, 2001
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * Modified by Udi Finkelstein udif@udif.com
 * For the RBC823 board.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC823		1	/* This is a MPC823 CPU		*/
#define CONFIG_RBC823		1	/* ...on a RBC823 module	*/

#define	CONFIG_SYS_TEXT_BASE	0xFFF00000

#if 0
#define DEBUG			1
#define CONFIG_LAST_STAGE_INIT
#endif
#define CONFIG_KEYBOARD		1	/* This board has a custom keybpard */
#define CONFIG_LCD		1	/* use LCD controller ...	*/
#define CONFIG_MPC8XX_LCD
#define CONFIG_HITACHI_SP19X001_Z1A	/* The LCD type we use */

#define	CONFIG_8xx_CONS_SMC2	1	/* Console is on SMC2		*/
#undef	CONFIG_8xx_CONS_SMC1
#undef	CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
#if 1
#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
#else
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
#endif

#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
#define CONFIG_8xx_GCLK_FREQ    48000000L

#define CONFIG_PREBOOT	"echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"

#undef	CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND							\
	"bootp; "								\
	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
	"bootm"

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

#define CONFIG_STATUS_LED	1	/* Status LED enabled		*/

#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE


#undef CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION

#undef	CONFIG_RTC_MPC8xx		/* don't use internal RTC of MPC8xx (no battery)	*/

#define CONFIG_HARD_I2C
#define CONFIG_SYS_I2C_SPEED 40000
#define CONFIG_SYS_I2C_SLAVE 0xfe
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
#define CONFIG_SYS_EEPROM_WRITE_BITS		4
#define CONFIG_SYS_EEPROM_WRITE_DELAY_MS	10

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_BEDBUG
#define CONFIG_CMD_BMP
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_CDP
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FAT
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IMMAP
#define CONFIG_CMD_KGDB
#define CONFIG_CMD_PING
#define CONFIG_CMD_PORTIO
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SAVES
#define CONFIG_CMD_SDRAM

#undef CONFIG_CMD_SETGETDCR
#undef CONFIG_CMD_XIMG

/*
 * Miscellaneous configurable options
 */
#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB)
#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define	CONFIG_SYS_LOAD_ADDR		0x0100000	/* default load address	*/

#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CONFIG_SYS_IMMR		0xFF000000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define	CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH_BASE		0xFFF00000
#if defined(DEBUG)
#define	CONFIG_SYS_MONITOR_LEN		(384 << 10)	/* Reserve 256 kB for Monitor	*/
#else
#define	CONFIG_SYS_MONITOR_LEN		(384 << 10)	/* Reserve 192 kB for Monitor	*/
#endif
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	67	/* max number of sectors on one chip	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define	CONFIG_ENV_IS_IN_FLASH	1
#define	CONFIG_ENV_OFFSET		0x10000	/*   Offset   of Environment Sector	*/
#define	CONFIG_ENV_SIZE		0x10000	/* Total Size of Environment Sector	*/

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
#endif

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#if defined(CONFIG_WATCHDOG)
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
#else
/*
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
*/
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWRI | SYPCR_SWP)
#endif

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				11-6
 *-----------------------------------------------------------------------
 * PCMCIA config., multi-function pin tri-state
 */
#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC00 | SIUMCR_FRC)

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control				11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)

/*-----------------------------------------------------------------------
 * RTCSC - Real-Time Clock Status and Control Register		11-27
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)

/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
 *-----------------------------------------------------------------------
 * Reset PLL lock status sticky bit, timer expired status bit and timer
 * interrupt status bit
 *
 */

/*
 * for 48 MHz, we use a 4 MHz clock * 12
 */
#define CONFIG_SYS_PLPRCR							\
		( (12-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_LOLRE )

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
#define SCCR_MASK	SCCR_EBDF11
#define CONFIG_SYS_SCCR	(SCCR_RTDIV   | SCCR_RTSEL    | SCCR_CRQEN    | \
		         SCCR_PRQEN   | SCCR_EBDF00   | \
		         SCCR_COM01   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD001 | \
			 SCCR_DFALCD00)

#ifdef NOT_USED
/*-----------------------------------------------------------------------
 * PCMCIA stuff
 *-----------------------------------------------------------------------
 *
 */
#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )

/*-----------------------------------------------------------------------
 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 *-----------------------------------------------------------------------
 */

#define	CONFIG_IDE_PCCARD	1	/* Use IDE with PC Card	Adapter	*/

#undef	CONFIG_IDE_PCMCIA		/* Direct IDE    not supported	*/
#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/

#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/

#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000

#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR

/* Offset for data I/O			*/
#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)

/* Offset for normal register accesses	*/
#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)

/* Offset for alternate registers	*/
#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100

#endif

/*-----------------------------------------------------------------------
 *
 *-----------------------------------------------------------------------
 *
 */
/*#define	CONFIG_SYS_DER	0x2002000F*/
#define CONFIG_SYS_DER	0

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */

#define FLASH_BASE0_PRELIM	0xFFF00000	/* FLASH bank #0	*/
#define FLASH_BASE1_PRELIM	0x04000000	/* D.O.C Millenium	*/

/* used to re-map FLASH both when starting from SRAM or FLASH:
 * restrict access enough to keep SRAM working (if any)
 * but not too much to meddle with FLASH accesses
 */
#define CONFIG_SYS_PRELIM_OR_AM	0xFFF80000	/* OR addr mask */

/* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 7, EHTR = 1	*/
#define CONFIG_SYS_OR_TIMING_FLASH  (OR_ACS_DIV1 | OR_BI | OR_SCY_7_CLK | OR_EHTR)

#define CONFIG_SYS_OR_TIMING_MSYS   (OR_ACS_DIV1 | OR_BI)

#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V)

#define CONFIG_SYS_OR1_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_MSYS)
#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMB | \
		          BR_PS_8 | BR_V)

/*
 * BR4 and OR4 (SDRAM)
 *
 */
#define SDRAM_BASE4_PRELIM	0x00000000	/* SDRAM bank #0	*/
#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/

/*
 * SDRAM timing:
 */
#define CONFIG_SYS_OR_TIMING_SDRAM	(OR_CSNT_SAM)

#define CONFIG_SYS_OR4_PRELIM	(~(SDRAM_MAX_SIZE-1) | CONFIG_SYS_OR_TIMING_SDRAM )
#define CONFIG_SYS_BR4_PRELIM	((SDRAM_BASE4_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )

/*
 * Memory Periodic Timer Prescaler
 */

/* periodic timer for refresh */
#define CONFIG_SYS_MAMR_PTA	187		/* start with divider for 48 MHz	*/

/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/

/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/

/*
 * MAMR settings for SDRAM
 */

/* 8 column SDRAM */
#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
/* 9 column SDRAM */
#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)

/*
 * JFFS2 partitions
 *
 */
/* No command line, one static partition, whole device */
#undef CONFIG_CMD_MTDPARTS
#define CONFIG_JFFS2_DEV		"nor0"
#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
#define CONFIG_JFFS2_PART_OFFSET	0x00000000

/* mtdparts command line support */
/* Note: fake mtd_id used, no linux mtd map file */
/*
#define CONFIG_CMD_MTDPARTS
#define MTDIDS_DEFAULT		""
#define MTDPARTS_DEFAULT	""
*/

#endif	/* __CONFIG_H */
Commit	Line	Data
682011ff WD	1	/*
	2	* (C) Copyright 2000, 2001
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* Modified by Udi Finkelstein udif@udif.com
	6	* For the RBC823 board.
	7	*
	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26
	27	/*
	28	* board/config.h - configuration options, board specific
	29	*/
	30
	31	#ifndef __CONFIG_H
	32	#define __CONFIG_H
	33
	34	/*
	35	* High Level Configuration Options
	36	* (easy to change)
	37	*/
	38
	39	#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
	40	#define CONFIG_RBC823 1 /* ...on a RBC823 module */
	41
2ae18241	42	#define CONFIG_SYS_TEXT_BASE 0xFFF00000
682011ff WD	43
	44	#if 0
	45	#define DEBUG 1
	46	#define CONFIG_LAST_STAGE_INIT
	47	#endif
	48	#define CONFIG_KEYBOARD 1 /* This board has a custom keybpard */
	49	#define CONFIG_LCD 1 /* use LCD controller ... */
59155f4c	50	#define CONFIG_MPC8XX_LCD
682011ff WD	51	#define CONFIG_HITACHI_SP19X001_Z1A /* The LCD type we use */
	52
	53	#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
	54	#undef CONFIG_8xx_CONS_SMC1
	55	#undef CONFIG_8xx_CONS_NONE
	56	#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
	57	#if 1
	58	#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
	59	#else
	60	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	61	#endif
	62
	63	#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
	64	#define CONFIG_8xx_GCLK_FREQ 48000000L
	65
32bf3d14	66	#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
682011ff WD	67
	68	#undef CONFIG_BOOTARGS
	69	#define CONFIG_BOOTCOMMAND \
53677ef1 WD	70	"bootp; " \
	71	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
	72	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
682011ff WD	73	"bootm"
	74
	75	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	76	#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
682011ff WD	77
	78	#undef CONFIG_WATCHDOG /* watchdog disabled */
	79
	80	#define CONFIG_STATUS_LED 1 /* Status LED enabled */
	81
	82	#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
	83
18225e8d JL	84	/*
	85	* BOOTP options
	86	*/
	87	#define CONFIG_BOOTP_SUBNETMASK
	88	#define CONFIG_BOOTP_GATEWAY
	89	#define CONFIG_BOOTP_HOSTNAME
	90	#define CONFIG_BOOTP_BOOTPATH
	91	#define CONFIG_BOOTP_BOOTFILESIZE
	92
682011ff WD	93
	94	#undef CONFIG_MAC_PARTITION
	95	#define CONFIG_DOS_PARTITION
	96
	97	#undef CONFIG_RTC_MPC8xx /* don't use internal RTC of MPC8xx (no battery) */
	98
	99	#define CONFIG_HARD_I2C
6d0f6bcf JCPV	100	#define CONFIG_SYS_I2C_SPEED 40000
	101	#define CONFIG_SYS_I2C_SLAVE 0xfe
	102	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
	103	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	104	#define CONFIG_SYS_EEPROM_WRITE_BITS 4
	105	#define CONFIG_SYS_EEPROM_WRITE_DELAY_MS 10
682011ff	106
e9a0f8f1 JL	107	/*
	108	* Command line configuration.
	109	*/
4e620410 JCPV	110	#include <config_cmd_default.h>
	111
	112	#define CONFIG_CMD_ASKENV
	113	#define CONFIG_CMD_BEDBUG
	114	#define CONFIG_CMD_BMP
	115	#define CONFIG_CMD_CACHE
	116	#define CONFIG_CMD_CDP
	117	#define CONFIG_CMD_DHCP
	118	#define CONFIG_CMD_DIAG
4e620410 JCPV	119	#define CONFIG_CMD_EEPROM
	120	#define CONFIG_CMD_ELF
	121	#define CONFIG_CMD_FAT
	122	#define CONFIG_CMD_I2C
	123	#define CONFIG_CMD_IMMAP
	124	#define CONFIG_CMD_KGDB
	125	#define CONFIG_CMD_PING
	126	#define CONFIG_CMD_PORTIO
	127	#define CONFIG_CMD_REGINFO
	128	#define CONFIG_CMD_SAVES
	129	#define CONFIG_CMD_SDRAM
	130
e9a0f8f1	131	#undef CONFIG_CMD_SETGETDCR
e9a0f8f1 JL	132	#undef CONFIG_CMD_XIMG
e9a0f8f1 JL	133
682011ff WD	134	/*
	135	* Miscellaneous configurable options
	136	*/
6d0f6bcf JCPV	137	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	138	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
e9a0f8f1	139	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	140	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
682011ff	141	#else
6d0f6bcf	142	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
682011ff	143	#endif
6d0f6bcf JCPV	144	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	145	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	146	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
682011ff	147
6d0f6bcf JCPV	148	#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
6d0f6bcf JCPV	149	#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
682011ff	150
6d0f6bcf	151	#define CONFIG_SYS_LOAD_ADDR 0x0100000 /* default load address */
682011ff	152
6d0f6bcf	153	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
682011ff	154
682011ff WD	155	/*
	156	* Low Level Configuration Settings
	157	* (address mappings, register initial values, etc.)
	158	* You should know what you are doing if you make changes here.
	159	*/
	160	/*-----------------------------------------------------------------------
	161	* Internal Memory Mapped Register
	162	*/
6d0f6bcf	163	#define CONFIG_SYS_IMMR 0xFF000000
682011ff WD	164
	165	/*-----------------------------------------------------------------------
	166	* Definitions for initial stack pointer and data area (in DPRAM)
	167	*/
6d0f6bcf	168	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
553f0982	169	#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
25ddd1fb	170	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	171	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
682011ff WD	172
	173	/*-----------------------------------------------------------------------
	174	* Start addresses for the final memory configuration
	175	* (Set up by the startup code)
6d0f6bcf	176	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
682011ff	177	*/
6d0f6bcf JCPV	178	#define CONFIG_SYS_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	179	#define CONFIG_SYS_FLASH_BASE 0xFFF00000
682011ff	180	#if defined(DEBUG)
6d0f6bcf	181	#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 256 kB for Monitor */
682011ff	182	#else
6d0f6bcf	183	#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 192 kB for Monitor */
682011ff	184	#endif
6d0f6bcf JCPV	185	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
6d0f6bcf JCPV	186	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
682011ff WD	187
	188	/*
	189	* For booting Linux, the board info and command line data
	190	* have to be in the first 8 MB of memory, since this is
	191	* the maximum mapped by the Linux kernel during initialization.
	192	*/
6d0f6bcf	193	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
682011ff WD	194
	195	/*-----------------------------------------------------------------------
	196	* FLASH organization
	197	*/
6d0f6bcf JCPV	198	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
6d0f6bcf JCPV	199	#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
682011ff	200
6d0f6bcf JCPV	201	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	202	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
682011ff	203
5a1aceb0	204	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	205	#define CONFIG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */
0e8d1586 JCPV	206	#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
682011ff WD	207
	208	/*-----------------------------------------------------------------------
	209	* Cache Configuration
	210	*/
6d0f6bcf	211	#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
e9a0f8f1	212	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	213	#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
682011ff WD	214	#endif
	215
	216	/*-----------------------------------------------------------------------
	217	* SYPCR - System Protection Control 11-9
	218	* SYPCR can only be written once after reset!
	219	*-----------------------------------------------------------------------
	220	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
	221	*/
	222	#if defined(CONFIG_WATCHDOG)
6d0f6bcf	223	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
682011ff WD	224	SYPCR_SWE \| SYPCR_SWRI\| SYPCR_SWP)
	225	#else
	226	/*
6d0f6bcf	227	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| SYPCR_SWP)
682011ff	228	*/
6d0f6bcf	229	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWRI \| SYPCR_SWP)
682011ff WD	230	#endif
	231
	232	/*-----------------------------------------------------------------------
	233	* SIUMCR - SIU Module Configuration 11-6
	234	*-----------------------------------------------------------------------
	235	* PCMCIA config., multi-function pin tri-state
	236	*/
6d0f6bcf	237	#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 \| SIUMCR_DBPC00 \| SIUMCR_MLRC00 \| SIUMCR_FRC)
682011ff WD	238
	239	/*-----------------------------------------------------------------------
	240	* TBSCR - Time Base Status and Control 11-26
	241	*-----------------------------------------------------------------------
	242	* Clear Reference Interrupt Status, Timebase freezing enabled
	243	*/
6d0f6bcf	244	#define CONFIG_SYS_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBF)
682011ff WD	245
	246	/*-----------------------------------------------------------------------
	247	* RTCSC - Real-Time Clock Status and Control Register 11-27
	248	*-----------------------------------------------------------------------
	249	*/
6d0f6bcf	250	#define CONFIG_SYS_RTCSC (RTCSC_SEC \| RTCSC_ALR \| RTCSC_RTF\| RTCSC_RTE)
682011ff WD	251
	252	/*-----------------------------------------------------------------------
	253	* PISCR - Periodic Interrupt Status and Control 11-31
	254	*-----------------------------------------------------------------------
	255	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
	256	*/
6d0f6bcf	257	#define CONFIG_SYS_PISCR (PISCR_PS \| PISCR_PITF)
682011ff WD	258
	259	/*-----------------------------------------------------------------------
	260	* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
	261	*-----------------------------------------------------------------------
	262	* Reset PLL lock status sticky bit, timer expired status bit and timer
	263	* interrupt status bit
	264	*
	265	*/
	266
	267	/*
	268	* for 48 MHz, we use a 4 MHz clock * 12
	269	*/
6d0f6bcf	270	#define CONFIG_SYS_PLPRCR \
682011ff WD	271	( (12-1)<<PLPRCR_MF_SHIFT \| PLPRCR_TEXPS \| PLPRCR_LOLRE )
	272
	273	/*-----------------------------------------------------------------------
	274	* SCCR - System Clock and reset Control Register 15-27
	275	*-----------------------------------------------------------------------
	276	* Set clock output, timebase and RTC source and divider,
	277	* power management and some other internal clocks
	278	*/
	279	#define SCCR_MASK SCCR_EBDF11
6d0f6bcf	280	#define CONFIG_SYS_SCCR (SCCR_RTDIV \| SCCR_RTSEL \| SCCR_CRQEN \| \
682011ff WD	281	SCCR_PRQEN \| SCCR_EBDF00 \| \
	282	SCCR_COM01 \| SCCR_DFSYNC00 \| SCCR_DFBRG00 \| \
	283	SCCR_DFNL000 \| SCCR_DFNH000 \| SCCR_DFLCD001 \| \
	284	SCCR_DFALCD00)
	285
	286	#ifdef NOT_USED
	287	/*-----------------------------------------------------------------------
	288	* PCMCIA stuff
	289	*-----------------------------------------------------------------------
	290	*
	291	*/
6d0f6bcf JCPV	292	#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
	293	#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
	294	#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
	295	#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
	296	#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
	297	#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
	298	#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
	299	#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
682011ff WD	300
	301	/*-----------------------------------------------------------------------
	302	* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
	303	*-----------------------------------------------------------------------
	304	*/
	305
	306	#define CONFIG_IDE_PCCARD 1 /* Use IDE with PC Card Adapter */
	307
	308	#undef CONFIG_IDE_PCMCIA /* Direct IDE not supported */
	309	#undef CONFIG_IDE_LED /* LED for ide not supported */
	310	#undef CONFIG_IDE_RESET /* reset for ide not supported */
	311
6d0f6bcf JCPV	312	#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
6d0f6bcf JCPV	313	#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
682011ff	314
6d0f6bcf	315	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
682011ff	316
6d0f6bcf	317	#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
682011ff WD	318
682011ff WD	319	/* Offset for data I/O */
6d0f6bcf	320	#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
682011ff WD	321
682011ff WD	322	/* Offset for normal register accesses */
6d0f6bcf	323	#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
682011ff WD	324
682011ff WD	325	/* Offset for alternate registers */
6d0f6bcf	326	#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
682011ff WD	327
	328	#endif
	329
682011ff WD	330	/*-----------------------------------------------------------------------
	331	*
	332	*-----------------------------------------------------------------------
	333	*
	334	*/
6d0f6bcf JCPV	335	/#define CONFIG_SYS_DER 0x2002000F/
6d0f6bcf JCPV	336	#define CONFIG_SYS_DER 0
682011ff WD	337
	338	/*
	339	* Init Memory Controller:
	340	*
	341	* BR0/1 and OR0/1 (FLASH)
	342	*/
	343
	344	#define FLASH_BASE0_PRELIM 0xFFF00000 /* FLASH bank #0 */
	345	#define FLASH_BASE1_PRELIM 0x04000000 /* D.O.C Millenium */
	346
	347	/* used to re-map FLASH both when starting from SRAM or FLASH:
	348	* restrict access enough to keep SRAM working (if any)
	349	* but not too much to meddle with FLASH accesses
	350	*/
6d0f6bcf	351	#define CONFIG_SYS_PRELIM_OR_AM 0xFFF80000 /* OR addr mask */
682011ff WD	352
682011ff WD	353	/* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 7, EHTR = 1 */
6d0f6bcf	354	#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 \| OR_BI \| OR_SCY_7_CLK \| OR_EHTR)
682011ff	355
6d0f6bcf	356	#define CONFIG_SYS_OR_TIMING_MSYS (OR_ACS_DIV1 \| OR_BI)
682011ff	357
6d0f6bcf JCPV	358	#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \| CONFIG_SYS_OR_TIMING_FLASH)
6d0f6bcf JCPV	359	#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) \| BR_PS_8 \| BR_V)
682011ff	360
6d0f6bcf JCPV	361	#define CONFIG_SYS_OR1_PRELIM (CONFIG_SYS_PRELIM_OR_AM \| CONFIG_SYS_OR_TIMING_MSYS)
6d0f6bcf JCPV	362	#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) \| BR_MS_UPMB \| \
682011ff WD	363	BR_PS_8 \| BR_V)
	364
	365	/*
	366	* BR4 and OR4 (SDRAM)
	367	*
	368	*/
	369	#define SDRAM_BASE4_PRELIM 0x00000000 /* SDRAM bank #0 */
	370	#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
	371
	372	/*
	373	* SDRAM timing:
	374	*/
6d0f6bcf	375	#define CONFIG_SYS_OR_TIMING_SDRAM (OR_CSNT_SAM)
682011ff	376
6d0f6bcf JCPV	377	#define CONFIG_SYS_OR4_PRELIM (~(SDRAM_MAX_SIZE-1) \| CONFIG_SYS_OR_TIMING_SDRAM )
6d0f6bcf JCPV	378	#define CONFIG_SYS_BR4_PRELIM ((SDRAM_BASE4_PRELIM & BR_BA_MSK) \| BR_MS_UPMA \| BR_V )
682011ff WD	379
	380	/*
	381	* Memory Periodic Timer Prescaler
	382	*/
	383
	384	/* periodic timer for refresh */
6d0f6bcf	385	#define CONFIG_SYS_MAMR_PTA 187 /* start with divider for 48 MHz */
682011ff WD	386
682011ff WD	387	/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
6d0f6bcf JCPV	388	#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
6d0f6bcf JCPV	389	#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
682011ff WD	390
682011ff WD	391	/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
6d0f6bcf JCPV	392	#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
6d0f6bcf JCPV	393	#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
682011ff WD	394
	395	/*
	396	* MAMR settings for SDRAM
	397	*/
	398
	399	/* 8 column SDRAM */
6d0f6bcf	400	#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
682011ff WD	401	MAMR_AMA_TYPE_0 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A11 \| \
	402	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
	403	/* 9 column SDRAM */
6d0f6bcf	404	#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
682011ff WD	405	MAMR_AMA_TYPE_1 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A10 \| \
	406	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
	407
700a0c64 WD	408	/*
	409	* JFFS2 partitions
	410	*
	411	*/
	412	/* No command line, one static partition, whole device */
68d7d651	413	#undef CONFIG_CMD_MTDPARTS
700a0c64 WD	414	#define CONFIG_JFFS2_DEV "nor0"
	415	#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
	416	#define CONFIG_JFFS2_PART_OFFSET 0x00000000
	417
	418	/* mtdparts command line support */
	419	/* Note: fake mtd_id used, no linux mtd map file */
	420	/*
68d7d651	421	#define CONFIG_CMD_MTDPARTS
700a0c64 WD	422	#define MTDIDS_DEFAULT ""
	423	#define MTDPARTS_DEFAULT ""
	424	*/
	425
682011ff	426	#endif /* __CONFIG_H */