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5b1d7137 WD |
1 | /* |
2 | * (C) Copyright 2000, 2001, 2002 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * board/config.h - configuration options, board specific | |
26 | */ | |
27 | ||
28 | /* Yoo. Jonghoon, IPone, yooth@ipone.co.kr | |
29 | * U-Boot port on RPXlite board | |
30 | */ | |
31 | ||
32 | #ifndef __CONFIG_H | |
33 | #define __CONFIG_H | |
34 | ||
35 | #define RPXClassic_50MHz | |
36 | ||
37 | /* | |
38 | * High Level Configuration Options | |
39 | * (easy to change) | |
40 | */ | |
41 | ||
42 | #define CONFIG_MPC860 1 | |
43 | #define CONFIG_RPXCLASSIC 1 | |
44 | ||
2ae18241 WD |
45 | #define CONFIG_SYS_TEXT_BASE 0xff000000 |
46 | ||
5b1d7137 WD |
47 | #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
48 | #undef CONFIG_8xx_CONS_SMC2 | |
49 | #undef CONFIG_8xx_CONS_NONE | |
50 | #define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */ | |
51 | ||
5b1d7137 | 52 | /* Define CONFIG_FEC_ENET to use Fast ethernet instead of ethernet on SCC1 */ |
a6c7ad2f | 53 | #define CONFIG_FEC_ENET |
5b1d7137 | 54 | #ifdef CONFIG_FEC_ENET |
6d0f6bcf | 55 | #define CONFIG_SYS_DISCOVER_PHY 1 |
a6c7ad2f | 56 | #define CONFIG_MII 1 |
5b1d7137 | 57 | #endif /* CONFIG_FEC_ENET */ |
d8d21e69 | 58 | #define CONFIG_MISC_INIT_R |
5b1d7137 | 59 | |
a6c7ad2f WD |
60 | /* Video console (graphic: Epson SED13806 on ECCX board, no keyboard */ |
61 | #if 1 | |
62 | #define CONFIG_VIDEO_SED13806 | |
63 | #define CONFIG_NEC_NL6448BC20 | |
64 | #define CONFIG_VIDEO_SED13806_16BPP | |
65 | ||
66 | #define CONFIG_CFB_CONSOLE | |
67 | #define CONFIG_VIDEO_LOGO | |
68 | #define CONFIG_VIDEO_BMP_LOGO | |
69 | #define CONFIG_CONSOLE_EXTRA_INFO | |
70 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
71 | #define CONFIG_VIDEO_SW_CURSOR | |
72 | #endif | |
73 | ||
5b1d7137 WD |
74 | #if 0 |
75 | #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ | |
76 | #else | |
77 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
78 | #endif | |
79 | ||
80 | #define CONFIG_ZERO_BOOTDELAY_CHECK 1 | |
81 | ||
82 | #undef CONFIG_BOOTARGS | |
83 | #define CONFIG_BOOTCOMMAND \ | |
53677ef1 WD |
84 | "tftpboot; " \ |
85 | "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ | |
86 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ | |
5b1d7137 WD |
87 | "bootm" |
88 | ||
89 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 90 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
5b1d7137 WD |
91 | |
92 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
93 | ||
18225e8d JL |
94 | /* |
95 | * BOOTP options | |
96 | */ | |
97 | #define CONFIG_BOOTP_SUBNETMASK | |
98 | #define CONFIG_BOOTP_GATEWAY | |
99 | #define CONFIG_BOOTP_HOSTNAME | |
100 | #define CONFIG_BOOTP_BOOTPATH | |
101 | #define CONFIG_BOOTP_BOOTFILESIZE | |
102 | ||
5b1d7137 WD |
103 | |
104 | #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ | |
105 | ||
106 | ||
e9a0f8f1 JL |
107 | /* |
108 | * Command line configuration. | |
109 | */ | |
110 | #include <config_cmd_default.h> | |
111 | ||
112 | #define CONFIG_CMD_ELF | |
5b1d7137 | 113 | |
5b1d7137 WD |
114 | |
115 | /* | |
116 | * Miscellaneous configurable options | |
117 | */ | |
6d0f6bcf JCPV |
118 | #define CONFIG_SYS_RESET_ADDRESS 0x80000000 |
119 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
120 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
e9a0f8f1 | 121 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 122 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
5b1d7137 | 123 | #else |
6d0f6bcf | 124 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
5b1d7137 | 125 | #endif |
6d0f6bcf JCPV |
126 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
127 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
128 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
5b1d7137 | 129 | |
6d0f6bcf JCPV |
130 | #define CONFIG_SYS_MEMTEST_START 0x0040000 /* memtest works on */ |
131 | #define CONFIG_SYS_MEMTEST_END 0x00C0000 /* 4 ... 12 MB in DRAM */ | |
5b1d7137 | 132 | |
6d0f6bcf | 133 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
5b1d7137 | 134 | |
6d0f6bcf | 135 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
5b1d7137 | 136 | |
5b1d7137 WD |
137 | /* |
138 | * Low Level Configuration Settings | |
139 | * (address mappings, register initial values, etc.) | |
140 | * You should know what you are doing if you make changes here. | |
141 | */ | |
142 | /*----------------------------------------------------------------------- | |
143 | * Internal Memory Mapped Register | |
144 | */ | |
6d0f6bcf | 145 | #define CONFIG_SYS_IMMR 0xFA200000 |
5b1d7137 WD |
146 | |
147 | /*----------------------------------------------------------------------------- | |
148 | * I2C Configuration | |
149 | *----------------------------------------------------------------------------- | |
150 | */ | |
ea818dbb HS |
151 | #define CONFIG_SYS_I2C_SPEED 50000 |
152 | #define CONFIG_SYS_I2C_SLAVE 0x34 | |
5b1d7137 WD |
153 | |
154 | ||
155 | /* enable I2C and select the hardware/software driver */ | |
156 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ | |
ea818dbb HS |
157 | #undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ |
158 | ||
159 | #if defined(CONFIG_SYS_I2C_SOFT) | |
160 | #define CONFIG_SYS_I2C 1 | |
5b1d7137 WD |
161 | /* |
162 | * Software (bit-bang) I2C driver configuration | |
163 | */ | |
164 | #define I2C_PORT 1 /* Port A=0, B=1, C=2, D=3 */ | |
165 | #define I2C_ACTIVE (iop->pdir |= 0x00000010) | |
166 | #define I2C_TRISTATE (iop->pdir &= ~0x00000010) | |
167 | #define I2C_READ ((iop->pdat & 0x00000010) != 0) | |
168 | #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00000010; \ | |
169 | else iop->pdat &= ~0x00000010 | |
170 | #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00000020; \ | |
171 | else iop->pdat &= ~0x00000020 | |
172 | #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ | |
173 | ||
174 | ||
ea818dbb HS |
175 | #define CONFIG_SYS_I2C_SOFT_SPEED 50000 |
176 | #define CONFIG_SYS_I2C_SOFT_SLAVE 0x34 | |
177 | #endif | |
178 | ||
6d0f6bcf JCPV |
179 | # define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM X24C16 */ |
180 | # define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ | |
5b1d7137 | 181 | /* mask of address bits that overflow into the "EEPROM chip address" */ |
6d0f6bcf | 182 | #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 |
5b1d7137 WD |
183 | |
184 | /*----------------------------------------------------------------------- | |
185 | * Definitions for initial stack pointer and data area (in DPRAM) | |
186 | */ | |
6d0f6bcf | 187 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
553f0982 | 188 | #define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */ |
25ddd1fb | 189 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 190 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
5b1d7137 WD |
191 | |
192 | /*----------------------------------------------------------------------- | |
193 | * Start addresses for the final memory configuration | |
194 | * (Set up by the startup code) | |
6d0f6bcf | 195 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
5b1d7137 | 196 | */ |
6d0f6bcf JCPV |
197 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
198 | #define CONFIG_SYS_FLASH_BASE 0xFF000000 | |
5b1d7137 | 199 | |
e9a0f8f1 | 200 | #if defined(DEBUG) || defined (CONFIG_VIDEO_SED13806) || defined(CONFIG_CMD_IDE) |
6d0f6bcf | 201 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
5b1d7137 | 202 | #else |
6d0f6bcf | 203 | #define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ |
5b1d7137 | 204 | #endif |
6d0f6bcf JCPV |
205 | #define CONFIG_SYS_MONITOR_BASE 0xFF000000 |
206 | /*%%% #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE */ | |
207 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
5b1d7137 WD |
208 | |
209 | /* | |
210 | * For booting Linux, the board info and command line data | |
211 | * have to be in the first 8 MB of memory, since this is | |
212 | * the maximum mapped by the Linux kernel during initialization. | |
213 | */ | |
6d0f6bcf | 214 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
5b1d7137 WD |
215 | |
216 | /*----------------------------------------------------------------------- | |
217 | * FLASH organization | |
218 | */ | |
6d0f6bcf JCPV |
219 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
220 | #define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ | |
5b1d7137 | 221 | |
6d0f6bcf JCPV |
222 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
223 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
5b1d7137 WD |
224 | |
225 | #if 0 | |
5a1aceb0 | 226 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
227 | #define CONFIG_ENV_OFFSET 0x20000 /* Offset of Environment Sector */ |
228 | #define CONFIG_ENV_SECT_SIZE 0x8000 | |
229 | #define CONFIG_ENV_SIZE 0x8000 /* Total Size of Environment Sector */ | |
5b1d7137 | 230 | #else |
9314cee6 | 231 | #define CONFIG_ENV_IS_IN_NVRAM 1 |
0e8d1586 JCPV |
232 | #define CONFIG_ENV_ADDR 0xfa000100 |
233 | #define CONFIG_ENV_SIZE 0x1000 | |
5b1d7137 WD |
234 | #endif |
235 | ||
236 | /*----------------------------------------------------------------------- | |
237 | * Cache Configuration | |
238 | */ | |
6d0f6bcf | 239 | #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
e9a0f8f1 | 240 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 241 | #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
5b1d7137 WD |
242 | #endif |
243 | ||
244 | /*----------------------------------------------------------------------- | |
245 | * SYPCR - System Protection Control 11-9 | |
246 | * SYPCR can only be written once after reset! | |
247 | *----------------------------------------------------------------------- | |
248 | * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze | |
249 | */ | |
6d0f6bcf | 250 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
5b1d7137 WD |
251 | SYPCR_SWP) |
252 | ||
253 | /*----------------------------------------------------------------------- | |
254 | * SIUMCR - SIU Module Configuration 11-6 | |
255 | *----------------------------------------------------------------------- | |
256 | * PCMCIA config., multi-function pin tri-state | |
257 | */ | |
6d0f6bcf | 258 | #define CONFIG_SYS_SIUMCR (SIUMCR_MLRC10) |
5b1d7137 WD |
259 | |
260 | /*----------------------------------------------------------------------- | |
261 | * TBSCR - Time Base Status and Control 11-26 | |
262 | *----------------------------------------------------------------------- | |
263 | * Clear Reference Interrupt Status, Timebase freezing enabled | |
264 | */ | |
6d0f6bcf | 265 | #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE) |
5b1d7137 WD |
266 | |
267 | /*----------------------------------------------------------------------- | |
268 | * RTCSC - Real-Time Clock Status and Control Register 11-27 | |
269 | *----------------------------------------------------------------------- | |
270 | */ | |
6d0f6bcf JCPV |
271 | /*%%%#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */ |
272 | #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTE) | |
5b1d7137 WD |
273 | |
274 | /*----------------------------------------------------------------------- | |
275 | * PISCR - Periodic Interrupt Status and Control 11-31 | |
276 | *----------------------------------------------------------------------- | |
277 | * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled | |
278 | */ | |
6d0f6bcf | 279 | #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE) |
5b1d7137 WD |
280 | |
281 | /*----------------------------------------------------------------------- | |
282 | * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 | |
283 | *----------------------------------------------------------------------- | |
284 | * Reset PLL lock status sticky bit, timer expired status bit and timer | |
285 | * interrupt status bit | |
286 | * | |
287 | * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! | |
288 | */ | |
289 | /* up to 50 MHz we use a 1:1 clock */ | |
6d0f6bcf | 290 | #define CONFIG_SYS_PLPRCR ( (4 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS | PLPRCR_SPLSS | PLPRCR_TMIST) |
5b1d7137 WD |
291 | |
292 | /*----------------------------------------------------------------------- | |
293 | * SCCR - System Clock and reset Control Register 15-27 | |
294 | *----------------------------------------------------------------------- | |
295 | * Set clock output, timebase and RTC source and divider, | |
296 | * power management and some other internal clocks | |
297 | */ | |
298 | #define SCCR_MASK SCCR_EBDF00 | |
299 | /* up to 50 MHz we use a 1:1 clock */ | |
6d0f6bcf | 300 | #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_TBS) |
5b1d7137 WD |
301 | |
302 | /*----------------------------------------------------------------------- | |
303 | * PCMCIA stuff | |
304 | *----------------------------------------------------------------------- | |
305 | * | |
306 | */ | |
6d0f6bcf JCPV |
307 | #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) |
308 | #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) | |
309 | #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) | |
310 | #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) | |
311 | #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) | |
312 | #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) | |
313 | #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) | |
314 | #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) | |
5b1d7137 WD |
315 | |
316 | /*----------------------------------------------------------------------- | |
317 | * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) | |
318 | *----------------------------------------------------------------------- | |
319 | */ | |
320 | ||
8d1165e1 | 321 | #define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ |
5b1d7137 WD |
322 | #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ |
323 | ||
324 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ | |
325 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
326 | #undef CONFIG_IDE_RESET /* reset for ide not supported */ | |
327 | ||
6d0f6bcf JCPV |
328 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
329 | #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ | |
5b1d7137 | 330 | |
6d0f6bcf | 331 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
5b1d7137 | 332 | |
6d0f6bcf | 333 | #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR |
5b1d7137 WD |
334 | |
335 | /* Offset for data I/O */ | |
6d0f6bcf | 336 | #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
5b1d7137 WD |
337 | |
338 | /* Offset for normal register accesses */ | |
6d0f6bcf | 339 | #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
5b1d7137 WD |
340 | |
341 | /* Offset for alternate registers */ | |
6d0f6bcf | 342 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 |
5b1d7137 WD |
343 | |
344 | /*----------------------------------------------------------------------- | |
345 | * | |
346 | *----------------------------------------------------------------------- | |
347 | * | |
348 | */ | |
6d0f6bcf JCPV |
349 | /* #define CONFIG_SYS_DER 0x2002000F */ |
350 | #define CONFIG_SYS_DER 0 | |
5b1d7137 WD |
351 | |
352 | /* | |
353 | * Init Memory Controller: | |
354 | * | |
355 | * BR0 and OR0 (FLASH) | |
356 | */ | |
357 | ||
358 | #define FLASH_BASE_PRELIM 0xFE000000 /* FLASH base */ | |
6d0f6bcf | 359 | #define CONFIG_SYS_PRELIM_OR_AM 0xFE000000 /* OR addr mask */ |
5b1d7137 WD |
360 | |
361 | /* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */ | |
6d0f6bcf | 362 | #define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI) |
5b1d7137 | 363 | |
6d0f6bcf JCPV |
364 | #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
365 | #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V) | |
5b1d7137 WD |
366 | |
367 | /* | |
368 | * BR1 and OR1 (SDRAM) | |
369 | * | |
370 | */ | |
371 | #define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */ | |
372 | #define SDRAM_MAX_SIZE 0x01000000 /* max 16 MB */ | |
373 | ||
374 | /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ | |
6d0f6bcf | 375 | #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000E00 |
5b1d7137 | 376 | |
6d0f6bcf JCPV |
377 | #define CONFIG_SYS_OR1_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) |
378 | #define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) | |
5b1d7137 WD |
379 | |
380 | /* RPXLITE mem setting */ | |
6d0f6bcf JCPV |
381 | #define CONFIG_SYS_BR3_PRELIM 0xFA400001 /* BCSR */ |
382 | #define CONFIG_SYS_OR3_PRELIM 0xff7f8970 | |
383 | #define CONFIG_SYS_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */ | |
384 | #define CONFIG_SYS_OR4_PRELIM 0xFFF80970 | |
5b1d7137 | 385 | |
a6c7ad2f WD |
386 | /* ECCX CS settings */ |
387 | #define SED13806_OR 0xFFC00108 /* - 4 Mo | |
8bde7f77 WD |
388 | - Burst inhibit |
389 | - external TA */ | |
a6c7ad2f WD |
390 | #define SED13806_REG_ADDR 0xa0000000 |
391 | #define SED13806_ACCES 0x801 /* 16 bit access */ | |
392 | ||
393 | ||
394 | /* Global definitions for the ECCX board */ | |
395 | #define ECCX_CSR_ADDR (0xfac00000) | |
396 | #define ECCX_CSR8_OFFSET (0x8) | |
397 | #define ECCX_CSR11_OFFSET (0xB) | |
398 | #define ECCX_CSR12_OFFSET (0xC) | |
399 | ||
400 | #define ECCX_CSR8 (volatile unsigned char *)(ECCX_CSR_ADDR + ECCX_CSR8_OFFSET) | |
401 | #define ECCX_CSR11 (volatile unsigned char *)(ECCX_CSR_ADDR + ECCX_CSR11_OFFSET) | |
402 | #define ECCX_CSR12 (volatile unsigned char *)(ECCX_CSR_ADDR + ECCX_CSR12_OFFSET) | |
403 | ||
404 | ||
405 | #define REG_GPIO_CTRL 0x008 | |
406 | ||
407 | /* Definitions for CSR8 */ | |
408 | #define ECCX_ENEPSON 0x80 /* Bit 0: | |
8bde7f77 WD |
409 | 0= disable and reset SED1386 |
410 | 1= enable SED1386 */ | |
a6c7ad2f WD |
411 | /* Bit 1: 0= SED1386 in Big Endian mode */ |
412 | /* 1= SED1386 in little endian mode */ | |
413 | #define ECCX_LE 0x40 | |
414 | #define ECCX_BE 0x00 | |
415 | ||
416 | /* Bit 2,3: Selection */ | |
417 | /* 00 = Disabled */ | |
418 | /* 01 = CS2 is used for the SED1386 */ | |
419 | /* 10 = CS5 is used for the SED1386 */ | |
420 | /* 11 = reserved */ | |
421 | #define ECCX_CS2 0x10 | |
422 | #define ECCX_CS5 0x20 | |
423 | ||
424 | /* Definitions for CSR12 */ | |
425 | #define ECCX_ID 0x02 | |
426 | #define ECCX_860 0x01 | |
427 | ||
5b1d7137 WD |
428 | /* |
429 | * Memory Periodic Timer Prescaler | |
430 | */ | |
431 | ||
432 | /* periodic timer for refresh */ | |
6d0f6bcf | 433 | #define CONFIG_SYS_MAMR_PTA 58 |
5b1d7137 WD |
434 | |
435 | /* | |
436 | * Refresh clock Prescalar | |
437 | */ | |
6d0f6bcf | 438 | #define CONFIG_SYS_MPTPR MPTPR_PTP_DIV8 |
5b1d7137 WD |
439 | |
440 | /* | |
441 | * MAMR settings for SDRAM | |
442 | */ | |
443 | ||
444 | /* 10 column SDRAM */ | |
6d0f6bcf | 445 | #define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
5b1d7137 WD |
446 | MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A12 | \ |
447 | MAMR_GPL_A4DIS | MAMR_RLFA_4X | MAMR_WLFA_3X | MAMR_TLFA_16X) | |
448 | ||
5b1d7137 WD |
449 | /*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */ |
450 | /* Configuration variable added by yooth. */ | |
451 | /*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */ | |
452 | ||
453 | /* | |
454 | * BCSRx | |
455 | * | |
456 | * Board Status and Control Registers | |
457 | * | |
458 | */ | |
459 | ||
460 | #define BCSR0 0xFA400000 | |
461 | #define BCSR1 0xFA400001 | |
462 | #define BCSR2 0xFA400002 | |
463 | #define BCSR3 0xFA400003 | |
464 | ||
465 | #define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */ | |
53677ef1 | 466 | #define BCSR0_ENNVRAM 0x02 /* CS4# Control */ |
5b1d7137 WD |
467 | #define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */ |
468 | #define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */ | |
469 | #define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */ | |
470 | #define BCSR0_COLTEST 0x20 | |
471 | #define BCSR0_ETHLPBK 0x40 | |
472 | #define BCSR0_ETHEN 0x80 | |
473 | ||
474 | #define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */ | |
475 | #define BCSR1_PCVCTL6 0x02 | |
476 | #define BCSR1_PCVCTL5 0x04 | |
477 | #define BCSR1_PCVCTL4 0x08 | |
478 | #define BCSR1_IPB5SEL 0x10 | |
479 | ||
480 | #define BCSR2_MIIRST 0x80 | |
481 | #define BCSR2_MIIPWRDWN 0x40 | |
482 | #define BCSR2_MIICTL 0x08 | |
483 | ||
484 | #define BCSR3_BWRTC 0x01 /* Real Time Clock Battery */ | |
485 | #define BCSR3_BWNVR 0x02 /* NVRAM Battery */ | |
486 | #define BCSR3_RDY_BSY 0x04 /* Flash Operation */ | |
487 | #define BCSR3_RPXL 0x08 /* Reserved (reads back '1') */ | |
488 | #define BCSR3_D27 0x10 /* Dip Switch settings */ | |
489 | #define BCSR3_D26 0x20 | |
490 | #define BCSR3_D25 0x40 | |
491 | #define BCSR3_D24 0x80 | |
492 | ||
493 | ||
494 | /* | |
495 | * Environment setting | |
496 | */ | |
497 | ||
498 | /* #define CONFIG_ETHADDR 00:10:EC:00:2C:A2 */ | |
499 | /* #define CONFIG_IPADDR 10.10.106.1 */ | |
500 | /* #define CONFIG_SERVERIP 10.10.104.11 */ | |
501 | ||
502 | #endif /* __CONFIG_H */ |