]>
Commit | Line | Data |
---|---|---|
e63c8ee3 WD |
1 | /* |
2 | * (C) Copyright 2004 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn | |
5 | * | |
6 | * See file CREDITS for list of people who contributed to this | |
7 | * project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | */ | |
24 | ||
25 | /* | |
26 | * board/config.h - configuration options, board specific | |
27 | */ | |
28 | ||
29 | /* Yoo. Jonghoon, IPone, yooth@ipone.co.kr | |
30 | * U-BOOT port on RPXlite board | |
31 | */ | |
32 | ||
33 | /* | |
34 | * Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn | |
35 | * U-BOOT port on RPXlite DW version board--RPXlite_DW | |
36 | * June 8 ,2004 | |
37 | */ | |
38 | ||
39 | #ifndef __CONFIG_H | |
40 | #define __CONFIG_H | |
41 | ||
42 | /* | |
43 | * High Level Configuration Options | |
44 | * (easy to change) | |
45 | */ | |
46 | ||
47 | /* #define DEBUG 1 */ | |
09e4b0c5 | 48 | /* #define DEPLOYMENT 1 */ |
e63c8ee3 WD |
49 | |
50 | #undef CONFIG_MPC860 | |
51 | #define CONFIG_MPC823 1 /* This is a MPC823e CPU. */ | |
52 | #define CONFIG_RPXLITE 1 /* RPXlite DW version board */ | |
53 | ||
2ae18241 WD |
54 | #define CONFIG_SYS_TEXT_BASE 0xff000000 |
55 | ||
e63c8ee3 | 56 | #ifdef CONFIG_LCD /* with LCD controller ? */ |
59155f4c | 57 | #define CONFIG_MPC8XX_LCD |
e63c8ee3 WD |
58 | #define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/ |
59 | #endif | |
60 | ||
61 | #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ | |
62 | #undef CONFIG_8xx_CONS_SMC2 | |
63 | #undef CONFIG_8xx_CONS_NONE | |
64 | #define CONFIG_BAUDRATE 9600 /* console default baudrate = 9600bps */ | |
65 | ||
6225c5db | 66 | #ifdef DEBUG |
09e4b0c5 | 67 | #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ |
e63c8ee3 | 68 | #else |
09e4b0c5 | 69 | #define CONFIG_BOOTDELAY 6 /* autoboot after 6 seconds */ |
6225c5db WD |
70 | |
71 | #ifdef DEPLOYMENT | |
09e4b0c5 | 72 | #define CONFIG_BOOT_RETRY_TIME -1 |
6225c5db | 73 | #define CONFIG_AUTOBOOT_KEYED |
f2302d44 SR |
74 | #define CONFIG_AUTOBOOT_PROMPT \ |
75 | "autoboot in %d seconds (stop with 'st')...\n", bootdelay | |
09e4b0c5 | 76 | #define CONFIG_AUTOBOOT_STOP_STR "st" |
6225c5db | 77 | #define CONFIG_ZERO_BOOTDELAY_CHECK |
09e4b0c5 WD |
78 | #define CONFIG_RESET_TO_RETRY 1 |
79 | #define CONFIG_BOOT_RETRY_MIN 1 | |
c3d2b4b4 WD |
80 | #endif /* DEPLOYMENT */ |
81 | #endif /* DEBUG */ | |
6225c5db WD |
82 | |
83 | /* pre-boot commands */ | |
09e4b0c5 | 84 | #define CONFIG_PREBOOT "setenv stdout serial;setenv stdin serial" |
e63c8ee3 WD |
85 | |
86 | #undef CONFIG_BOOTARGS | |
87 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
88 | "netdev=eth0\0" \ | |
6225c5db | 89 | "nfsargs=setenv bootargs console=tty0 console=ttyS0,9600 " \ |
fe126d8b | 90 | "root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \ |
6225c5db | 91 | "ramargs=setenv bootargs console=tty0 root=/dev/ram rw\0" \ |
fe126d8b WD |
92 | "addip=setenv bootargs ${bootargs} " \ |
93 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
94 | ":${hostname}:${netdev}:off panic=1\0" \ | |
e63c8ee3 | 95 | "flash_nfs=run nfsargs addip;" \ |
fe126d8b | 96 | "bootm ${kernel_addr}\0" \ |
e63c8ee3 | 97 | "flash_self=run ramargs addip;" \ |
fe126d8b WD |
98 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
99 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ | |
e63c8ee3 WD |
100 | "gatewayip=172.16.115.254\0" \ |
101 | "netmask=255.255.255.0\0" \ | |
6225c5db WD |
102 | "kernel_addr=ff040000\0" \ |
103 | "ramdisk_addr=ff200000\0" \ | |
fe126d8b WD |
104 | "ku=era ${kernel_addr} ff1fffff;cp.b 100000 ${kernel_addr} " \ |
105 | "${filesize};md ${kernel_addr};" \ | |
6225c5db WD |
106 | "echo kernel updating finished\0" \ |
107 | "uu=protect off 1:0-4;era 1:0-4;cp.b 100000 ff000000 " \ | |
fe126d8b | 108 | "${filesize};md ff000000;" \ |
6225c5db WD |
109 | "echo u-boot updating finished\0" \ |
110 | "eu=protect off 1:6;era 1:6;reset\0" \ | |
111 | "lcd=setenv stdout lcd;setenv stdin lcd\0" \ | |
112 | "ser=setenv stdout serial;setenv stdin serial\0" \ | |
113 | "verify=no" | |
082acfd4 | 114 | |
e63c8ee3 WD |
115 | #define CONFIG_BOOTCOMMAND "run flash_self" |
116 | ||
117 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 118 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
e63c8ee3 WD |
119 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
120 | #undef CONFIG_STATUS_LED /* disturbs display. Status LED disabled. */ | |
121 | ||
18225e8d JL |
122 | /* |
123 | * BOOTP options | |
124 | */ | |
125 | #define CONFIG_BOOTP_SUBNETMASK | |
126 | #define CONFIG_BOOTP_GATEWAY | |
127 | #define CONFIG_BOOTP_HOSTNAME | |
128 | #define CONFIG_BOOTP_BOOTPATH | |
129 | #define CONFIG_BOOTP_BOOTFILESIZE | |
130 | ||
e63c8ee3 | 131 | |
09e4b0c5 WD |
132 | #if 1 /* Enable this stuff could make image enlarge about 25KB. Mask it if you |
133 | don't want the advanced function */ | |
0a3471fc | 134 | |
e9a0f8f1 JL |
135 | |
136 | /* | |
137 | * Command line configuration. | |
138 | */ | |
139 | #include <config_cmd_default.h> | |
140 | ||
141 | #define CONFIG_CMD_ASKENV | |
142 | #define CONFIG_CMD_JFFS2 | |
143 | #define CONFIG_CMD_PING | |
144 | #define CONFIG_CMD_ELF | |
145 | #define CONFIG_CMD_REGINFO | |
146 | #define CONFIG_CMD_DHCP | |
147 | ||
09e4b0c5 | 148 | #ifdef CONFIG_SPLASH_SCREEN |
e9a0f8f1 JL |
149 | #define CONFIG_CMD_BMP |
150 | #endif | |
151 | ||
0a3471fc WD |
152 | |
153 | /* test-only */ | |
6d0f6bcf JCPV |
154 | #define CONFIG_SYS_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ |
155 | #define CONFIG_SYS_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */ | |
0a3471fc WD |
156 | |
157 | #define CONFIG_NETCONSOLE | |
158 | ||
09e4b0c5 | 159 | #endif /* 1 */ |
0a3471fc | 160 | |
e63c8ee3 WD |
161 | /* |
162 | * Miscellaneous configurable options | |
163 | */ | |
6d0f6bcf JCPV |
164 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
165 | #define CONFIG_SYS_PROMPT "u-boot>" /* Monitor Command Prompt */ | |
e63c8ee3 | 166 | |
e9a0f8f1 | 167 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 168 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
e63c8ee3 | 169 | #else |
6d0f6bcf | 170 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
e63c8ee3 | 171 | #endif |
c3d2b4b4 | 172 | |
6d0f6bcf JCPV |
173 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
174 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
175 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
e63c8ee3 | 176 | |
6d0f6bcf JCPV |
177 | #define CONFIG_SYS_MEMTEST_START 0x0040000 /* memtest works on */ |
178 | #define CONFIG_SYS_MEMTEST_END 0x00C0000 /* 4 ... 12 MB in DRAM */ | |
179 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ | |
e63c8ee3 | 180 | |
6d0f6bcf | 181 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
e63c8ee3 WD |
182 | |
183 | /* | |
184 | * Low Level Configuration Settings | |
185 | * (address mappings, register initial values, etc.) | |
186 | * You should know what you are doing if you make changes here. | |
187 | */ | |
188 | /*----------------------------------------------------------------------- | |
189 | * Internal Memory Mapped Register | |
190 | */ | |
6d0f6bcf | 191 | #define CONFIG_SYS_IMMR 0xFA200000 |
e63c8ee3 WD |
192 | |
193 | /*----------------------------------------------------------------------- | |
194 | * Definitions for initial stack pointer and data area (in DPRAM) | |
195 | */ | |
6d0f6bcf | 196 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
553f0982 | 197 | #define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ |
25ddd1fb | 198 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 199 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
e63c8ee3 WD |
200 | |
201 | /*----------------------------------------------------------------------- | |
202 | * Start addresses for the final memory configuration | |
203 | * (Set up by the startup code) | |
6d0f6bcf | 204 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
e63c8ee3 | 205 | */ |
6d0f6bcf JCPV |
206 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
207 | #define CONFIG_SYS_FLASH_BASE 0xFF000000 | |
e63c8ee3 | 208 | |
e9a0f8f1 | 209 | #if defined(DEBUG) || defined(CONFIG_CMD_IDE) |
6d0f6bcf | 210 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
e63c8ee3 | 211 | #else |
6d0f6bcf | 212 | #define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ |
e63c8ee3 | 213 | #endif |
c3d2b4b4 | 214 | |
6d0f6bcf JCPV |
215 | #define CONFIG_SYS_MONITOR_BASE 0xFF000000 |
216 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
e63c8ee3 WD |
217 | |
218 | /* | |
219 | * For booting Linux, the board info and command line data | |
220 | * have to be in the first 8 MB of memory, since this is | |
221 | * the maximum mapped by the Linux kernel during initialization. | |
222 | */ | |
6d0f6bcf | 223 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
e63c8ee3 WD |
224 | |
225 | /*----------------------------------------------------------------------- | |
226 | * FLASH organization | |
227 | */ | |
6d0f6bcf JCPV |
228 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
229 | #define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ | |
230 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ | |
231 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
e63c8ee3 | 232 | |
9314cee6 | 233 | #ifdef CONFIG_ENV_IS_IN_NVRAM |
0e8d1586 JCPV |
234 | #define CONFIG_ENV_ADDR 0xFA000100 |
235 | #define CONFIG_ENV_SIZE 0x1000 | |
e63c8ee3 | 236 | #else |
5a1aceb0 | 237 | #define CONFIG_ENV_IS_IN_FLASH |
0e8d1586 JCPV |
238 | #define CONFIG_ENV_OFFSET 0x30000 /* Offset of Environment Sector */ |
239 | #define CONFIG_ENV_SIZE 0x8000 /* Total Size of Environment Sector */ | |
9314cee6 | 240 | #endif /* CONFIG_ENV_IS_IN_NVRAM */ |
082acfd4 | 241 | |
6d0f6bcf | 242 | #define CONFIG_SYS_RESET_ADDRESS ((ulong)((((immap_t *)CONFIG_SYS_IMMR)->im_clkrst.res))) |
30d56fae | 243 | |
e63c8ee3 WD |
244 | /*----------------------------------------------------------------------- |
245 | * Cache Configuration | |
246 | */ | |
6d0f6bcf | 247 | #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
e9a0f8f1 | 248 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 249 | #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
e63c8ee3 WD |
250 | #endif |
251 | ||
252 | /*----------------------------------------------------------------------- | |
253 | * SYPCR - System Protection Control 32-bit 12-35 | |
254 | * SYPCR can only be written once after reset! | |
255 | *----------------------------------------------------------------------- | |
256 | * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze | |
257 | */ | |
258 | #if defined(CONFIG_WATCHDOG) | |
6d0f6bcf | 259 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
e63c8ee3 WD |
260 | SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
261 | #else | |
6d0f6bcf | 262 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
e63c8ee3 WD |
263 | #endif /* We can get SYPCR: 0xFFFF0689. */ |
264 | ||
265 | /*----------------------------------------------------------------------- | |
266 | * SIUMCR - SIU Module Configuration 32-bit 12-30 | |
267 | *----------------------------------------------------------------------- | |
268 | * PCMCIA config., multi-function pin tri-state | |
269 | */ | |
6d0f6bcf | 270 | #define CONFIG_SYS_SIUMCR (SIUMCR_MLRC10) /* SIUMCR:0x00000800 */ |
e63c8ee3 WD |
271 | |
272 | /*--------------------------------------------------------------------- | |
273 | * TBSCR - Time Base Status and Control 16-bit 12-16 | |
274 | *--------------------------------------------------------------------- | |
275 | * Clear Reference Interrupt Status, Timebase freezing enabled | |
276 | */ | |
6d0f6bcf | 277 | #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE) |
e63c8ee3 WD |
278 | /* TBSCR: 0x00C3 [SAM] */ |
279 | ||
280 | /*----------------------------------------------------------------------- | |
281 | * RTCSC - Real-Time Clock Status and Control Register 16-bit 12-18 | |
282 | *----------------------------------------------------------------------- | |
283 | * [RTC enabled but not stopped on FRZ] | |
284 | */ | |
6d0f6bcf | 285 | #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTE) /* RTCSC:0x00C1 */ |
e63c8ee3 WD |
286 | |
287 | /*----------------------------------------------------------------------- | |
288 | * PISCR - Periodic Interrupt Status and Control 16-bit 12-23 | |
289 | *----------------------------------------------------------------------- | |
290 | * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled | |
291 | * [Periodic timer enabled,Periodic timer interrupt disable. ] | |
292 | */ | |
6d0f6bcf | 293 | #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE) /* PISCR:0x0083 */ |
e63c8ee3 WD |
294 | |
295 | /*----------------------------------------------------------------------- | |
296 | * PLPRCR - PLL, Low-Power, and Reset Control Register 32-bit 5-7 | |
297 | *----------------------------------------------------------------------- | |
298 | * Reset PLL lock status sticky bit, timer expired status bit and timer | |
299 | * interrupt status bit | |
300 | */ | |
301 | /* up to 64 MHz we use a 1:2 clock */ | |
302 | #if defined(RPXlite_64MHz) | |
6d0f6bcf | 303 | #define CONFIG_SYS_PLPRCR ( (7 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS ) /*PLPRCR: 0x00700000. */ |
e63c8ee3 | 304 | #else |
6d0f6bcf | 305 | #define CONFIG_SYS_PLPRCR ( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS ) |
e63c8ee3 WD |
306 | #endif |
307 | ||
308 | /*----------------------------------------------------------------------- | |
309 | * SCCR - System Clock and reset Control Register 5-3 | |
310 | *----------------------------------------------------------------------- | |
311 | * Set clock output, timebase and RTC source and divider, | |
312 | * power management and some other internal clocks | |
313 | */ | |
314 | #define SCCR_MASK SCCR_EBDF00 | |
30d56fae WD |
315 | /* Up to 48MHz system clock, we use 1:1 SYSTEM/BUS ratio */ |
316 | #if defined(RPXlite_64MHz) | |
6d0f6bcf | 317 | #define CONFIG_SYS_SCCR ( SCCR_TBS | SCCR_EBDF01 ) /* %%%SCCR:0x02020000 */ |
6225c5db | 318 | #else |
6d0f6bcf | 319 | #define CONFIG_SYS_SCCR ( SCCR_TBS | SCCR_EBDF00 ) /* %%%SCCR:0x02000000 */ |
6225c5db | 320 | #endif |
e63c8ee3 WD |
321 | |
322 | /*----------------------------------------------------------------------- | |
323 | * PCMCIA stuff | |
324 | *----------------------------------------------------------------------- | |
325 | */ | |
6d0f6bcf JCPV |
326 | #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) |
327 | #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) | |
328 | #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) | |
329 | #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) | |
330 | #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) | |
331 | #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) | |
332 | #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) | |
333 | #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) | |
e63c8ee3 WD |
334 | |
335 | /*----------------------------------------------------------------------- | |
336 | * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) | |
337 | *----------------------------------------------------------------------- | |
338 | */ | |
8d1165e1 | 339 | #define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ |
e63c8ee3 WD |
340 | #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ |
341 | ||
342 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ | |
343 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
344 | #undef CONFIG_IDE_RESET /* reset for ide not supported */ | |
345 | ||
6d0f6bcf JCPV |
346 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
347 | #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ | |
e63c8ee3 | 348 | |
6d0f6bcf JCPV |
349 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
350 | #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR | |
e63c8ee3 WD |
351 | |
352 | /* Offset for data I/O */ | |
6d0f6bcf | 353 | #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
e63c8ee3 WD |
354 | |
355 | /* Offset for normal register accesses */ | |
6d0f6bcf | 356 | #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
e63c8ee3 WD |
357 | |
358 | /* Offset for alternate registers */ | |
6d0f6bcf | 359 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 |
e63c8ee3 | 360 | |
6d0f6bcf | 361 | #define CONFIG_SYS_DER 0 |
e63c8ee3 WD |
362 | |
363 | /* | |
364 | * Init Memory Controller: | |
365 | * | |
366 | * BR0 and OR0 (FLASH) | |
367 | */ | |
368 | #define FLASH_BASE_PRELIM 0xFC000000 /* FLASH base */ | |
6d0f6bcf | 369 | #define CONFIG_SYS_PRELIM_OR_AM 0xFC000000 /* OR addr mask */ |
e63c8ee3 WD |
370 | |
371 | /* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 8, ETHR = 0, BIH = 1 */ | |
6d0f6bcf JCPV |
372 | #define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_8_CLK | OR_BI) |
373 | #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) | |
374 | #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V) | |
e63c8ee3 WD |
375 | |
376 | /* | |
377 | * BR1 and OR1 (SDRAM) | |
378 | * | |
379 | */ | |
380 | #define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */ | |
381 | #define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB in system */ | |
382 | ||
383 | /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ | |
6d0f6bcf JCPV |
384 | #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000E00 |
385 | #define CONFIG_SYS_OR_AM_SDRAM (-(SDRAM_MAX_SIZE & OR_AM_MSK)) | |
386 | #define CONFIG_SYS_OR1_PRELIM ( CONFIG_SYS_OR_AM_SDRAM | CONFIG_SYS_OR_TIMING_SDRAM ) | |
387 | #define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) | |
e63c8ee3 WD |
388 | |
389 | /* RPXlite mem setting */ | |
6d0f6bcf JCPV |
390 | #define CONFIG_SYS_BR3_PRELIM 0xFA400001 /* BCSR */ |
391 | #define CONFIG_SYS_OR3_PRELIM 0xFF7F8900 | |
392 | #define CONFIG_SYS_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */ | |
393 | #define CONFIG_SYS_OR4_PRELIM 0xFFFE0040 | |
e63c8ee3 WD |
394 | |
395 | /* | |
396 | * Memory Periodic Timer Prescaler | |
397 | */ | |
398 | /* periodic timer for refresh */ | |
399 | #if defined(RPXlite_64MHz) | |
6d0f6bcf | 400 | #define CONFIG_SYS_MAMR_PTA 32 |
e63c8ee3 | 401 | #else |
6d0f6bcf | 402 | #define CONFIG_SYS_MAMR_PTA 20 |
e63c8ee3 WD |
403 | #endif |
404 | ||
405 | /* | |
406 | * Refresh clock Prescalar | |
407 | */ | |
6d0f6bcf | 408 | #define CONFIG_SYS_MPTPR MPTPR_PTP_DIV2 |
e63c8ee3 WD |
409 | |
410 | /* | |
411 | * MAMR settings for SDRAM | |
412 | */ | |
413 | ||
414 | /* 9 column SDRAM */ | |
6d0f6bcf | 415 | #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
e63c8ee3 | 416 | MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10) |
6d0f6bcf | 417 | /* CONFIG_SYS_MAMR_9COL:0x20904000 @ 64MHz */ |
e63c8ee3 | 418 | |
e63c8ee3 WD |
419 | /*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */ |
420 | /* Configuration variable added by yooth. */ | |
421 | /*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */ | |
422 | /* | |
423 | * BCSRx | |
424 | * | |
425 | * Board Status and Control Registers | |
426 | * | |
427 | */ | |
428 | #define BCSR0 0xFA400000 | |
429 | #define BCSR1 0xFA400001 | |
430 | #define BCSR2 0xFA400002 | |
431 | #define BCSR3 0xFA400003 | |
432 | ||
433 | #define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */ | |
434 | #define BCSR0_ENNVRAM 0x02 /* CS4# Control */ | |
435 | #define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */ | |
436 | #define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */ | |
437 | #define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */ | |
438 | #define BCSR0_COLTEST 0x20 | |
439 | #define BCSR0_ETHLPBK 0x40 | |
440 | #define BCSR0_ETHEN 0x80 | |
441 | ||
442 | #define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */ | |
443 | #define BCSR1_PCVCTL6 0x02 | |
444 | #define BCSR1_PCVCTL5 0x04 | |
445 | #define BCSR1_PCVCTL4 0x08 | |
446 | #define BCSR1_IPB5SEL 0x10 | |
447 | ||
448 | #define BCSR1_SMC1CTS 0x40 /* Added by SAM. */ | |
449 | #define BCSR1_SMC1TRS 0x80 /* Added by SAM. */ | |
450 | ||
451 | #define BCSR2_ENRTCIRQ 0x01 /* Added by SAM. */ | |
452 | #define BCSR2_ENBRG1 0x04 /* Added by SAM. */ | |
453 | ||
454 | #define BCSR2_ENPA5HDR 0x08 /* USB Control */ | |
455 | #define BCSR2_ENUSBCLK 0x10 | |
456 | #define BCSR2_USBPWREN 0x20 | |
457 | #define BCSR2_USBSPD 0x40 | |
458 | #define BCSR2_USBSUSP 0x80 | |
459 | ||
460 | #define BCSR3_BWKAPWR 0x01 /* Changed by SAM. Backup battery situation */ | |
461 | #define BCSR3_IRQRTC 0x02 /* Changed by SAM. NVRAM Battery */ | |
462 | #define BCSR3_RDY_BSY 0x04 /* Changed by SAM. Flash Operation */ | |
463 | #define BCSR3_MPLX_LIN 0x08 /* Changed by SAM. Linear or Multiplexed address Mode */ | |
464 | ||
465 | #define BCSR3_D27 0x10 /* Dip Switch settings */ | |
466 | #define BCSR3_D26 0x20 | |
467 | #define BCSR3_D25 0x40 | |
468 | #define BCSR3_D24 0x80 | |
469 | ||
470 | /* | |
471 | * Environment setting | |
472 | */ | |
473 | #define CONFIG_ETHADDR 00:10:EC:00:37:5B | |
474 | #define CONFIG_IPADDR 172.16.115.7 | |
475 | #define CONFIG_SERVERIP 172.16.115.6 | |
8b3637c6 | 476 | #define CONFIG_ROOTPATH "/workspace/myfilesystem/target/" |
b3f44c21 | 477 | #define CONFIG_BOOTFILE "uImage.rpxusb" |
0a3471fc | 478 | #define CONFIG_HOSTNAME LITE_H1_DW |
e63c8ee3 WD |
479 | |
480 | #endif /* __CONFIG_H */ |