[people/ms/u-boot.git] / include / configs / RPXsuper.h

#ifndef __CONFIG_H
#define __CONFIG_H

#define	CONFIG_SYS_TEXT_BASE	0x80F00000

/*****************************************************************************
 *
 * These settings must match the way _your_ board is set up
 *
 *****************************************************************************/
/* for the AY-Revision which does not use the HRCW */
#define CONFIG_SYS_DEFAULT_IMMR	0x00010000

/* What is the oscillator's (UX2) frequency in Hz? */
#define CONFIG_8260_CLKIN  (66 * 1000 * 1000)

/* How is switch S2 set? We really only want the MODCK[1-3] bits, so
 * only the 3 least significant bits are important.
*/
#define CONFIG_SYS_SBC_S2  0x04

/* What should MODCK_H be? It is dependent on the oscillator
 * frequency, MODCK[1-3], and desired CPM and core frequencies.
 * Some example values (all frequencies are in MHz):
 *
 * MODCK_H   MODCK[1-3]  Osc    CPM    Core
 * 0x2       0x2         33     133    133
 * 0x2       0x4         33     133    200
 * 0x5       0x5         66     133    133
 * 0x5       0x7         66     133    200
 */
#define CONFIG_SYS_SBC_MODCK_H 0x06

#define CONFIG_SYS_SBC_BOOT_LOW 1	/* only for HRCW */
#undef CONFIG_SYS_SBC_BOOT_LOW

/* What should the base address of the main FLASH be and how big is
 * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE.
 * The main FLASH is whichever is connected to *CS0. U-Boot expects
 * this to be the SIMM.
 */
#define CONFIG_SYS_FLASH0_BASE 0x80000000
#define CONFIG_SYS_FLASH0_SIZE 16

/* What should the base address of the secondary FLASH be and how big
 * is it (in Mbytes)? The secondary FLASH is whichever is connected
 * to *CS6. U-Boot expects this to be the on board FLASH. If you don't
 * want it enabled, don't define these constants.
 */
#define CONFIG_SYS_FLASH1_BASE 0
#define CONFIG_SYS_FLASH1_SIZE 0
#undef CONFIG_SYS_FLASH1_BASE
#undef CONFIG_SYS_FLASH1_SIZE

/* What should be the base address of SDRAM DIMM and how big is
 * it (in Mbytes)?
*/
#define CONFIG_SYS_SDRAM0_BASE 0x00000000
#define CONFIG_SYS_SDRAM0_SIZE 64

/* What should be the base address of SDRAM DIMM and how big is
 * it (in Mbytes)?
*/
#define CONFIG_SYS_SDRAM1_BASE 0x04000000
#define CONFIG_SYS_SDRAM1_SIZE 32

/* What should be the base address of the LEDs and switch S0?
 * If you don't want them enabled, don't define this.
 */
#define CONFIG_SYS_LED_BASE 0x00000000

/*
 * select serial console configuration
 *
 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
 * for SCC).
 *
 * if CONFIG_CONS_NONE is defined, then the serial console routines must
 * defined elsewhere.
 */
#define CONFIG_CONS_ON_SMC          /* define if console on SMC */
#undef  CONFIG_CONS_ON_SCC          /* define if console on SCC */
#undef  CONFIG_CONS_NONE            /* define if console on neither */
#define CONFIG_CONS_INDEX    1      /* which SMC/SCC channel for console */

/*
 * select ethernet configuration
 *
 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
 * for FCC)
 *
 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
 */
#undef  CONFIG_ETHER_ON_SCC           /* define if ethernet on SCC    */
#define CONFIG_ETHER_ON_FCC           /* define if ethernet on FCC    */
#undef  CONFIG_ETHER_NONE             /* define if ethernet on neither */
#define CONFIG_ETHER_INDEX      3     /* which SCC/FCC channel for ethernet */

#if ( CONFIG_ETHER_INDEX == 3 )

/*
 * - Rx-CLK is CLK15
 * - Tx-CLK is CLK16
 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
 * - Enable Half Duplex in FSMR
 */
# define CONFIG_SYS_CMXFCR_MASK3	(CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
# define CONFIG_SYS_CMXFCR_VALUE3	(CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
# define CONFIG_SYS_CPMFCR_RAMTYPE	0
/*#define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB) */
# define CONFIG_SYS_FCC_PSMR		0

#else /* CONFIG_ETHER_INDEX */
# error "on RPX Super ethernet must be FCC3"
#endif /* CONFIG_ETHER_INDEX */

#define CONFIG_HARD_I2C         1	/* I2C with hardware support	*/
#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/
#define CONFIG_SYS_I2C_SLAVE		0x7F


/* Define this to reserve an entire FLASH sector (256 KB) for
 * environment variables. Otherwise, the environment will be
 * put in the same sector as U-Boot, and changing variables
 * will erase U-Boot temporarily
 */
#define CONFIG_ENV_IN_OWN_SECT

/* Define to allow the user to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE

/* What should the console's baud rate be? */
#define CONFIG_BAUDRATE         115200

/* Ethernet MAC address */
#define CONFIG_ETHADDR          08:00:22:50:70:63

#define CONFIG_IPADDR		192.168.1.99
#define CONFIG_SERVERIP         192.168.1.3

/* Set to a positive value to delay for running BOOTCOMMAND */
#define CONFIG_BOOTDELAY        -1

/* undef this to save memory */
#define CONFIG_SYS_LONGHELP

/* Monitor Command Prompt       */


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_IMMAP
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_I2C
#define CONFIG_CMD_REGINFO

#undef CONFIG_CMD_KGDB


/* Where do the internal registers live? */
#define CONFIG_SYS_IMMR               0xF0000000

/* Where do the on board registers (CS4) live? */
#define CONFIG_SYS_REGS_BASE          0xFA000000

/*****************************************************************************
 *
 * You should not have to modify any of the following settings
 *
 *****************************************************************************/

#define CONFIG_MPC8260          1       /* This is an MPC8260 CPU   */
#define CONFIG_RPXSUPER         1       /* on an Embedded Planet RPX Super Board  */
#define CONFIG_CPM2		1	/* Has a CPM2 */

#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/
#define CONFIG_RESET_PHY_R	1	/* Call reset_phy()		*/

/*
 * Miscellaneous configurable options
 */
#if defined(CONFIG_CMD_KGDB)
#  define CONFIG_SYS_CBSIZE              1024       /* Console I/O Buffer Size      */
#else
#  define CONFIG_SYS_CBSIZE              256        /* Console I/O Buffer Size      */
#endif

/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE        (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)

#define CONFIG_SYS_MAXARGS       8            /* max number of command args   */

#define CONFIG_SYS_BARGSIZE      CONFIG_SYS_CBSIZE   /* Boot Argument Buffer Size    */

#define CONFIG_SYS_MEMTEST_START 0x04000000   /* memtest works on  */
#define CONFIG_SYS_MEMTEST_END   0x06000000   /* 64-96 MB in SDRAM */

#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */

#define CONFIG_SYS_LOAD_ADDR     0x100000     /* default load address */

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */

#define CONFIG_SYS_FLASH_BASE    CONFIG_SYS_FLASH0_BASE
#define CONFIG_SYS_SDRAM_BASE    CONFIG_SYS_SDRAM0_BASE

/*-----------------------------------------------------------------------
 * Hard Reset Configuration Words
 */
#if defined(CONFIG_SYS_SBC_BOOT_LOW)
#  define  CONFIG_SYS_SBC_HRCW_BOOT_FLAGS  (HRCW_CIP | HRCW_BMS)
#else
#  define  CONFIG_SYS_SBC_HRCW_BOOT_FLAGS  (0)
#endif /* defined(CONFIG_SYS_SBC_BOOT_LOW) */

/* get the HRCW ISB field from CONFIG_SYS_IMMR */
#define CONFIG_SYS_SBC_HRCW_IMMR ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) |\
			    ((CONFIG_SYS_IMMR & 0x01000000) >> 7)  |\
			    ((CONFIG_SYS_IMMR & 0x00100000) >> 4) )

#define CONFIG_SYS_HRCW_MASTER (HRCW_BPS11                           |\
			 HRCW_DPPC11                          |\
			 CONFIG_SYS_SBC_HRCW_IMMR                    |\
			 HRCW_MMR00                           |\
			 HRCW_LBPC11                          |\
			 HRCW_APPC10                          |\
			 HRCW_CS10PC00                        |\
			 (CONFIG_SYS_SBC_MODCK_H & HRCW_MODCK_H1111) |\
			 CONFIG_SYS_SBC_HRCW_BOOT_FLAGS)

/* no slaves */
#define CONFIG_SYS_HRCW_SLAVE1 0
#define CONFIG_SYS_HRCW_SLAVE2 0
#define CONFIG_SYS_HRCW_SLAVE3 0
#define CONFIG_SYS_HRCW_SLAVE4 0
#define CONFIG_SYS_HRCW_SLAVE5 0
#define CONFIG_SYS_HRCW_SLAVE6 0
#define CONFIG_SYS_HRCW_SLAVE7 0

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR       CONFIG_SYS_IMMR
#define CONFIG_SYS_INIT_RAM_SIZE        0x4000  /* Size of used area in DPRAM    */
#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent.
 */
#define CONFIG_SYS_MONITOR_BASE        (CONFIG_SYS_FLASH0_BASE + 0x00F00000)

#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#  define CONFIG_SYS_RAMBOOT
#endif

#define CONFIG_SYS_MONITOR_LEN      (256 << 10)     /* Reserve 256 kB for Monitor   */
#define CONFIG_SYS_MALLOC_LEN       (128 << 10)     /* Reserve 128 kB for malloc()  */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS   1       /* max number of memory banks         */
#define CONFIG_SYS_MAX_FLASH_SECT    71      /* max number of sectors on one chip  */

#define CONFIG_SYS_FLASH_ERASE_TOUT  8000    /* Timeout for Flash Erase (in ms)    */
#define CONFIG_SYS_FLASH_WRITE_TOUT  1       /* Timeout for Flash Write (in ms)    */

#ifndef CONFIG_SYS_RAMBOOT
#  define CONFIG_ENV_IS_IN_FLASH  1

#  ifdef CONFIG_ENV_IN_OWN_SECT
#    define CONFIG_ENV_ADDR       (CONFIG_SYS_MONITOR_BASE + 0x40000)
#    define CONFIG_ENV_SECT_SIZE  0x40000
#  else
#    define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SECT_SIZE)
#    define CONFIG_ENV_SIZE       0x1000  /* Total Size of Environment Sector */
#    define CONFIG_ENV_SECT_SIZE  0x10000 /* see README - env sect real size */
#  endif /* CONFIG_ENV_IN_OWN_SECT */
#else
#  define CONFIG_ENV_IS_IN_NVRAM  1
#  define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
#  define CONFIG_ENV_SIZE         0x200
#endif /* CONFIG_SYS_RAMBOOT */

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE      32      /* For MPC8260 CPU */

#if defined(CONFIG_CMD_KGDB)
#  define CONFIG_SYS_CACHELINE_SHIFT     5     /* log base 2 of the above value */
#endif

/*-----------------------------------------------------------------------
 * HIDx - Hardware Implementation-dependent Registers                    2-11
 *-----------------------------------------------------------------------
 * HID0 also contains cache control - initially enable both caches and
 * invalidate contents, then the final state leaves only the instruction
 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 * but Soft reset does not.
 *
 * HID1 has only read-only information - nothing to set.
 */
#define CONFIG_SYS_HID0_INIT   (/*HID0_ICE  |*/\
			 /*HID0_DCE  |*/\
			 HID0_ICFI |\
			 HID0_DCI  |\
			 HID0_IFEM |\
			 HID0_ABE)

#define CONFIG_SYS_HID0_FINAL  (/*HID0_ICE  |*/\
			 HID0_IFEM |\
			 HID0_ABE  |\
			 HID0_EMCP)
#define CONFIG_SYS_HID2        0

/*-----------------------------------------------------------------------
 * RMR - Reset Mode Register
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_RMR         0

/*-----------------------------------------------------------------------
 * BCR - Bus Configuration                                       4-25
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_BCR         (BCR_EBM   |\
			 BCR_PLDP  |\
			 BCR_EAV   |\
			 BCR_NPQM0)

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration                             4-31
 *-----------------------------------------------------------------------
 */

#define CONFIG_SYS_SIUMCR      (SIUMCR_L2CPC01 |\
			 SIUMCR_APPC10  |\
			 SIUMCR_CS10PC01)


/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control                            11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 */
#define CONFIG_SYS_SYPCR       (SYPCR_SWTC |\
			 SYPCR_BMT  |\
			 SYPCR_PBME |\
			 SYPCR_LBME |\
			 SYPCR_SWRI |\
			 SYPCR_SWP)

/*-----------------------------------------------------------------------
 * TMCNTSC - Time Counter Status and Control                     4-40
 *-----------------------------------------------------------------------
 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 * and enable Time Counter
 */
#define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC |\
			 TMCNTSC_ALR |\
			 TMCNTSC_TCF |\
			 TMCNTSC_TCE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control                 4-42
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 * Periodic timer
 */
#define CONFIG_SYS_PISCR       (PISCR_PS  |\
			 PISCR_PTF |\
			 PISCR_PTE)

/*-----------------------------------------------------------------------
 * SCCR - System Clock Control                                   9-8
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_SCCR        (SCCR_DFBRG01)

/*-----------------------------------------------------------------------
 * RCCR - RISC Controller Configuration                         13-7
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_RCCR        0

/*
 * Init Memory Controller:
 *
 * Bank Bus     Machine PortSz  Device
 * ---- ---     ------- ------  ------
 *  0   60x     GPCM    64 bit  FLASH (BGA - 16MB AMD AM29DL323DB90)
 *  1   60x     SDRAM   64 bit  SDRAM (BGA - 64MB Hitachi HM5225325FBP-B60)
 *  2   Local   SDRAM   32 bit  SDRAM (BGA - 32MB Hitachi HM5225325FBP-B60)
 *  3   unused
 *  4   60x     GPCM     8 bit  Board Regs, LEDs, switches
 *  5   unused
 *  6   unused
 *  7   unused
 *  8   PCMCIA
 *  9   unused
 * 10   unused
 * 11   unused
*/

/* Bank 0 - FLASH
 *
 */
#define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\
			 BRx_PS_64                      |\
			 BRx_DECC_NONE                  |\
			 BRx_MS_GPCM_P                  |\
			 BRx_V)

#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE)     |\
			 ORxG_CSNT                      |\
			 ORxG_ACS_DIV1                  |\
			 ORxG_SCY_6_CLK                 |\
			 ORxG_EHTR)

/* Bank 1 - SDRAM
 *
 */
#define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\
			 BRx_PS_64                      |\
			 BRx_MS_SDRAM_P                 |\
			 BRx_V)

#define CONFIG_SYS_OR1_PRELIM  (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE)     |\
			 ORxS_BPD_4                     |\
			 ORxS_ROWST_PBI0_A8             |\
			 ORxS_NUMR_12                   |\
			 ORxS_IBID)

#define CONFIG_SYS_PSDMR       0x014DA412
#define CONFIG_SYS_PSRT	0x79


/* Bank 2 - SDRAM
 *
 */
#define CONFIG_SYS_BR2_PRELIM  ((CONFIG_SYS_SDRAM1_BASE & BRx_BA_MSK) |\
			 BRx_PS_32                      |\
			 BRx_MS_SDRAM_L                 |\
			 BRx_V)

#define CONFIG_SYS_OR2_PRELIM  (MEG_TO_AM(CONFIG_SYS_SDRAM1_SIZE)     |\
			 ORxS_BPD_4                     |\
			 ORxS_ROWST_PBI0_A9             |\
			 ORxS_NUMR_12)

#define CONFIG_SYS_LSDMR       0x0169A512
#define CONFIG_SYS_LSRT	0x79

#define CONFIG_SYS_MPTPR	(0x0800 & MPTPR_PTP_MSK)

/* Bank 4 - On board registers
 *
 */
#define CONFIG_SYS_BR4_PRELIM   ((CONFIG_SYS_REGS_BASE & BRx_BA_MSK)  |\
			   BRx_PS_8                     |\
			   BRx_MS_GPCM_P                |\
			   BRx_V)

#define CONFIG_SYS_OR4_PRELIM    (ORxG_AM_MSK                 |\
			   ORxG_CSNT                   |\
			   ORxG_ACS_DIV1               |\
			   ORxG_SCY_5_CLK              |\
			   ORxG_TRLX)

#endif  /* __CONFIG_H */
Commit	Line	Data
5b1d7137 WD	1	#ifndef __CONFIG_H
	2	#define __CONFIG_H
	3
2ae18241	4	#define CONFIG_SYS_TEXT_BASE 0x80F00000
5b1d7137 WD	5
	6	/*****************************************************************************
	7	*
	8	* These settings must match the way _your_ board is set up
	9	*
	10	*****************************************************************************/
	11	/* for the AY-Revision which does not use the HRCW */
6d0f6bcf	12	#define CONFIG_SYS_DEFAULT_IMMR 0x00010000
5b1d7137 WD	13
	14	/* What is the oscillator's (UX2) frequency in Hz? */
	15	#define CONFIG_8260_CLKIN (66 * 1000 * 1000)
	16
	17	/* How is switch S2 set? We really only want the MODCK[1-3] bits, so
	18	* only the 3 least significant bits are important.
	19	*/
6d0f6bcf	20	#define CONFIG_SYS_SBC_S2 0x04
5b1d7137 WD	21
	22	/* What should MODCK_H be? It is dependent on the oscillator
	23	* frequency, MODCK[1-3], and desired CPM and core frequencies.
	24	* Some example values (all frequencies are in MHz):
	25	*
	26	* MODCK_H MODCK[1-3] Osc CPM Core
	27	* 0x2 0x2 33 133 133
	28	* 0x2 0x4 33 133 200
	29	* 0x5 0x5 66 133 133
	30	* 0x5 0x7 66 133 200
	31	*/
6d0f6bcf	32	#define CONFIG_SYS_SBC_MODCK_H 0x06
5b1d7137	33
6d0f6bcf JCPV	34	#define CONFIG_SYS_SBC_BOOT_LOW 1 /* only for HRCW */
6d0f6bcf JCPV	35	#undef CONFIG_SYS_SBC_BOOT_LOW
5b1d7137 WD	36
5b1d7137 WD	37	/* What should the base address of the main FLASH be and how big is
b30d41ca	38	* it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE.
5b1d7137 WD	39	* The main FLASH is whichever is connected to *CS0. U-Boot expects
	40	* this to be the SIMM.
	41	*/
6d0f6bcf JCPV	42	#define CONFIG_SYS_FLASH0_BASE 0x80000000
6d0f6bcf JCPV	43	#define CONFIG_SYS_FLASH0_SIZE 16
5b1d7137 WD	44
	45	/* What should the base address of the secondary FLASH be and how big
	46	* is it (in Mbytes)? The secondary FLASH is whichever is connected
	47	* to *CS6. U-Boot expects this to be the on board FLASH. If you don't
	48	* want it enabled, don't define these constants.
	49	*/
6d0f6bcf JCPV	50	#define CONFIG_SYS_FLASH1_BASE 0
	51	#define CONFIG_SYS_FLASH1_SIZE 0
	52	#undef CONFIG_SYS_FLASH1_BASE
	53	#undef CONFIG_SYS_FLASH1_SIZE
5b1d7137 WD	54
	55	/* What should be the base address of SDRAM DIMM and how big is
	56	* it (in Mbytes)?
	57	*/
6d0f6bcf JCPV	58	#define CONFIG_SYS_SDRAM0_BASE 0x00000000
6d0f6bcf JCPV	59	#define CONFIG_SYS_SDRAM0_SIZE 64
5b1d7137 WD	60
	61	/* What should be the base address of SDRAM DIMM and how big is
	62	* it (in Mbytes)?
	63	*/
6d0f6bcf JCPV	64	#define CONFIG_SYS_SDRAM1_BASE 0x04000000
6d0f6bcf JCPV	65	#define CONFIG_SYS_SDRAM1_SIZE 32
5b1d7137 WD	66
	67	/* What should be the base address of the LEDs and switch S0?
	68	* If you don't want them enabled, don't define this.
	69	*/
6d0f6bcf	70	#define CONFIG_SYS_LED_BASE 0x00000000
5b1d7137 WD	71
	72	/*
	73	* select serial console configuration
	74	*
	75	* if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
	76	* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
	77	* for SCC).
	78	*
	79	* if CONFIG_CONS_NONE is defined, then the serial console routines must
	80	* defined elsewhere.
	81	*/
	82	#define CONFIG_CONS_ON_SMC /* define if console on SMC */
	83	#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
	84	#undef CONFIG_CONS_NONE /* define if console on neither */
	85	#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */
	86
	87	/*
	88	* select ethernet configuration
	89	*
	90	* if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
	91	* CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
	92	* for FCC)
	93	*
	94	* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
639221c7	95	* defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
5b1d7137 WD	96	*/
	97	#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */
	98	#define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */
	99	#undef CONFIG_ETHER_NONE /* define if ethernet on neither */
	100	#define CONFIG_ETHER_INDEX 3 /* which SCC/FCC channel for ethernet */
	101
	102	#if ( CONFIG_ETHER_INDEX == 3 )
	103
	104	/*
	105	* - Rx-CLK is CLK15
	106	* - Tx-CLK is CLK16
	107	* - RAM for BD/Buffers is on the 60x Bus (see 28-13)
	108	* - Enable Half Duplex in FSMR
	109	*/
d4590da4 MF	110	# define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3\|CMXFCR_RF3CS_MSK\|CMXFCR_TF3CS_MSK)
d4590da4 MF	111	# define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15\|CMXFCR_TF3CS_CLK16)
6d0f6bcf JCPV	112	# define CONFIG_SYS_CPMFCR_RAMTYPE 0
	113	/#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE\|FCC_PSMR_LPB) /
	114	# define CONFIG_SYS_FCC_PSMR 0
5b1d7137 WD	115
	116	#else /* CONFIG_ETHER_INDEX */
	117	# error "on RPX Super ethernet must be FCC3"
	118	#endif /* CONFIG_ETHER_INDEX */
	119
	120	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
6d0f6bcf JCPV	121	#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
6d0f6bcf JCPV	122	#define CONFIG_SYS_I2C_SLAVE 0x7F
5b1d7137 WD	123
	124
	125	/* Define this to reserve an entire FLASH sector (256 KB) for
	126	* environment variables. Otherwise, the environment will be
	127	* put in the same sector as U-Boot, and changing variables
	128	* will erase U-Boot temporarily
	129	*/
0e8d1586	130	#define CONFIG_ENV_IN_OWN_SECT
5b1d7137 WD	131
	132	/* Define to allow the user to overwrite serial and ethaddr */
	133	#define CONFIG_ENV_OVERWRITE
	134
	135	/* What should the console's baud rate be? */
	136	#define CONFIG_BAUDRATE 115200
	137
	138	/* Ethernet MAC address */
	139	#define CONFIG_ETHADDR 08:00:22:50:70:63
	140
	141	#define CONFIG_IPADDR 192.168.1.99
	142	#define CONFIG_SERVERIP 192.168.1.3
	143
	144	/* Set to a positive value to delay for running BOOTCOMMAND */
	145	#define CONFIG_BOOTDELAY -1
	146
	147	/* undef this to save memory */
6d0f6bcf	148	#define CONFIG_SYS_LONGHELP
5b1d7137 WD	149
5b1d7137 WD	150	/* Monitor Command Prompt */
5b1d7137	151
e9a0f8f1	152
a1aa0bb5 JL	153	/*
	154	* BOOTP options
	155	*/
	156	#define CONFIG_BOOTP_BOOTFILESIZE
	157	#define CONFIG_BOOTP_BOOTPATH
	158	#define CONFIG_BOOTP_GATEWAY
	159	#define CONFIG_BOOTP_HOSTNAME
	160
	161
e9a0f8f1 JL	162	/*
	163	* Command line configuration.
	164	*/
	165	#include <config_cmd_default.h>
	166
	167	#define CONFIG_CMD_IMMAP
	168	#define CONFIG_CMD_ASKENV
	169	#define CONFIG_CMD_I2C
	170	#define CONFIG_CMD_REGINFO
	171
	172	#undef CONFIG_CMD_KGDB
	173
5b1d7137 WD	174
5b1d7137 WD	175	/* Where do the internal registers live? */
6d0f6bcf	176	#define CONFIG_SYS_IMMR 0xF0000000
5b1d7137 WD	177
5b1d7137 WD	178	/* Where do the on board registers (CS4) live? */
6d0f6bcf	179	#define CONFIG_SYS_REGS_BASE 0xFA000000
5b1d7137 WD	180
	181	/*****************************************************************************
	182	*
	183	* You should not have to modify any of the following settings
	184	*
	185	*****************************************************************************/
	186
	187	#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
	188	#define CONFIG_RPXSUPER 1 /* on an Embedded Planet RPX Super Board */
9c4c5ae3	189	#define CONFIG_CPM2 1 /* Has a CPM2 */
5b1d7137	190
c837dcb1	191	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
004eca0c	192	#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
5b1d7137	193
5b1d7137 WD	194	/*
	195	* Miscellaneous configurable options
	196	*/
e9a0f8f1	197	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	198	# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
5b1d7137	199	#else
6d0f6bcf	200	# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
5b1d7137 WD	201	#endif
	202
	203	/* Print Buffer Size */
6d0f6bcf	204	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
5b1d7137	205
6d0f6bcf	206	#define CONFIG_SYS_MAXARGS 8 /* max number of command args */
5b1d7137	207
6d0f6bcf	208	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
5b1d7137	209
6d0f6bcf JCPV	210	#define CONFIG_SYS_MEMTEST_START 0x04000000 /* memtest works on */
6d0f6bcf JCPV	211	#define CONFIG_SYS_MEMTEST_END 0x06000000 /* 64-96 MB in SDRAM */
5b1d7137 WD	212
	213	#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
	214
6d0f6bcf	215	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
5b1d7137	216
5b1d7137 WD	217	/*
	218	* Low Level Configuration Settings
	219	* (address mappings, register initial values, etc.)
	220	* You should know what you are doing if you make changes here.
	221	*/
	222
6d0f6bcf JCPV	223	#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE
6d0f6bcf JCPV	224	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM0_BASE
5b1d7137 WD	225
	226	/*-----------------------------------------------------------------------
	227	* Hard Reset Configuration Words
	228	*/
6d0f6bcf JCPV	229	#if defined(CONFIG_SYS_SBC_BOOT_LOW)
6d0f6bcf JCPV	230	# define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (HRCW_CIP \| HRCW_BMS)
5b1d7137	231	#else
6d0f6bcf JCPV	232	# define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (0)
6d0f6bcf JCPV	233	#endif /* defined(CONFIG_SYS_SBC_BOOT_LOW) */
5b1d7137	234
6d0f6bcf JCPV	235	/* get the HRCW ISB field from CONFIG_SYS_IMMR */
	236	#define CONFIG_SYS_SBC_HRCW_IMMR ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) \|\
	237	((CONFIG_SYS_IMMR & 0x01000000) >> 7) \|\
	238	((CONFIG_SYS_IMMR & 0x00100000) >> 4) )
5b1d7137	239
6d0f6bcf	240	#define CONFIG_SYS_HRCW_MASTER (HRCW_BPS11 \|\
8bde7f77	241	HRCW_DPPC11 \|\
6d0f6bcf	242	CONFIG_SYS_SBC_HRCW_IMMR \|\
8bde7f77 WD	243	HRCW_MMR00 \|\
	244	HRCW_LBPC11 \|\
	245	HRCW_APPC10 \|\
	246	HRCW_CS10PC00 \|\
6d0f6bcf JCPV	247	(CONFIG_SYS_SBC_MODCK_H & HRCW_MODCK_H1111) \|\
6d0f6bcf JCPV	248	CONFIG_SYS_SBC_HRCW_BOOT_FLAGS)
5b1d7137 WD	249
5b1d7137 WD	250	/* no slaves */
6d0f6bcf JCPV	251	#define CONFIG_SYS_HRCW_SLAVE1 0
	252	#define CONFIG_SYS_HRCW_SLAVE2 0
	253	#define CONFIG_SYS_HRCW_SLAVE3 0
	254	#define CONFIG_SYS_HRCW_SLAVE4 0
	255	#define CONFIG_SYS_HRCW_SLAVE5 0
	256	#define CONFIG_SYS_HRCW_SLAVE6 0
	257	#define CONFIG_SYS_HRCW_SLAVE7 0
5b1d7137 WD	258
	259	/*-----------------------------------------------------------------------
	260	* Definitions for initial stack pointer and data area (in DPRAM)
	261	*/
6d0f6bcf	262	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
553f0982	263	#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
25ddd1fb	264	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	265	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
5b1d7137 WD	266
	267	/*-----------------------------------------------------------------------
	268	* Start addresses for the final memory configuration
	269	* (Set up by the startup code)
6d0f6bcf JCPV	270	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
6d0f6bcf JCPV	271	* Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent.
5b1d7137	272	*/
6d0f6bcf	273	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH0_BASE + 0x00F00000)
5b1d7137	274
6d0f6bcf JCPV	275	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
6d0f6bcf JCPV	276	# define CONFIG_SYS_RAMBOOT
5b1d7137 WD	277	#endif
5b1d7137 WD	278
6d0f6bcf JCPV	279	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
6d0f6bcf JCPV	280	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
5b1d7137 WD	281
	282	/*
	283	* For booting Linux, the board info and command line data
	284	* have to be in the first 8 MB of memory, since this is
	285	* the maximum mapped by the Linux kernel during initialization.
	286	*/
6d0f6bcf	287	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
5b1d7137 WD	288
	289	/*-----------------------------------------------------------------------
	290	* FLASH and environment organization
	291	*/
6d0f6bcf JCPV	292	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
6d0f6bcf JCPV	293	#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
5b1d7137	294
6d0f6bcf JCPV	295	#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	296	#define CONFIG_SYS_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
5b1d7137	297
6d0f6bcf	298	#ifndef CONFIG_SYS_RAMBOOT
5a1aceb0	299	# define CONFIG_ENV_IS_IN_FLASH 1
5b1d7137	300
0e8d1586	301	# ifdef CONFIG_ENV_IN_OWN_SECT
6d0f6bcf	302	# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
0e8d1586	303	# define CONFIG_ENV_SECT_SIZE 0x40000
5b1d7137	304	# else
6d0f6bcf	305	# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SECT_SIZE)
0e8d1586 JCPV	306	# define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
	307	# define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */
	308	# endif /* CONFIG_ENV_IN_OWN_SECT */
5b1d7137	309	#else
9314cee6	310	# define CONFIG_ENV_IS_IN_NVRAM 1
6d0f6bcf	311	# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
0e8d1586	312	# define CONFIG_ENV_SIZE 0x200
6d0f6bcf	313	#endif /* CONFIG_SYS_RAMBOOT */
5b1d7137 WD	314
	315	/*-----------------------------------------------------------------------
	316	* Cache Configuration
	317	*/
6d0f6bcf	318	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
5b1d7137	319
e9a0f8f1	320	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	321	# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
5b1d7137 WD	322	#endif
	323
	324	/*-----------------------------------------------------------------------
	325	* HIDx - Hardware Implementation-dependent Registers 2-11
	326	*-----------------------------------------------------------------------
	327	* HID0 also contains cache control - initially enable both caches and
	328	* invalidate contents, then the final state leaves only the instruction
	329	* cache enabled. Note that Power-On and Hard reset invalidate the caches,
	330	* but Soft reset does not.
	331	*
	332	* HID1 has only read-only information - nothing to set.
	333	*/
6d0f6bcf	334	#define CONFIG_SYS_HID0_INIT (/HID0_ICE \|/\
5b1d7137 WD	335	/HID0_DCE \|/\
	336	HID0_ICFI \|\
	337	HID0_DCI \|\
	338	HID0_IFEM \|\
	339	HID0_ABE)
	340
6d0f6bcf	341	#define CONFIG_SYS_HID0_FINAL (/HID0_ICE \|/\
5b1d7137 WD	342	HID0_IFEM \|\
	343	HID0_ABE \|\
	344	HID0_EMCP)
6d0f6bcf	345	#define CONFIG_SYS_HID2 0
5b1d7137 WD	346
	347	/*-----------------------------------------------------------------------
	348	* RMR - Reset Mode Register
	349	*-----------------------------------------------------------------------
	350	*/
6d0f6bcf	351	#define CONFIG_SYS_RMR 0
5b1d7137 WD	352
	353	/*-----------------------------------------------------------------------
	354	* BCR - Bus Configuration 4-25
	355	*-----------------------------------------------------------------------
	356	*/
6d0f6bcf	357	#define CONFIG_SYS_BCR (BCR_EBM \|\
5b1d7137 WD	358	BCR_PLDP \|\
	359	BCR_EAV \|\
	360	BCR_NPQM0)
	361
	362	/*-----------------------------------------------------------------------
	363	* SIUMCR - SIU Module Configuration 4-31
	364	*-----------------------------------------------------------------------
	365	*/
	366
6d0f6bcf	367	#define CONFIG_SYS_SIUMCR (SIUMCR_L2CPC01 \|\
8bde7f77 WD	368	SIUMCR_APPC10 \|\
8bde7f77 WD	369	SIUMCR_CS10PC01)
5b1d7137 WD	370
	371
	372	/*-----------------------------------------------------------------------
	373	* SYPCR - System Protection Control 11-9
	374	* SYPCR can only be written once after reset!
	375	*-----------------------------------------------------------------------
	376	* Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
	377	*/
6d0f6bcf	378	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \|\
8bde7f77 WD	379	SYPCR_BMT \|\
	380	SYPCR_PBME \|\
	381	SYPCR_LBME \|\
	382	SYPCR_SWRI \|\
	383	SYPCR_SWP)
5b1d7137 WD	384
	385	/*-----------------------------------------------------------------------
	386	* TMCNTSC - Time Counter Status and Control 4-40
	387	*-----------------------------------------------------------------------
	388	* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
	389	* and enable Time Counter
	390	*/
6d0f6bcf	391	#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC \|\
8bde7f77 WD	392	TMCNTSC_ALR \|\
	393	TMCNTSC_TCF \|\
	394	TMCNTSC_TCE)
5b1d7137 WD	395
	396	/*-----------------------------------------------------------------------
	397	* PISCR - Periodic Interrupt Status and Control 4-42
	398	*-----------------------------------------------------------------------
	399	* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
	400	* Periodic timer
	401	*/
6d0f6bcf	402	#define CONFIG_SYS_PISCR (PISCR_PS \|\
8bde7f77 WD	403	PISCR_PTF \|\
8bde7f77 WD	404	PISCR_PTE)
5b1d7137 WD	405
	406	/*-----------------------------------------------------------------------
	407	* SCCR - System Clock Control 9-8
	408	*-----------------------------------------------------------------------
	409	*/
6d0f6bcf	410	#define CONFIG_SYS_SCCR (SCCR_DFBRG01)
5b1d7137 WD	411
	412	/*-----------------------------------------------------------------------
	413	* RCCR - RISC Controller Configuration 13-7
	414	*-----------------------------------------------------------------------
	415	*/
6d0f6bcf	416	#define CONFIG_SYS_RCCR 0
5b1d7137 WD	417
	418	/*
	419	* Init Memory Controller:
	420	*
	421	* Bank Bus Machine PortSz Device
	422	* ---- --- ------- ------ ------
	423	* 0 60x GPCM 64 bit FLASH (BGA - 16MB AMD AM29DL323DB90)
	424	* 1 60x SDRAM 64 bit SDRAM (BGA - 64MB Hitachi HM5225325FBP-B60)
	425	* 2 Local SDRAM 32 bit SDRAM (BGA - 32MB Hitachi HM5225325FBP-B60)
	426	* 3 unused
	427	* 4 60x GPCM 8 bit Board Regs, LEDs, switches
	428	* 5 unused
	429	* 6 unused
	430	* 7 unused
	431	* 8 PCMCIA
	432	* 9 unused
	433	* 10 unused
	434	* 11 unused
	435	*/
	436
	437	/* Bank 0 - FLASH
	438	*
	439	*/
6d0f6bcf	440	#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) \|\
8bde7f77	441	BRx_PS_64 \|\
5b1d7137	442	BRx_DECC_NONE \|\
8bde7f77 WD	443	BRx_MS_GPCM_P \|\
8bde7f77 WD	444	BRx_V)
5b1d7137	445
6d0f6bcf	446	#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE) \|\
8bde7f77 WD	447	ORxG_CSNT \|\
	448	ORxG_ACS_DIV1 \|\
	449	ORxG_SCY_6_CLK \|\
	450	ORxG_EHTR)
5b1d7137 WD	451
	452	/* Bank 1 - SDRAM
	453	*
	454	*/
6d0f6bcf	455	#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) \|\
8bde7f77 WD	456	BRx_PS_64 \|\
	457	BRx_MS_SDRAM_P \|\
	458	BRx_V)
5b1d7137	459
6d0f6bcf	460	#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) \|\
8bde7f77 WD	461	ORxS_BPD_4 \|\
	462	ORxS_ROWST_PBI0_A8 \|\
	463	ORxS_NUMR_12 \|\
5b1d7137 WD	464	ORxS_IBID)
5b1d7137 WD	465
6d0f6bcf JCPV	466	#define CONFIG_SYS_PSDMR 0x014DA412
6d0f6bcf JCPV	467	#define CONFIG_SYS_PSRT 0x79
5b1d7137 WD	468
	469
	470	/* Bank 2 - SDRAM
	471	*
	472	*/
6d0f6bcf	473	#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM1_BASE & BRx_BA_MSK) \|\
8bde7f77 WD	474	BRx_PS_32 \|\
	475	BRx_MS_SDRAM_L \|\
	476	BRx_V)
5b1d7137	477
6d0f6bcf	478	#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM1_SIZE) \|\
8bde7f77 WD	479	ORxS_BPD_4 \|\
	480	ORxS_ROWST_PBI0_A9 \|\
	481	ORxS_NUMR_12)
5b1d7137	482
6d0f6bcf JCPV	483	#define CONFIG_SYS_LSDMR 0x0169A512
6d0f6bcf JCPV	484	#define CONFIG_SYS_LSRT 0x79
5b1d7137	485
6d0f6bcf	486	#define CONFIG_SYS_MPTPR (0x0800 & MPTPR_PTP_MSK)
5b1d7137 WD	487
	488	/* Bank 4 - On board registers
	489	*
	490	*/
6d0f6bcf	491	#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_REGS_BASE & BRx_BA_MSK) \|\
8bde7f77 WD	492	BRx_PS_8 \|\
	493	BRx_MS_GPCM_P \|\
	494	BRx_V)
5b1d7137	495
6d0f6bcf	496	#define CONFIG_SYS_OR4_PRELIM (ORxG_AM_MSK \|\
8bde7f77 WD	497	ORxG_CSNT \|\
	498	ORxG_ACS_DIV1 \|\
	499	ORxG_SCY_5_CLK \|\
	500	ORxG_TRLX)
5b1d7137	501
5b1d7137	502	#endif /* __CONFIG_H */