[people/ms/u-boot.git] / include / configs / Rattler.h

/*
 * Copyright (C) 2004 Arabella Software Ltd.
 * Yuli Barcohen <yuli@arabellasw.com>
 *
 * U-Boot configuration for Analogue&Micro Rattler boards.
 *
 * SPDX-License-Identifier:	GPL-2.0+ 
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#ifdef CONFIG_MPC8248
#define CPU_ID_STR		"MPC8248"
#else
#define CONFIG_MPC8260
#define CPU_ID_STR		"MPC8250"
#endif /* CONFIG_MPC8248 */

#define	CONFIG_SYS_TEXT_BASE	0xFE000000

#define CONFIG_CPM2		1	/* Has a CPM2 */

#define CONFIG_RATTLER			/* Analogue&Micro Rattler board */

/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
#define CONFIG_ENV_OVERWRITE

/*
 * Select serial console configuration
 *
 * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
 * for SCC).
 */
#define	CONFIG_CONS_ON_SMC		/* Console is on SMC         */
#undef  CONFIG_CONS_ON_SCC		/* It's not on SCC           */
#undef	CONFIG_CONS_NONE		/* It's not on external UART */
#define CONFIG_CONS_INDEX	1	/* SMC1 is used for console  */

/*
 * Select ethernet configuration
 *
 * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
 * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
 * SCC, 1-3 for FCC)
 *
 * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
 * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
 * must be unset.
 */
#undef	CONFIG_ETHER_ON_SCC		/* Ethernet is not on SCC */
#define CONFIG_ETHER_ON_FCC		/* Ethernet is on FCC     */
#undef	CONFIG_ETHER_NONE		/* No external Ethernet   */

#ifdef CONFIG_ETHER_ON_FCC

#define CONFIG_ETHER_INDEX	1	/* FCC1 is used for Ethernet */

#if   (CONFIG_ETHER_INDEX == 1)

/* - Rx clock is CLK11
 * - Tx clock is CLK10
 * - BDs/buffers on 60x bus
 * - Full duplex
 */
#define CONFIG_SYS_CMXFCR_MASK1		(CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
#define CONFIG_SYS_CMXFCR_VALUE1	(CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK10)
#define CONFIG_SYS_CPMFCR_RAMTYPE	0
#define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)

#elif (CONFIG_ETHER_INDEX == 2)

/* - Rx clock is CLK15
 * - Tx clock is CLK14
 * - BDs/buffers on 60x bus
 * - Full duplex
 */
#define CONFIG_SYS_CMXFCR_MASK2		(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
#define CONFIG_SYS_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK14)
#define CONFIG_SYS_CPMFCR_RAMTYPE	0
#define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)

#endif /* CONFIG_ETHER_INDEX */

#define CONFIG_MII			/* MII PHY management        */
#define CONFIG_BITBANGMII		/* Bit-banged MDIO interface */
/*
 * GPIO pins used for bit-banged MII communications
 */
#define MDIO_PORT		2	/* Port C */
#define MDIO_DECLARE		volatile ioport_t *iop = ioport_addr ( \
					(immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
#define MDC_DECLARE		MDIO_DECLARE

#define MDIO_ACTIVE		(iop->pdir |=  0x00400000)
#define MDIO_TRISTATE		(iop->pdir &= ~0x00400000)
#define MDIO_READ		((iop->pdat &  0x00400000) != 0)

#define MDIO(bit)		if(bit) iop->pdat |=  0x00400000; \
				else	iop->pdat &= ~0x00400000

#define MDC(bit)		if(bit) iop->pdat |=  0x00800000; \
				else	iop->pdat &= ~0x00800000

#define MIIDELAY		udelay(1)

#endif /* CONFIG_ETHER_ON_FCC */

#ifndef CONFIG_8260_CLKIN
#define CONFIG_8260_CLKIN	100000000	/* in Hz */
#endif

#define CONFIG_BAUDRATE		38400


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_DHCP
#define CONFIG_CMD_IMMAP
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING


#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
#define CONFIG_BOOTCOMMAND	"bootm FE040000"	/* autoboot command */
#define CONFIG_BOOTARGS		"root=/dev/mtdblock2 rw mtdparts=phys:1M(ROM)ro,-(root)"

#if defined(CONFIG_CMD_KGDB)
#undef	CONFIG_KGDB_ON_SMC		/* define if kgdb on SMC */
#define CONFIG_KGDB_ON_SCC		/* define if kgdb on SCC */
#undef	CONFIG_KGDB_NONE		/* define if kgdb on something else */
#define CONFIG_KGDB_INDEX	2	/* which serial channel for kgdb */
#define CONFIG_KGDB_BAUDRATE	115200	/* speed to run kgdb serial port at */
#endif

#define CONFIG_BZIP2	/* include support for bzip2 compressed images */
#undef	CONFIG_WATCHDOG			/* disable platform specific watchdog */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
#else
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size  */
#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size  */

#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/

#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */

#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */

#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }

#define CONFIG_SYS_FLASH_BASE		0xFE000000
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of flash banks	*/
#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max num of sects on one chip */

#define	CONFIG_SYS_DIRECT_FLASH_TFTP

#if defined(CONFIG_CMD_JFFS2)
#define CONFIG_SYS_JFFS2_NUM_BANKS	CONFIG_SYS_MAX_FLASH_BANKS
#define CONFIG_SYS_JFFS2_SORT_FRAGMENTS

/*
 * JFFS2 partitions
 *
 */
/* No command line, one static partition */
#undef CONFIG_CMD_MTDPARTS
#define CONFIG_JFFS2_DEV		"nor0"
#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
#define CONFIG_JFFS2_PART_OFFSET	0x00100000

/* mtdparts command line support */
/* Note: fake mtd_id used, no linux mtd map file */
/*
#define CONFIG_CMD_MTDPARTS
#define MTDIDS_DEFAULT		"nor0=rattler-0"
#define MTDPARTS_DEFAULT	"mtdparts=rattler-0:-@1m(jffs2)"
*/
#endif /* CONFIG_CMD_JFFS2 */

#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#endif

#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/

#define CONFIG_ENV_IS_IN_FLASH

#ifdef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE	0x10000
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#endif /* CONFIG_ENV_IS_IN_FLASH */

#define CONFIG_SYS_DEFAULT_IMMR	0xFF010000

#define CONFIG_SYS_IMMR		0xF0000000

#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
#define CONFIG_SYS_INIT_RAM_SIZE	0x2000	/* Size of used area in DPRAM	*/
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_SDRAM_SIZE		32
#define CONFIG_SYS_SDRAM_BR		(CONFIG_SYS_SDRAM_BASE | 0x00000041)
#define CONFIG_SYS_SDRAM_OR		0xFE002EC0

#define CONFIG_SYS_BCSR		0xFC000000

/* Hard reset configuration word */
#define CONFIG_SYS_HRCW_MASTER		0x0A06875A /* Not used - provided by FPGA */
/* No slaves */
#define CONFIG_SYS_HRCW_SLAVE1		0
#define CONFIG_SYS_HRCW_SLAVE2		0
#define CONFIG_SYS_HRCW_SLAVE3		0
#define CONFIG_SYS_HRCW_SLAVE4		0
#define CONFIG_SYS_HRCW_SLAVE5		0
#define CONFIG_SYS_HRCW_SLAVE6		0
#define CONFIG_SYS_HRCW_SLAVE7		0

#define CONFIG_SYS_MALLOC_LEN		(4096 << 10)	/* Reserve 4 MB for malloc()	*/
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8260 CPUs */
#if defined(CONFIG_CMD_KGDB)
#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif

#define CONFIG_SYS_HID0_INIT		0
#define CONFIG_SYS_HID0_FINAL		(HID0_ICE | HID0_IFEM | HID0_ABE)

#define CONFIG_SYS_HID2		0

#define CONFIG_SYS_SIUMCR		0x0E04C000
#define CONFIG_SYS_SYPCR		0xFFFFFFC3
#define CONFIG_SYS_BCR			0x00000000
#define CONFIG_SYS_SCCR		SCCR_DFBRG01

#define CONFIG_SYS_RMR			RMR_CSRE
#define CONFIG_SYS_TMCNTSC		(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
#define CONFIG_SYS_PISCR		(PISCR_PS|PISCR_PTF|PISCR_PTE)
#define CONFIG_SYS_RCCR		0

#define CONFIG_SYS_PSDMR		0x8249A452
#define CONFIG_SYS_PSRT		0x1F
#define CONFIG_SYS_MPTPR		0x2000

#define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE | 0x00001001)
#define CONFIG_SYS_OR0_PRELIM		0xFF001ED6
#define CONFIG_SYS_BR7_PRELIM		(CONFIG_SYS_BCSR | 0x00000801)
#define CONFIG_SYS_OR7_PRELIM		0xFFFF87F6

#define CONFIG_SYS_RESET_ADDRESS	0xC0000000

#endif /* __CONFIG_H */
Commit	Line	Data
8b0bfc68 WD	1	/*
	2	* Copyright (C) 2004 Arabella Software Ltd.
	3	* Yuli Barcohen <yuli@arabellasw.com>
	4	*
	5	* U-Boot configuration for Analogue&Micro Rattler boards.
	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
8b0bfc68 WD	8	*/
	9
	10	#ifndef __CONFIG_H
	11	#define __CONFIG_H
	12
	13	#ifdef CONFIG_MPC8248
	14	#define CPU_ID_STR "MPC8248"
	15	#else
	16	#define CONFIG_MPC8260
	17	#define CPU_ID_STR "MPC8250"
	18	#endif /* CONFIG_MPC8248 */
	19
2ae18241 WD	20	#define CONFIG_SYS_TEXT_BASE 0xFE000000
2ae18241 WD	21
9c4c5ae3 JL	22	#define CONFIG_CPM2 1 /* Has a CPM2 */
9c4c5ae3 JL	23
8b0bfc68 WD	24	#define CONFIG_RATTLER /* Analogue&Micro Rattler board */
8b0bfc68 WD	25
8b0bfc68 WD	26	/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
	27	#define CONFIG_ENV_OVERWRITE
	28
	29	/*
	30	* Select serial console configuration
	31	*
	32	* If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
	33	* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
	34	* for SCC).
	35	*/
	36	#define CONFIG_CONS_ON_SMC /* Console is on SMC */
	37	#undef CONFIG_CONS_ON_SCC /* It's not on SCC */
	38	#undef CONFIG_CONS_NONE /* It's not on external UART */
	39	#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */
	40
	41	/*
	42	* Select ethernet configuration
	43	*
	44	* If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
	45	* then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
	46	* SCC, 1-3 for FCC)
	47	*
	48	* If CONFIG_ETHER_NONE is defined, then either the ethernet routines
639221c7 JL	49	* must be defined elsewhere (as for the console), or CONFIG_CMD_NET
639221c7 JL	50	* must be unset.
8b0bfc68 WD	51	*/
	52	#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */
	53	#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */
	54	#undef CONFIG_ETHER_NONE /* No external Ethernet */
	55
	56	#ifdef CONFIG_ETHER_ON_FCC
	57
	58	#define CONFIG_ETHER_INDEX 1 /* FCC1 is used for Ethernet */
	59
	60	#if (CONFIG_ETHER_INDEX == 1)
	61
	62	/* - Rx clock is CLK11
	63	* - Tx clock is CLK10
	64	* - BDs/buffers on 60x bus
	65	* - Full duplex
	66	*/
d4590da4 MF	67	#define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1 \| CMXFCR_RF1CS_MSK \| CMXFCR_TF1CS_MSK)
d4590da4 MF	68	#define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11 \| CMXFCR_TF1CS_CLK10)
6d0f6bcf JCPV	69	#define CONFIG_SYS_CPMFCR_RAMTYPE 0
6d0f6bcf JCPV	70	#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE \| FCC_PSMR_LPB)
8b0bfc68 WD	71
	72	#elif (CONFIG_ETHER_INDEX == 2)
	73
	74	/* - Rx clock is CLK15
	75	* - Tx clock is CLK14
	76	* - BDs/buffers on 60x bus
	77	* - Full duplex
	78	*/
d4590da4 MF	79	#define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 \| CMXFCR_RF2CS_MSK \| CMXFCR_TF2CS_MSK)
d4590da4 MF	80	#define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK15 \| CMXFCR_TF2CS_CLK14)
6d0f6bcf JCPV	81	#define CONFIG_SYS_CPMFCR_RAMTYPE 0
6d0f6bcf JCPV	82	#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE \| FCC_PSMR_LPB)
8b0bfc68 WD	83
	84	#endif /* CONFIG_ETHER_INDEX */
	85
	86	#define CONFIG_MII /* MII PHY management */
	87	#define CONFIG_BITBANGMII /* Bit-banged MDIO interface */
	88	/*
	89	* GPIO pins used for bit-banged MII communications
	90	*/
	91	#define MDIO_PORT 2 /* Port C */
be225442 LCM	92	#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
	93	(immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
	94	#define MDC_DECLARE MDIO_DECLARE
	95
8b0bfc68 WD	96	#define MDIO_ACTIVE (iop->pdir \|= 0x00400000)
	97	#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
	98	#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
	99
	100	#define MDIO(bit) if(bit) iop->pdat \|= 0x00400000; \
	101	else iop->pdat &= ~0x00400000
	102
	103	#define MDC(bit) if(bit) iop->pdat \|= 0x00800000; \
	104	else iop->pdat &= ~0x00800000
	105
	106	#define MIIDELAY udelay(1)
	107
	108	#endif /* CONFIG_ETHER_ON_FCC */
	109
	110	#ifndef CONFIG_8260_CLKIN
	111	#define CONFIG_8260_CLKIN 100000000 /* in Hz */
	112	#endif
	113
	114	#define CONFIG_BAUDRATE 38400
	115
8b0bfc68	116
a1aa0bb5 JL	117	/*
	118	* BOOTP options
	119	*/
	120	#define CONFIG_BOOTP_BOOTFILESIZE
	121	#define CONFIG_BOOTP_BOOTPATH
	122	#define CONFIG_BOOTP_GATEWAY
	123	#define CONFIG_BOOTP_HOSTNAME
	124
	125
e9a0f8f1 JL	126	/*
	127	* Command line configuration.
	128	*/
	129	#include <config_cmd_default.h>
	130
	131	#define CONFIG_CMD_DHCP
	132	#define CONFIG_CMD_IMMAP
	133	#define CONFIG_CMD_JFFS2
	134	#define CONFIG_CMD_MII
	135	#define CONFIG_CMD_PING
	136
8b0bfc68 WD	137
	138	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	139	#define CONFIG_BOOTCOMMAND "bootm FE040000" /* autoboot command */
	140	#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw mtdparts=phys:1M(ROM)ro,-(root)"
	141
e9a0f8f1	142	#if defined(CONFIG_CMD_KGDB)
8b0bfc68 WD	143	#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
	144	#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
	145	#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
	146	#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
	147	#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
	148	#endif
	149
	150	#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
	151	#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
	152
	153	/*
	154	* Miscellaneous configurable options
	155	*/
6d0f6bcf	156	#define CONFIG_SYS_HUSH_PARSER
6d0f6bcf JCPV	157	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	158	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
e9a0f8f1	159	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	160	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
8b0bfc68	161	#else
6d0f6bcf	162	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
8b0bfc68	163	#endif
6d0f6bcf JCPV	164	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	165	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	166	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
8b0bfc68	167
6d0f6bcf JCPV	168	#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
6d0f6bcf JCPV	169	#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
8b0bfc68	170
6d0f6bcf	171	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
8b0bfc68	172
6d0f6bcf	173	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
8b0bfc68	174
6d0f6bcf	175	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
8b0bfc68	176
6d0f6bcf JCPV	177	#define CONFIG_SYS_FLASH_BASE 0xFE000000
6d0f6bcf JCPV	178	#define CONFIG_SYS_FLASH_CFI
00b1883a	179	#define CONFIG_FLASH_CFI_DRIVER
6d0f6bcf JCPV	180	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
6d0f6bcf JCPV	181	#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
8b0bfc68	182
6d0f6bcf	183	#define CONFIG_SYS_DIRECT_FLASH_TFTP
8b0bfc68	184
e9a0f8f1	185	#if defined(CONFIG_CMD_JFFS2)
6d0f6bcf JCPV	186	#define CONFIG_SYS_JFFS2_NUM_BANKS CONFIG_SYS_MAX_FLASH_BANKS
6d0f6bcf JCPV	187	#define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
700a0c64 WD	188
	189	/*
	190	* JFFS2 partitions
	191	*
	192	*/
	193	/* No command line, one static partition */
68d7d651	194	#undef CONFIG_CMD_MTDPARTS
700a0c64 WD	195	#define CONFIG_JFFS2_DEV "nor0"
	196	#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
	197	#define CONFIG_JFFS2_PART_OFFSET 0x00100000
	198
	199	/* mtdparts command line support */
	200	/* Note: fake mtd_id used, no linux mtd map file */
	201	/*
68d7d651	202	#define CONFIG_CMD_MTDPARTS
700a0c64 WD	203	#define MTDIDS_DEFAULT "nor0=rattler-0"
	204	#define MTDPARTS_DEFAULT "mtdparts=rattler-0:-@1m(jffs2)"
	205	*/
a1aa0bb5	206	#endif /* CONFIG_CMD_JFFS2 */
8b0bfc68	207
14d0a02a	208	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
6d0f6bcf JCPV	209	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
6d0f6bcf JCPV	210	#define CONFIG_SYS_RAMBOOT
8b0bfc68 WD	211	#endif
8b0bfc68 WD	212
6d0f6bcf	213	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
8b0bfc68	214
5a1aceb0	215	#define CONFIG_ENV_IS_IN_FLASH
8b0bfc68	216
5a1aceb0	217	#ifdef CONFIG_ENV_IS_IN_FLASH
0e8d1586	218	#define CONFIG_ENV_SECT_SIZE 0x10000
6d0f6bcf	219	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
5a1aceb0	220	#endif /* CONFIG_ENV_IS_IN_FLASH */
8b0bfc68	221
6d0f6bcf	222	#define CONFIG_SYS_DEFAULT_IMMR 0xFF010000
8b0bfc68	223
6d0f6bcf	224	#define CONFIG_SYS_IMMR 0xF0000000
8b0bfc68	225
6d0f6bcf	226	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
553f0982	227	#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */
25ddd1fb	228	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	229	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
8b0bfc68	230
6d0f6bcf JCPV	231	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	232	#define CONFIG_SYS_SDRAM_SIZE 32
	233	#define CONFIG_SYS_SDRAM_BR (CONFIG_SYS_SDRAM_BASE \| 0x00000041)
	234	#define CONFIG_SYS_SDRAM_OR 0xFE002EC0
8b0bfc68	235
6d0f6bcf	236	#define CONFIG_SYS_BCSR 0xFC000000
8b0bfc68 WD	237
8b0bfc68 WD	238	/* Hard reset configuration word */
6d0f6bcf	239	#define CONFIG_SYS_HRCW_MASTER 0x0A06875A /* Not used - provided by FPGA */
8b0bfc68	240	/* No slaves */
6d0f6bcf JCPV	241	#define CONFIG_SYS_HRCW_SLAVE1 0
	242	#define CONFIG_SYS_HRCW_SLAVE2 0
	243	#define CONFIG_SYS_HRCW_SLAVE3 0
	244	#define CONFIG_SYS_HRCW_SLAVE4 0
	245	#define CONFIG_SYS_HRCW_SLAVE5 0
	246	#define CONFIG_SYS_HRCW_SLAVE6 0
	247	#define CONFIG_SYS_HRCW_SLAVE7 0
8b0bfc68	248
6d0f6bcf JCPV	249	#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
6d0f6bcf JCPV	250	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
8b0bfc68	251
6d0f6bcf	252	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
e9a0f8f1	253	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	254	# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
8b0bfc68 WD	255	#endif
8b0bfc68 WD	256
6d0f6bcf JCPV	257	#define CONFIG_SYS_HID0_INIT 0
6d0f6bcf JCPV	258	#define CONFIG_SYS_HID0_FINAL (HID0_ICE \| HID0_IFEM \| HID0_ABE)
8b0bfc68	259
6d0f6bcf	260	#define CONFIG_SYS_HID2 0
8b0bfc68	261
6d0f6bcf JCPV	262	#define CONFIG_SYS_SIUMCR 0x0E04C000
	263	#define CONFIG_SYS_SYPCR 0xFFFFFFC3
	264	#define CONFIG_SYS_BCR 0x00000000
	265	#define CONFIG_SYS_SCCR SCCR_DFBRG01
8b0bfc68	266
6d0f6bcf JCPV	267	#define CONFIG_SYS_RMR RMR_CSRE
	268	#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC\|TMCNTSC_ALR\|TMCNTSC_TCF\|TMCNTSC_TCE)
	269	#define CONFIG_SYS_PISCR (PISCR_PS\|PISCR_PTF\|PISCR_PTE)
	270	#define CONFIG_SYS_RCCR 0
8b0bfc68	271
6d0f6bcf JCPV	272	#define CONFIG_SYS_PSDMR 0x8249A452
	273	#define CONFIG_SYS_PSRT 0x1F
	274	#define CONFIG_SYS_MPTPR 0x2000
8b0bfc68	275
6d0f6bcf JCPV	276	#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \| 0x00001001)
	277	#define CONFIG_SYS_OR0_PRELIM 0xFF001ED6
	278	#define CONFIG_SYS_BR7_PRELIM (CONFIG_SYS_BCSR \| 0x00000801)
	279	#define CONFIG_SYS_OR7_PRELIM 0xFFFF87F6
8b0bfc68	280
6d0f6bcf	281	#define CONFIG_SYS_RESET_ADDRESS 0xC0000000
8b0bfc68 WD	282
8b0bfc68 WD	283	#endif /* __CONFIG_H */